337 lines
12 KiB
C
337 lines
12 KiB
C
/*-
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* Copyright (c) 2003-2009 RMI Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of RMI Corporation, nor the names of its contributors,
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RMI_BSD */
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#ifndef XLRCONFIG_H
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#define XLRCONFIG_H
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#include <sys/types.h>
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#include <mips/rmi/shared_structs.h>
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#include <mips/rmi/shared_structs_func.h>
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#define read_c0_register32(reg, sel) \
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({ unsigned int __rv; \
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__asm__ __volatile__( \
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".set\tpush\n\t" \
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".set mips32\n\t" \
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"mfc0\t%0,$%1,%2\n\t" \
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".set\tpop" \
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: "=r" (__rv) : "i" (reg), "i" (sel) ); \
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__rv;})
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#define write_c0_register32(reg, sel, value) \
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__asm__ __volatile__( \
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".set\tpush\n\t" \
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".set mips32\n\t" \
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"mtc0\t%0,$%1,%2\n\t" \
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".set\tpop" \
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: : "r" (value), "i" (reg), "i" (sel) );
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#define read_c0_register64(reg, sel) \
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({ unsigned int __high, __low; \
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__asm__ __volatile__( \
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".set\tpush\n\t" \
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".set mips64\n\t" \
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"dmfc0\t $8, $%2, %3\n\t" \
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"dsrl32\t%0, $8, 0\n\t" \
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"dsll32\t$8, $8, 0\n\t" \
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"dsrl32\t%1, $8, 0\n\t" \
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".set\tpop" \
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: "=r"(__high), "=r"(__low): "i"(reg), "i"(sel): "$8" );\
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(((unsigned long long)__high << 32) | __low);})
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#define write_c0_register64(reg, sel, value) \
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do{ \
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unsigned int __high = val>>32; \
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unsigned int __low = val & 0xffffffff; \
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__asm__ __volatile__( \
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".set\tpush\n\t" \
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".set mips64\n\t" \
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"dsll32\t$8, %1, 0\n\t" \
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"dsll32\t$9, %0, 0\n\t" \
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"or\t $8, $8, $9\n\t" \
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"dmtc0\t $8, $%2, %3\n\t" \
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".set\tpop" \
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:: "r"(high), "r"(low), "i"(reg), "i"(sel):"$8", "$9");\
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} while(0)
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#define read_c2_register32(reg, sel) \
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({ unsigned int __rv; \
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__asm__ __volatile__( \
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".set\tpush\n\t" \
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".set mips32\n\t" \
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"mfc2\t%0,$%1,%2\n\t" \
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".set\tpop" \
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: "=r" (__rv) : "i" (reg), "i" (sel) ); \
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__rv;})
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#define write_c2_register32(reg, sel, value) \
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__asm__ __volatile__( \
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".set\tpush\n\t" \
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".set mips32\n\t" \
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"mtc2\t%0,$%1,%2\n\t" \
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".set\tpop" \
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: : "r" (value), "i" (reg), "i" (sel) );
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#define read_c2_register64(reg, sel) \
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({ unsigned int __high, __low; \
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__asm__ __volatile__( \
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".set mips64\n\t" \
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"dmfc2\t $8, $%2, %3\n\t" \
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"dsrl32\t%0, $8, 0\n\t" \
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"dsll32\t$8, $8, 0\n\t" \
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"dsrl32\t%1, $8, 0\n\t" \
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".set\tmips0" \
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: "=r"(__high), "=r"(__low): "i"(reg), "i"(sel): "$8" );\
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(((unsigned long long)__high << 32) | __low);})
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#define write_c2_register64(reg, sel, value) \
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do{ \
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unsigned int __high = value>>32; \
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unsigned int __low = value & 0xffffffff; \
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__asm__ __volatile__( \
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".set mips64\n\t" \
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"dsll32\t$8, %1, 0\n\t" \
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"dsll32\t$9, %0, 0\n\t" \
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"dsrl32\t$8, $8, 0\n\t" \
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"or\t $8, $8, $9\n\t" \
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"dmtc2\t $8, $%2, %3\n\t" \
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".set\tmips0" \
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:: "r"(__high), "r"(__low), \
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"i"(reg), "i"(sel) \
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:"$8", "$9"); \
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} while(0)
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#if 0
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#define xlr_processor_id() \
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({int __id; \
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__asm__ __volatile__ ( \
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".set push\n" \
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".set noreorder\n" \
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".word 0x40088007\n" \
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"srl $8, $8, 10\n" \
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"andi %0, $8, 0x3f\n" \
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".set pop\n" \
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: "=r" (__id) : : "$8"); \
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__id;})
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#endif
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#define xlr_cpu_id() \
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({int __id; \
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__asm__ __volatile__ ( \
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".set push\n" \
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".set noreorder\n" \
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".word 0x40088007\n" \
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"srl $8, $8, 4\n" \
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"andi %0, $8, 0x7\n" \
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".set pop\n" \
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: "=r" (__id) : : "$8"); \
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__id;})
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#define xlr_thr_id() \
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({int __id; \
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__asm__ __volatile__ ( \
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".set push\n" \
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".set noreorder\n" \
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".word 0x40088007\n" \
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"andi %0, $8, 0x03\n" \
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".set pop\n" \
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: "=r" (__id) : : "$8"); \
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__id;})
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/* Additional registers on the XLR */
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#define MIPS_COP_0_OSSCRATCH 22
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#define XLR_CACHELINE_SIZE 32
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#define XLR_MAX_CORES 8
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/* functions to write to and read from the extended
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* cp0 registers.
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* EIRR : Extended Interrupt Request Register
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* cp0 register 9 sel 6
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* bits 0...7 are same as cause register 8...15
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* EIMR : Extended Interrupt Mask Register
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* cp0 register 9 sel 7
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* bits 0...7 are same as status register 8...15
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*/
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static inline uint64_t
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read_c0_eirr64(void)
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{
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__uint32_t high, low;
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__asm__ __volatile__(
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".set push\n"
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".set noreorder\n"
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".set noat\n"
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".set mips4\n"
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".word 0x40214806 \n\t"
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"nop \n\t"
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"dsra32 %0, $1, 0 \n\t"
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"sll %1, $1, 0 \n\t"
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".set pop\n"
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: "=r"(high), "=r"(low)
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);
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return (((__uint64_t) high) << 32) | low;
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}
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static inline __uint64_t
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read_c0_eimr64(void)
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{
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__uint32_t high, low;
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__asm__ __volatile__(
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".set push\n"
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".set noreorder\n"
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".set noat\n"
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".set mips4\n"
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".word 0x40214807 \n\t"
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"nop \n\t"
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"dsra32 %0, $1, 0 \n\t"
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"sll %1, $1, 0 \n\t"
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".set pop\n"
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: "=r"(high), "=r"(low)
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);
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return (((__uint64_t) high) << 32) | low;
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}
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static inline void
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write_c0_eirr64(__uint64_t value)
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{
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__uint32_t low, high;
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high = value >> 32;
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low = value & 0xffffffff;
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__asm__ __volatile__(
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".set push\n"
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".set noreorder\n"
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".set noat\n"
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".set mips4\n\t"
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"dsll32 $2, %1, 0 \n\t"
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"dsll32 $1, %0, 0 \n\t"
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"dsrl32 $2, $2, 0 \n\t"
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"or $1, $1, $2 \n\t"
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".word 0x40a14806 \n\t"
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"nop \n\t"
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".set pop\n"
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:
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: "r"(high), "r"(low)
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: "$1", "$2");
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}
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static inline void
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write_c0_eimr64(__uint64_t value)
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{
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__uint32_t low, high;
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high = value >> 32;
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low = value & 0xffffffff;
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__asm__ __volatile__(
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".set push\n"
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".set noreorder\n"
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".set noat\n"
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".set mips4\n\t"
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"dsll32 $2, %1, 0 \n\t"
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"dsll32 $1, %0, 0 \n\t"
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"dsrl32 $2, $2, 0 \n\t"
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"or $1, $1, $2 \n\t"
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".word 0x40a14807 \n\t"
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"nop \n\t"
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".set pop\n"
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:
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: "r"(high), "r"(low)
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: "$1", "$2");
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}
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static __inline__ int
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xlr_test_and_set(int *lock)
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{
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int oldval = 0;
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__asm__ __volatile__(".set push\n"
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".set noreorder\n"
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"move $9, %2\n"
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"li $8, 1\n"
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// "swapw $8, $9\n"
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".word 0x71280014\n"
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"move %1, $8\n"
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".set pop\n"
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: "+m"(*lock), "=r"(oldval)
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: "r"((unsigned long)lock)
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: "$8", "$9"
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);
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return (oldval == 0 ? 1 /* success */ : 0 /* failure */ );
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}
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static __inline__ uint32_t
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xlr_mfcr(uint32_t reg)
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{
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uint32_t val;
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__asm__ __volatile__(
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"move $8, %1\n"
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".word 0x71090018\n"
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"move %0, $9\n"
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: "=r"(val)
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: "r"(reg):"$8", "$9");
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return val;
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}
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static __inline__ void
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xlr_mtcr(uint32_t reg, uint32_t val)
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{
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__asm__ __volatile__(
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"move $8, %1\n"
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"move $9, %0\n"
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".word 0x71090019\n"
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:: "r"(val), "r"(reg)
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: "$8", "$9");
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}
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#endif
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