ca950537bb
On XLP evaluation platform, the board information is stored in an I2C eeprom and the network block configuration is available from a CPLD connected to the GBU (NOR flash bus). Add support for both of these.
114 lines
3.0 KiB
C
114 lines
3.0 KiB
C
/*-
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* Copyright (c) 2003-2012 Broadcom Corporation
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/endian.h>
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#include <mips/nlm/hal/mips-extns.h>
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#include <mips/nlm/hal/haldefs.h>
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#include <mips/nlm/hal/iomap.h>
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#include <mips/nlm/hal/gbu.h>
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#include <mips/nlm/board.h>
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#define CPLD_REVISION 0x0
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#define CPLD_RESET 0x1
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#define CPLD_CTRL 0x2
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#define CPLD_RSVD 0x3
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#define CPLD_PWR_CTRL 0x4
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#define CPLD_MISC 0x5
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#define CPLD_CTRL_STATUS 0x6
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#define CPLD_PWR_INTR_STATUS 0x7
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#define CPLD_DATA 0x8
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static __inline
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int nlm_cpld_read(uint64_t base, int reg)
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{
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uint16_t val;
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val = *(volatile uint16_t *)(long)(base + reg * 2);
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return bswap16(val);
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}
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static __inline void
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nlm_cpld_write(uint64_t base, int reg, uint16_t data)
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{
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bswap16(data);
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*(volatile uint16_t *)(long)(base + reg * 2) = data;
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}
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int
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nlm_board_cpld_majorversion(uint64_t base)
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{
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return (nlm_cpld_read(base, CPLD_REVISION) >> 8);
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}
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int
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nlm_board_cpld_minorversion(uint64_t base)
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{
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return (nlm_cpld_read(base, CPLD_REVISION) & 0xff);
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}
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uint64_t nlm_board_cpld_base(int node, int chipselect)
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{
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uint64_t gbubase, cpld_phys;
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gbubase = nlm_get_gbu_regbase(node);
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cpld_phys = nlm_read_gbu_reg(gbubase, GBU_CS_BASEADDR(chipselect));
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return (MIPS_PHYS_TO_KSEG1(cpld_phys << 8));
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}
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void
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nlm_board_cpld_reset(uint64_t base)
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{
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nlm_cpld_write(base, CPLD_RESET, 1 << 15);
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for(;;)
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__asm __volatile("wait");
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}
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/* get daughter board type */
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int
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nlm_board_cpld_dboard_type(uint64_t base, int slot)
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{
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uint16_t val;
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int shift = 0;
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switch (slot) {
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case 0: shift = 0; break;
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case 1: shift = 4; break;
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case 2: shift = 2; break;
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case 3: shift = 6; break;
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}
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val = nlm_cpld_read(base, CPLD_CTRL_STATUS) >> shift;
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return (val & 0x3);
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}
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