3a6a9a3bcc
from the git tree. This merges a lot that we're not using, but there's too many files to be selective and have a hope of catching everything. If there are conflicts with the rest of the tree, we'll resolve them on a case by case basis. MFC after: 2 weeks Sponsored by: Netflix, Inc.
114 lines
2.6 KiB
Plaintext
114 lines
2.6 KiB
Plaintext
/*
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* Copyright 2012 Sascha Hauer, Pengutronix
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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#include "imx25.dtsi"
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/ {
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model = "Ka-Ro TX25";
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compatible = "karo,imx25-tx25", "fsl,imx25";
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chosen {
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stdout-path = &uart1;
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_fec_phy: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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regulator-name = "fec-phy";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio4 9 0>;
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enable-active-high;
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};
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};
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memory {
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reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
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};
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};
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&iomuxc {
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
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MX25_PAD_UART1_RXD__UART1_RXD 0x80000000
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MX25_PAD_UART1_CTS__UART1_CTS 0x80000000
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MX25_PAD_UART1_RTS__UART1_RTS 0x80000000
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>;
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};
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pinctrl_fec: fecgrp {
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fsl,pins = <
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MX25_PAD_D11__GPIO_4_9 0x80000000 /* FEC PHY power on pin */
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MX25_PAD_D13__GPIO_4_7 0x80000000 /* FEC reset */
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MX25_PAD_FEC_MDC__FEC_MDC 0x80000000
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MX25_PAD_FEC_MDIO__FEC_MDIO 0x80000000
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MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
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MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
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MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
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MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000
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MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000
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MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
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MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000
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>;
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};
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pinctrl_nfc: nfcgrp {
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fsl,pins = <
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MX25_PAD_NF_CE0__NF_CE0 0x80000000
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MX25_PAD_NFWE_B__NFWE_B 0x80000000
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MX25_PAD_NFRE_B__NFRE_B 0x80000000
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MX25_PAD_NFALE__NFALE 0x80000000
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MX25_PAD_NFCLE__NFCLE 0x80000000
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MX25_PAD_NFWP_B__NFWP_B 0x80000000
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MX25_PAD_NFRB__NFRB 0x80000000
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MX25_PAD_D7__D7 0x80000000
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MX25_PAD_D6__D6 0x80000000
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MX25_PAD_D5__D5 0x80000000
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MX25_PAD_D4__D4 0x80000000
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MX25_PAD_D3__D3 0x80000000
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MX25_PAD_D2__D2 0x80000000
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MX25_PAD_D1__D1 0x80000000
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MX25_PAD_D0__D0 0x80000000
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>;
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};
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-reset-gpios = <&gpio3 7 0>;
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phy-mode = "rmii";
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phy-supply = <®_fec_phy>;
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status = "okay";
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};
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&nfc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_nfc>;
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nand-on-flash-bbt;
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nand-ecc-mode = "hw";
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nand-bus-width = <8>;
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status = "okay";
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};
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