freebsd-dev/sys/mips
Adrian Chadd d24766cc51 mips: rate limit the trap handler output; add pid/tid/program name.
I discovered that we're logging each trap, which gets pretty spendy;
and there wasn't any further information on the pid/tid/progname involved.

I originally noticed this because I don't attach anything to /dev/log and so
the log() output stays going to the kernel.  That's an oops on my part, but
I'm glad I did it.

This commit adds the following:

* a rate limiter, which could do with some eyeballs/ideas on how to
  make it more predictable on SMP;
* log pid, tid, progname (comm) as part of the output.

I now get output like this:

Unaligned Load Word: pid=621 (pmcstat), tid=100060, pc=0xffffffff803ae898, badvaddr=0x40a10055
Unaligned Load Word: pid=621 (pmcstat), tid=100060, pc=0xffffffff803ae898, badvaddr=0x40a10051
Unaligned Load Word: pid=621 (pmcstat), tid=100060, pc=0xffffffff803ae898, badvaddr=0x40a1004d
Unaligned Load Word: pid=602 (login), tid=100042, pc=0xffffffff803ae898, badvaddr=0x401159
Unaligned Load Word: pid=602 (login), tid=100042, pc=0xffffffff803ae898, badvaddr=0x401155
Unaligned Load Word: pid=602 (login), tid=100042, pc=0xffffffff803ae898, badvaddr=0x401151

.. which makes it much easier to start figuring out what/where to fix.

The pc looks suss (it looks like it's in kernel space); I'll dig into that one next.

Tested:

* AR9331 SoC (Carambola2)
2015-11-02 03:36:15 +00:00
..
adm5120 Add domain support to PCI bus allocation 2015-09-16 23:34:51 +00:00
alchemy Fix a typo introduced in r257338. 2013-10-31 02:27:16 +00:00
atheros arge_mdio: fix barriers; correctly check MII indicator register. 2015-10-30 23:59:52 +00:00
beri preload_search_info: make sure mod is set 2015-08-21 15:57:57 +00:00
cavium Add domain support to PCI bus allocation 2015-09-16 23:34:51 +00:00
conf Commit the right board file - use the right name + hints. 2015-10-22 15:15:45 +00:00
gxemul Add 32-bit support for Gxemul's oldtestmips machine emulation 2013-09-04 20:34:36 +00:00
idt Add domain support to PCI bus allocation 2015-09-16 23:34:51 +00:00
include mips74k: use cache-writeback for memory, not writethrough. 2015-10-31 00:04:44 +00:00
malta Add domain support to PCI bus allocation 2015-09-16 23:34:51 +00:00
mips mips: rate limit the trap handler output; add pid/tid/program name. 2015-11-02 03:36:15 +00:00
nlm Add domain support to PCI bus allocation 2015-09-16 23:34:51 +00:00
rmi Add domain support to PCI bus allocation 2015-09-16 23:34:51 +00:00
rt305x Add support for the uart classes to set their default register shift value. 2015-04-11 17:16:23 +00:00
sentry5 Merge from vmobj-rwlock branch: 2013-02-26 01:00:11 +00:00
sibyte Devices that rely on hints or identify routines for discovery need to 2013-10-29 14:07:31 +00:00