209 lines
8.3 KiB
C
209 lines
8.3 KiB
C
/*
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* i82365.h - Definitions for Intel 82365 PCIC
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* PCMCIA Card Interface Controller
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*
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* originally by Barry Jaspan; hacked over by Keith Moore
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* hacked to unrecognisability by Andrew McRae (andrew@mega.com.au)
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*
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* Updated 3/3/95 to include Cirrus Logic stuff.
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*-------------------------------------------------------------------------
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*
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* Copyright (c) 1995 Andrew McRae. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#define PCIC_I82365 0 /* Intel chip */
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#define PCIC_IBM 1 /* IBM clone */
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#define PCIC_VLSI 2 /* VLSI chip */
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#define PCIC_PD672X 3 /* Cirrus logic 627x */
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#define PCIC_PD6710 4
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#define PCIC_CL6729 5
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#define PCIC_VG468 6
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#define PCIC_VG469 7
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/*
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* Address of the controllers. Each controller can manage
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* two PCMCIA slots. Up to 8 slots are supported in total.
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* The PCIC controller is accessed via an index port and a
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* data port. The index port has the 8 bit address of the
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* register accessed via the data port. How I long for
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* real memory mapped I/O!
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* The top two bits of the index address are used to
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* identify the port number, and the lower 6 bits
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* select one of the 64 possible data registers.
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*/
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#define PCIC_INDEX_0 0x3E0 /* index reg, chips 0 and 1 */
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#define PCIC_DATA_0 0x3E1 /* data register, chips 0 and 1 */
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#define PCIC_INDEX_1 0x3E2 /* index reg, chips 2 and 3 */
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#define PCIC_DATA_1 0x3E3 /* data register, chips 2 and 3 */
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/*
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* Register index addresses.
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*/
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#define PCIC_ID_REV 0x00 /* Identification and Revision */
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#define PCIC_STATUS 0x01 /* Interface Status */
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#define PCIC_POWER 0x02 /* Power and RESETDRV control */
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#define PCIC_INT_GEN 0x03 /* Interrupt and General Control */
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#define PCIC_STAT_CHG 0x04 /* Card Status Change */
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#define PCIC_STAT_INT 0x05 /* Card Status Change Interrupt Config */
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#define PCIC_ADDRWINE 0x06 /* Address Window Enable */
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#define PCIC_IOCTL 0x07 /* I/O Control */
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#define PCIC_IO0 0x08 /* I/O Address 0 */
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#define PCIC_IO1 0x0c /* I/O Address 1 */
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#define PCIC_MEMBASE 0x10 /* Base of memory window registers */
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#define PCIC_CDGC 0x16 /* Card Detect and General Control */
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#define PCIC_GLO_CTRL 0x1e /* Global Control Register */
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#define PCIC_TIME_SETUP0 0x3a
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#define PCIC_TIME_CMD0 0x3b
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#define PCIC_TIME_RECOV0 0x3c
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#define PCIC_TIME_SETUP1 0x3d
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#define PCIC_TIME_CMD1 0x3e
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#define PCIC_TIME_RECOV1 0x3f
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#define PCIC_SLOT_SIZE 0x40 /* Size of register set for one slot */
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/* Now register bits, ordered by reg # */
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/* For Identification and Revision (PCIC_ID_REV) */
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#define PCIC_INTEL0 0x82 /* Intel 82365SL Rev. 0; Both Memory and I/O */
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#define PCIC_INTEL1 0x83 /* Intel 82365SL Rev. 1; Both Memory and I/O */
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#define PCIC_IBM1 0x88 /* IBM PCIC clone; Both Memory and I/O */
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#define PCIC_IBM2 0x89 /* IBM PCIC clone; Both Memory and I/O */
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/* For Interface Status register (PCIC_STATUS) */
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#define PCIC_VPPV 0x80 /* Vpp_valid */
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#define PCIC_POW 0x40 /* PC Card power active */
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#define PCIC_READY 0x20 /* Ready/~Busy */
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#define PCIC_MWP 0x10 /* Memory Write Protect */
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#define PCIC_CD 0x0C /* Both card detect bits */
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#define PCIC_BVD 0x03 /* Both Battery Voltage Detect bits */
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/* For the Power and RESETDRV register (PCIC_POWER) */
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#define PCIC_OUTENA 0x80 /* Output Enable */
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#define PCIC_DISRST 0x40 /* Disable RESETDRV */
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#define PCIC_APSENA 0x20 /* Auto Pwer Switch Enable */
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#define PCIC_VCC 0x18 /* Vcc control bits */
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#define PCIC_VCC_5V 0x10 /* 5 volts */
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#define PCIC_VCC_3V 0x18 /* 3 volts */
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#define PCIC_VPP 0x0C /* Vpp control bits */
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#define PCIC_VPP_5V 0x01 /* 5 volts */
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#define PCIC_VPP_12V 0x02 /* 12 volts */
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/* For the Interrupt and General Control register (PCIC_INT_GEN) */
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#define PCIC_CARDTYPE 0x20 /* Card Type 0 = memory, 1 = I/O */
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#define PCIC_IOCARD 0x20
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#define PCIC_MEMCARD 0x00
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#define PCIC_CARDRESET 0x40 /* Card reset 0 = Reset, 1 = Normal */
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#define PCIC_INTR_ENA 0x10 /* Interrupt enable */
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/* For the Card Status Change register (PCIC_STAT_CHG) */
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#define PCIC_CDTCH 0x08 /* Card Detect Change */
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#define PCIC_RDYCH 0x04 /* Ready Change */
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#define PCIC_BATWRN 0x02 /* Battery Warning */
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#define PCIC_BATDED 0x01 /* Battery Dead */
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/*
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* For the Address Window Enable Register (PCIC_ADDRWINE)
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* The lower 6 bits contain enable bits for the memory
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* windows (LSB = memory window 0).
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*/
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#define PCIC_MEMCS16 0x20 /* ~MEMCS16 Decode A23-A12 */
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#define PCIC_IO0_EN 0x40 /* I/O Window 0 Enable */
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#define PCIC_IO1_EN 0x80 /* I/O Window 1 Enable */
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/*
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* For the I/O Control Register (PCIC_IOCTL)
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* The lower nybble is the flags for I/O window 0
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* The upper nybble is the flags for I/O window 1
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*/
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#define PCIC_IO_16BIT 0x01 /* I/O to this segment is 16 bit */
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#define PCIC_IO_CS16 0x02 /* I/O cs16 source is the card */
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#define PCIC_IO_0WS 0x04 /* zero wait states added on 8 bit cycles */
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#define PCIC_IO_WS 0x08 /* Wait states added for 16 bit cycles */
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/*
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* The memory window registers contain the start and end
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* physical host address that the PCIC maps to the card,
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* and an offset calculated from the card memory address.
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* All values are shifted down 12 bits, so allocation is
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* done in 4Kb blocks. Only 12 bits of each value is
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* stored, limiting the range to the ISA address size of
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* 24 bits. The upper 4 bits of the most significant byte
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* within the values are used for various flags.
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*
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* The layout is:
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*
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* base+0 : lower 8 bits of system memory start address
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* base+1 : upper 4 bits of system memory start address + flags
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* base+2 : lower 8 bits of system memory end address
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* base+3 : upper 4 bits of system memory end address + flags
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* base+4 : lower 8 bits of offset to card address
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* base+5 : upper 4 bits of offset to card address + flags
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*
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* The following two bytes are reserved for other use.
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*/
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#define PCIC_MEMSIZE 8
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/*
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* Flags for system memory start address upper byte
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*/
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#define PCIC_ZEROWS 0x40 /* Zero wait states */
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#define PCIC_DATA16 0x80 /* Data width is 16 bits */
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/*
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* Flags for system memory end address upper byte
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*/
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#define PCIC_MW0 0x40 /* Wait state bit 0 */
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#define PCIC_MW1 0x80 /* Wait state bit 1 */
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/*
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* Flags for card offset upper byte
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*/
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#define PCIC_REG 0x40 /* Attribute/Common select (why called Reg?) */
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#define PCIC_WP 0x80 /* Write-protect this window */
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/* For Card Detect and General Control register (PCIC_CDGC) */
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#define PCIC_16_DL_INH 0x01 /* 16-bit memory delay inhibit */
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#define PCIC_CNFG_RST_EN 0x02 /* configuration reset enable */
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#define PCIC_GPI_EN 0x04 /* GPI Enable */
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#define PCIC_GPI_TRANS 0x08 /* GPI Transition Control */
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#define PCIC_CDRES_EN 0x10 /* card detect resume enable */
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#define PCIC_SW_CD_INT 0x20 /* s/w card detect interrupt */
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/* For Global Control register (PCIC_GLO_CTRL) */
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#define PCIC_PWR_DOWN 0x01 /* power down */
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#define PCIC_LVL_MODE 0x02 /* level mode interrupt enable */
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#define PCIC_WB_CSCINT 0x04 /* explicit write-back csc intr */
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#define PCIC_IRQ0_LEVEL 0x08 /* irq 14 pulse mode enable */
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#define PCIC_IRQ1_LEVEL 0x10
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/*
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* Mask of allowable interrupts.
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* Ints are 3,4,5,7,9,10,11,12,14,15
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*/
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#define PCIC_INT_MASK_ALLOWED 0xDEB8
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#define PCIC_IO_WIN 2
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#define PCIC_MEM_WIN 5
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#define PCIC_MAX_SLOTS 8
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