caeff9a3c2
On BHND MIPS SoCs, this replaces the use of hard-coded MIPS IRQ#s in the common bhnd(4) core drivers; we now register an INTRNG child PIC that handles routing of backplane interrupt vectors via the MIPS core. On BHND PCI devices, backplane interrupt vectors are now routed to the PCI/PCIe host bridge core when bus_setup_intr() is called, where they are dispatched by the PCI core via a host interrupt (e.g. INTx/MSI). The bhndb(4) bridge driver tracks registered interrupt handlers for the bridged bhnd(4) devices and manages backplane interrupt routing, while delegating actual bus interrupt setup/teardown to the parent bus on behalf of the bridged cores. Approved by: adrian (mentor, implicit) Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D12518
139 lines
4.9 KiB
C
139 lines
4.9 KiB
C
/*-
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* Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
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* Copyright (c) 2017 The FreeBSD Foundation
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* All rights reserved.
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*
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* Portions of this software were developed by Landon Fuller
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* under sponsorship from the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*
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* $FreeBSD$
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*/
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#ifndef _MIPS_BROADCOM_BCM_MACHDEP_H_
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#define _MIPS_BROADCOM_BCM_MACHDEP_H_
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#include <machine/cpufunc.h>
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#include <machine/cpuregs.h>
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#include <dev/bhnd/bhnd.h>
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#include <dev/bhnd/bhnd_eromvar.h>
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#include <dev/bhnd/cores/pmu/bhnd_pmuvar.h>
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#include "bcm_nvram_cfevar.h"
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extern const struct bhnd_pmu_io bcm_pmu_soc_io;
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struct bcm_platform {
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struct bhnd_chipid cid; /**< chip id */
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struct bhnd_core_info cc_id; /**< chipc core info */
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uintptr_t cc_addr; /**< chipc core phys address */
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uint32_t cc_caps; /**< chipc capabilities */
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uint32_t cc_caps_ext; /**< chipc extended capabilies */
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struct bhnd_core_info cpu_id; /**< cpu core info */
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uintptr_t cpu_addr; /**< cpu core phys address */
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/* On non-AOB devices, the PMU register block is mapped to chipc;
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* the pmu_id and pmu_addr values will be copied from cc_id
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* and cc_addr. */
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struct bhnd_core_info pmu_id; /**< PMU core info */
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uintptr_t pmu_addr; /**< PMU core phys address, or
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0x0 if no PMU */
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struct bhnd_pmu_query pmu; /**< PMU query instance */
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bhnd_erom_class_t *erom_impl; /**< erom parser class */
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struct kobj_ops erom_ops; /**< compiled kobj opcache */
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struct bhnd_erom_iobus erom_io; /**< erom I/O callbacks */
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union {
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bhnd_erom_static_t data;
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bhnd_erom_t obj;
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} erom;
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struct bhnd_nvram_io *nvram_io; /**< NVRAM I/O context, or NULL if unavailable */
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bhnd_nvram_data_class *nvram_cls; /**< NVRAM data class, or NULL if unavailable */
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struct bhnd_service_registry services; /**< platform service providers */
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#ifdef CFE
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int cfe_console; /**< Console handle, or -1 */
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#endif
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};
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struct bcm_platform *bcm_get_platform(void);
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uint64_t bcm_get_cpufreq(struct bcm_platform *bp);
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uint64_t bcm_get_sifreq(struct bcm_platform *bp);
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uint64_t bcm_get_alpfreq(struct bcm_platform *bp);
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uint64_t bcm_get_ilpfreq(struct bcm_platform *bp);
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u_int bcm_get_uart_rclk(struct bcm_platform *bp);
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int bcm_get_nvram(struct bcm_platform *bp,
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const char *name, void *outp, size_t *olen,
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bhnd_nvram_type type);
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#define BCM_ERR(fmt, ...) \
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printf("%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
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#define BCM_SOC_BSH(_addr, _offset) \
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((bus_space_handle_t)BCM_SOC_ADDR((_addr), (_offset)))
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#define BCM_SOC_ADDR(_addr, _offset) \
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MIPS_PHYS_TO_KSEG1((_addr) + (_offset))
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#define BCM_SOC_READ_4(_addr, _offset) \
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readl(BCM_SOC_ADDR((_addr), (_offset)))
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#define BCM_SOC_WRITE_4(_addr, _reg, _val) \
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writel(BCM_SOC_ADDR((_addr), (_offset)), (_val))
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#define BCM_CORE_ADDR(_bp, _name, _reg) \
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BCM_SOC_ADDR(_bp->_name, (_reg))
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#define BCM_CORE_READ_4(_bp, _name, _reg) \
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readl(BCM_CORE_ADDR(_bp, _name, (_reg)))
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#define BCM_CORE_WRITE_4(_bp, _name, _reg, _val) \
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writel(BCM_CORE_ADDR(_bp, _name, (_reg)), (_val))
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#define BCM_CHIPC_READ_4(_bp, _reg) \
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BCM_CORE_READ_4(_bp, cc_addr, (_reg))
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#define BCM_CHIPC_WRITE_4(_bp, _reg, _val) \
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BCM_CORE_WRITE_4(_bp, cc_addr, (_reg), (_val))
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#define BCM_CPU_READ_4(_bp, _reg) \
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BCM_CORE_READ_4(_bp, cpu_addr, (_reg))
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#define BCM_CPU_WRITE_4(_bp, _reg, _val) \
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BCM_CORE_WRITE_4(_bp, cpu_addr, (_reg), (_val))
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#define BCM_PMU_READ_4(_bp, _reg) \
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BCM_CORE_READ_4(_bp, pmu_addr, (_reg))
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#define BCM_PMU_WRITE_4(_bp, _reg, _val) \
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BCM_CORE_WRITE_4(_bp, pmu_addr, (_reg), (_val))
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#endif /* _MIPS_BROADCOM_BCM_MACHDEP_H_ */
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