102 lines
3.8 KiB
C
102 lines
3.8 KiB
C
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/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* cvmx-smi-defs.h
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*
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* Configuration and status register (CSR) type definitions for
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* Octeon smi.
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*
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* This file is auto generated. Do not edit.
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*
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* <hr>$Revision$<hr>
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*
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*/
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#ifndef __CVMX_SMI_TYPEDEFS_H__
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#define __CVMX_SMI_TYPEDEFS_H__
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_SMI_DRV_CTL CVMX_SMI_DRV_CTL_FUNC()
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static inline uint64_t CVMX_SMI_DRV_CTL_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
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cvmx_warn("CVMX_SMI_DRV_CTL not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001180000001828ull);
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}
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#else
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#define CVMX_SMI_DRV_CTL (CVMX_ADD_IO_SEG(0x0001180000001828ull))
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#endif
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/**
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* cvmx_smi_drv_ctl
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*
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* SMI_DRV_CTL = SMI Drive Strength Control
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*
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*/
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union cvmx_smi_drv_ctl
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{
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uint64_t u64;
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struct cvmx_smi_drv_ctl_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_14_63 : 50;
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uint64_t pctl : 6; /**< PCTL Drive strength control bits
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Assuming a 50ohm termination
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3.3v supply = 19
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2.5v supply = TBD */
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uint64_t reserved_6_7 : 2;
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uint64_t nctl : 6; /**< NCTL Drive strength control bits
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Assuming a 50ohm termination
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3.3v supply = 15
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2.5v supply = TBD */
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#else
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uint64_t nctl : 6;
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uint64_t reserved_6_7 : 2;
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uint64_t pctl : 6;
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uint64_t reserved_14_63 : 50;
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#endif
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} s;
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struct cvmx_smi_drv_ctl_s cn63xx;
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struct cvmx_smi_drv_ctl_s cn63xxp1;
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};
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typedef union cvmx_smi_drv_ctl cvmx_smi_drv_ctl_t;
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#endif
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