2016-09-09 14:50:44 +00:00
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/*-
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* Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Portions of this software were developed by SRI International and the
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* University of Cambridge Computer Laboratory under DARPA/AFRL contract
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* FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Portions of this software were developed by the University of Cambridge
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* Computer Laboratory as part of the CTSRD Project, with support from the
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* UK Higher Education Innovation Fund (HEIF).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/smp.h>
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#include <sys/systm.h>
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#include <machine/cpufunc.h>
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#include <machine/hwfunc.h>
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#include <machine/md_var.h>
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#include <machine/smp.h>
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2016-09-12 16:38:51 +00:00
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#define VPECONF0_VPA (1 << 0)
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#define MVPCONTROL_VPC (1 << 1)
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2018-08-14 16:29:10 +00:00
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#define MVPCONF0_PVPE_SHIFT 10
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#define MVPCONF0_PVPE_MASK (0xf << MVPCONF0_PVPE_SHIFT)
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2016-09-12 16:38:51 +00:00
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#define TCSTATUS_A (1 << 13)
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2016-09-09 14:50:44 +00:00
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unsigned malta_ap_boot = ~0;
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#define C_SW0 (1 << 8)
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#define C_SW1 (1 << 9)
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#define C_IRQ0 (1 << 10)
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#define C_IRQ1 (1 << 11)
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#define C_IRQ2 (1 << 12)
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#define C_IRQ3 (1 << 13)
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#define C_IRQ4 (1 << 14)
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#define C_IRQ5 (1 << 15)
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2016-09-12 16:38:51 +00:00
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static inline void
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evpe(void)
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{
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__asm __volatile(
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" .set push \n"
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" .set noreorder \n"
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" .set noat \n"
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" .set mips32r2 \n"
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" .word 0x41600021 # evpe \n"
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" ehb \n"
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" .set pop \n");
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}
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2016-09-09 14:50:44 +00:00
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static inline void
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ehb(void)
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{
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__asm __volatile(
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" .set mips32r2 \n"
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" ehb \n"
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" .set mips0 \n");
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}
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#define mttc0(rd, sel, val) \
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({ \
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__asm __volatile( \
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" .set push \n" \
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" .set mips32r2 \n" \
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" .set noat \n" \
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" move $1, %0 \n" \
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" .word 0x41810000 | (" #rd " << 11) | " #sel " \n" \
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" .set pop \n" \
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:: "r" (val)); \
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})
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#define mftc0(rt, sel) \
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({ \
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unsigned long __res; \
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__asm __volatile( \
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" .set push \n" \
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" .set mips32r2 \n" \
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" .set noat \n" \
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" .word 0x41000800 | (" #rt " << 16) | " #sel " \n" \
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" move %0, $1 \n" \
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" .set pop \n" \
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: "=r" (__res)); \
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__res; \
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})
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#define write_c0_register32(reg, sel, val) \
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({ \
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__asm __volatile( \
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" .set push \n" \
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" .set mips32 \n" \
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" mtc0 %0, $%1, %2 \n" \
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" .set pop \n" \
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:: "r" (val), "i" (reg), "i" (sel)); \
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})
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#define read_c0_register32(reg, sel) \
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({ \
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uint32_t __retval; \
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__asm __volatile( \
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" .set push \n" \
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" .set mips32 \n" \
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" mfc0 %0, $%1, %2 \n" \
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" .set pop \n" \
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: "=r" (__retval) : "i" (reg), "i" (sel)); \
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__retval; \
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})
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2016-09-12 16:38:51 +00:00
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static void
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set_thread_context(int cpuid)
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2016-09-09 14:50:44 +00:00
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{
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uint32_t reg;
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reg = read_c0_register32(1, 1);
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reg &= ~(0xff);
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reg |= cpuid;
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write_c0_register32(1, 1, reg);
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ehb();
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2016-09-12 16:38:51 +00:00
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}
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void
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platform_ipi_send(int cpuid)
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{
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uint32_t reg;
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set_thread_context(cpuid);
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2016-09-09 14:50:44 +00:00
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/* Set cause */
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reg = mftc0(13, 0);
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2016-09-12 16:38:51 +00:00
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reg |= (C_SW1);
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mttc0(13, 0, reg);
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2016-09-09 14:50:44 +00:00
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}
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void
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platform_ipi_clear(void)
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{
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uint32_t reg;
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reg = mips_rd_cause();
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reg &= ~(C_SW1);
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mips_wr_cause(reg);
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}
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int
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platform_ipi_hardintr_num(void)
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{
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return (-1);
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}
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int
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platform_ipi_softintr_num(void)
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{
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return (1);
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}
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void
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platform_init_ap(int cpuid)
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{
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uint32_t clock_int_mask;
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uint32_t ipi_intr_mask;
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/*
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* Clear any pending IPIs.
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*/
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platform_ipi_clear();
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/*
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* Unmask the clock and ipi interrupts.
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*/
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ipi_intr_mask = soft_int_mask(platform_ipi_softintr_num());
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clock_int_mask = hard_int_mask(5);
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set_intr_mask(ipi_intr_mask | clock_int_mask);
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mips_wbflush();
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}
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void
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platform_cpu_mask(cpuset_t *mask)
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{
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2018-08-14 16:29:10 +00:00
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uint32_t i, ncpus, reg;
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reg = mftc0(0, 2);
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ncpus = ((reg & MVPCONF0_PVPE_MASK) >> MVPCONF0_PVPE_SHIFT) + 1;
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2016-09-09 14:50:44 +00:00
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CPU_ZERO(mask);
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2018-08-14 16:29:10 +00:00
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for (i = 0; i < ncpus; i++)
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2016-09-09 14:50:44 +00:00
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CPU_SET(i, mask);
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}
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struct cpu_group *
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platform_smp_topo(void)
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{
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return (smp_topo_none());
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}
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int
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platform_start_ap(int cpuid)
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{
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2016-09-12 16:38:51 +00:00
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uint32_t reg;
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2016-09-09 14:50:44 +00:00
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int timeout;
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2016-09-12 16:38:51 +00:00
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/* Enter into configuration */
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reg = read_c0_register32(0, 1);
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reg |= (MVPCONTROL_VPC);
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write_c0_register32(0, 1, reg);
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set_thread_context(cpuid);
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/*
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* Hint: how to set entry point.
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* reg = 0x80000000;
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* mttc0(2, 3, reg);
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*/
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/* Enable thread */
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reg = mftc0(2, 1);
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reg |= (TCSTATUS_A);
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mttc0(2, 1, reg);
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/* Unhalt CPU core */
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mttc0(2, 4, 0);
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/* Activate VPE */
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reg = mftc0(1, 2);
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reg |= (VPECONF0_VPA);
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mttc0(1, 2, reg);
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/* Out of configuration */
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reg = read_c0_register32(0, 1);
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reg &= ~(MVPCONTROL_VPC);
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write_c0_register32(0, 1, reg);
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evpe();
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2016-09-09 14:50:44 +00:00
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if (atomic_cmpset_32(&malta_ap_boot, ~0, cpuid) == 0)
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return (-1);
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printf("Waiting for cpu%d to start\n", cpuid);
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timeout = 100;
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do {
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DELAY(1000);
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if (atomic_cmpset_32(&malta_ap_boot, 0, ~0) != 0) {
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printf("CPU %d started\n", cpuid);
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return (0);
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}
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} while (timeout--);
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printf("CPU %d failed to start\n", cpuid);
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return (0);
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}
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