1995-04-08 09:39:36 +00:00
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/*
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* Copyright (c) 1993 Dean Huxley (dean@fsa.ca)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Dean Huxley.
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* 4. The name of Dean Huxley may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Register offsets from base.
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*/
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#define EG_COMMAND 0x00
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#define EG_STATUS 0x02
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#define EG_DATA 0x04
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#define EG_CONTROL 0x06
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/*
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* Host Control Register bits
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* EG_CTL_ATTN - does a soft reset
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* EG_CTL_FLSH - flushes the data register
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* EG_CTL_RESET - does a hard reset
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* EG_CTL_DMAE - Used with DIR bit, enables DMA transfers to/from data reg.
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* EG_CTL_DIR - if clear then host -> adapter, if set then adapter -> host
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* EG_CTL_TCEN - terminal count enable. enables host interrupt after DMA.
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* EG_CTL_CMDE - command reg interrupt enable. (when it is written)
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* EG_CTL_HSF1 - Host status flag 1
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* EG_CTL_HSF2 - Host status flag 2
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*/
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#define EG_CTL_ATTN 0x80
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#define EG_CTL_FLSH 0x40
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#define EG_CTL_RESET (EG_CTL_ATTN|EG_CTL_FLSH)
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#define EG_CTL_DMAE 0x20
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#define EG_CTL_DIR 0x10
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#define EG_CTL_TCEN 0x08
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#define EG_CTL_CMDE 0x04
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#define EG_CTL_HSF2 0x02
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#define EG_CTL_HSF1 0x01
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/*
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* Host Status Register bits
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1996-08-04 10:58:17 +00:00
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* EG_STAT_HRDY - Data Register ready
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1995-04-08 09:39:36 +00:00
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* EG_STAT_HCRE - Host Command Register empty
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* EG_STAT_ACRF - Adapter Command register full
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* EG_STAT_DIR - Direction flag, 0 = host -> adapter, 1 = adapter -> host
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* EG_STAT_DONE - DMA done
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* EG_STAT_ASF1 - Adapter status flag 1
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* EG_STAT_ASF2 - Adapter status flag 2
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* EG_STAT_ASF3 - Adapter status flag 3
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*/
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#define EG_STAT_HRDY 0x80
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#define EG_STAT_HCRE 0x40
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#define EG_STAT_ACRF 0x20
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#define EG_STAT_DIR 0x10
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#define EG_STAT_DONE 0x08
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#define EG_STAT_ASF3 0x04
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#define EG_STAT_ASF2 0x02
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#define EG_STAT_ASF1 0x01
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1996-08-04 10:58:17 +00:00
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#define EG_PCB_NULL 0x00
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#define EG_PCB_ACCEPT 0x01
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#define EG_PCB_REJECT 0x02
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#define EG_PCB_DONE 0x03
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#define EG_PCB_STAT 0x03
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1995-04-08 09:39:36 +00:00
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#define EG_CMD_CONFIG82586 0x02
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#define EG_CMD_GETEADDR 0x03
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#define EG_CMD_RECVPACKET 0x08
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#define EG_CMD_SENDPACKET 0x09
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#define EG_CMD_GETSTATS 0x0a
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#define EG_CMD_SETEADDR 0x10
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#define EG_CMD_GETINFO 0x11
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#define EG_RSP_CONFIG82586 0x32
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#define EG_RSP_GETEADDR 0x33
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#define EG_RSP_RECVPACKET 0x38
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#define EG_RSP_SENDPACKET 0x39
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#define EG_RSP_GETSTATS 0x3a
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#define EG_RSP_SETEADDR 0x40
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#define EG_RSP_GETINFO 0x41
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