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freebsd-nq/sys/dev/vr/if_vr.c

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/* -> /*- for license, minor formatting changes
2005-01-07 02:29:27 +00:00
/*-
spdx: initial adoption of licensing ID tags. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts. Special thanks to Wind River for providing access to "The Duke of Highlander" tool: an older (2014) run over FreeBSD tree was useful as a starting point. Initially, only tag files that use BSD 4-Clause "Original" license. RelNotes: yes Differential Revision: https://reviews.freebsd.org/D13133
2017-11-18 14:26:50 +00:00
* SPDX-License-Identifier: BSD-4-Clause
*
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
* Copyright (c) 1997, 1998
* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
Remove duplicate FBSDID's, move others to their right place.
2003-11-14 17:16:58 +00:00
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
/*
* VIA Rhine fast ethernet PCI NIC driver
*
* Supports various network adapters based on the VIA Rhine
* and Rhine II PCI controllers, including the D-Link DFE530TX.
* Datasheets are available at http://www.via.com.tw.
*
* Written by Bill Paul <wpaul@ctr.columbia.edu>
* Electrical Engineering Department
* Columbia University, New York City
*/
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
/*
* The VIA Rhine controllers are similar in some respects to the
* the DEC tulip chips, except less complicated. The controller
* uses an MII bus and an external physical layer interface. The
* receiver has a one entry perfect filter and a 64-bit hash table
* multicast filter. Transmit and receive descriptors are similar
* to the tulip.
*
Remove the old software bit-banging MII interface, we started using the Rhines shiftregisters in four years ago (1.60).
2007-04-22 15:58:56 +00:00
* Some Rhine chips has a serious flaw in its transmit DMA mechanism:
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
* transmit buffers must be longword aligned. Unfortunately,
* FreeBSD doesn't guarantee that mbufs will be filled in starting
* at longword boundaries, so we have to do a buffer copy before
* transmission.
*/
- Don't pollute opt_global.h with DEVICE_POLLING and introduce opt_device_polling.h - Include opt_device_polling.h into appropriate files. - Embrace with HAVE_KERNEL_OPTION_HEADERS the include in the files that can be compiled as loadable modules. Reviewed by: bde
2005-10-05 10:09:17 +00:00
#ifdef HAVE_KERNEL_OPTION_HEADERS
#include "opt_device_polling.h"
#endif
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
#include <sys/param.h>
#include <sys/systm.h>
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
#include <sys/bus.h>
#include <sys/endian.h>
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
#include <sys/kernel.h>
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
#include <sys/malloc.h>
#include <sys/mbuf.h>
Add missing <sys/module.h> includes
2004-05-30 20:00:41 +00:00
#include <sys/module.h>
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
#include <sys/rman.h>
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
#include <sys/socket.h>
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
#include <sys/sockio.h>
#include <sys/sysctl.h>
#include <sys/taskqueue.h>
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
#include <net/bpf.h>
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
#include <net/if.h>
The r48589 promised to remove implicit inclusion of if_var.h soon. Prepare to this event, adding if_var.h to files that do need it. Also, include all includes that now are included due to implicit pollution via if_var.h Sponsored by: Netflix Sponsored by: Nginx, Inc.
2013-10-26 17:58:36 +00:00
#include <net/if_var.h>
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
#include <net/ethernet.h>
#include <net/if_dl.h>
#include <net/if_media.h>
Stop embedding struct ifnet at the top of driver softcs. Instead the struct ifnet or the layer 2 common structure it was embedded in have been replaced with a struct ifnet pointer to be filled by a call to the new function, if_alloc(). The layer 2 common structure is also allocated via if_alloc() based on the interface type. It is hung off the new struct ifnet member, if_l2com. This change removes the size of these structures from the kernel ABI and will allow us to better manage them as interfaces come and go. Other changes of note: - Struct arpcom is no longer referenced in normal interface code. Instead the Ethernet address is accessed via the IFP2ENADDR() macro. To enforce this ac_enaddr has been renamed to _ac_enaddr. - The second argument to ether_ifattach is now always the mac address from driver private storage rather than sometimes being ac_enaddr. Reviewed by: sobomax, sam
2005-06-10 16:49:24 +00:00
#include <net/if_types.h>
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
#include <net/if_vlan_var.h>
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
#include <dev/mii/mii.h>
Convert the VIA Rhine driver to miibus.
1999-09-19 22:03:31 +00:00
#include <dev/mii/miivar.h>
Not all VIA Rhine chips support 256 register space. So touching VR_STICKHW register would result in unexpected results on these hardwares. wpaul said the following for the issue. The vr_attach() routine unconditionally does this for all supported chips: /* * Windows may put the chip in suspend mode when it * shuts down. Be sure to kick it in the head to wake it * up again. */ VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); The problem is, the VR_STICKHW register is not valid on all Rhine devices. The VT86C100A chip, which is present on the D-Link DFE-530TX boards, doesn't support power management, and its register space is only 128 bytes wide. The VR_STICKHW register offset falls outside this range. This may go unnoticed in most scenarios, but if you happen to have another PCI device in your system which is assigned the register space immediately after that of the Rhine, the vr(4) driver will incorrectly stomp it. In my case, the BIOS on my test board decided to put the register space for my PRO/100 ethernet board right next to the Rhine, and the Rhine driver ended up clobbering the IMR register of the PRO/100 device. (Long story short: the board kept locking up on boot. Took me the better part of the morning suss out why.) The strictly correct thing to do would be to check the PCI config space to make sure the device supports the power management capability and only write to the VR_STICKHW register if it does. Instead of inspecting chip revision numbers for the availability of VR_STICKHW register, check the existence of power management capability of the hardware as wpaul suggested. Reported by: wpaul Suggested by: wpaul OK'ed by: jhb
2007-10-12 03:32:55 +00:00
#include <dev/pci/pcireg.h>
Prefer new location of pci include files (which have only been in the tree for two or more years now), except in a few places where there's code to be compatible with older versions of FreeBSD.
2003-08-22 07:20:27 +00:00
#include <dev/pci/pcivar.h>
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
#include <machine/bus.h>
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Forced commit to note that vr(4) was repocopied from sys/pci and modified for its new location.
2008-03-11 03:44:46 +00:00
#include <dev/vr/if_vrreg.h>
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
/* "device miibus" required. See GENERIC if you get errors here. */
#include "miibus_if.h"
- Express hard dependencies on bus (pci, isa, pccard) and network layer (ether). - Don't abuse module names to facilitate ifconfig module loading; such abuse isn't really needed. (And if we do need type information associated with a module then we should make it explicit and not use hacks.)
2003-04-15 06:37:30 +00:00
MODULE_DEPEND(vr, pci, 1, 1, 1);
MODULE_DEPEND(vr, ether, 1, 1, 1);
Depend on miibus. Note that if_aue doesn't strictly depend on usb because it uses the method interface for calls rather than using internal symbols, and because it's a child driver of usb and therefore will not try and do anything unless the parent usb code is loaded at some point. if_aue does strictly depend on miibus as it will fail to link if it is missing.
2000-04-29 13:41:57 +00:00
MODULE_DEPEND(vr, miibus, 1, 1, 1);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
/* Define to show Rx/Tx error status. */
#undef VR_SHOW_ERRORS
#define VR_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
Convert the VIA Rhine driver to miibus.
1999-09-19 22:03:31 +00:00
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
/*
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
* Various supported device vendors/types, their names & quirks.
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
*/
Remove further cobwebs: Two layers of pointless substructures.
2007-04-22 15:48:29 +00:00
#define VR_Q_NEEDALIGN (1<<0)
#define VR_Q_CSUM (1<<1)
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
#define VR_Q_CAM (1<<2)
Remove further cobwebs: Two layers of pointless substructures.
2007-04-22 15:48:29 +00:00
Sprinkle const.
2011-10-09 20:16:51 +00:00
static const struct vr_type {
Remove further cobwebs: Two layers of pointless substructures.
2007-04-22 15:48:29 +00:00
u_int16_t vr_vid;
u_int16_t vr_did;
int vr_quirks;
Sprinkle const.
2011-10-09 20:16:51 +00:00
const char *vr_name;
Remove duplicate const specifiers in many drivers (I hope I got all of them, please let me know if not). Most of these are of the form: static const struct bzzt_type { [...list of members...] } const bzzt_devs[] = { [...list of initializers...] }; The second const is unnecessary, as arrays cannot be modified anyway, and if the elements are const, the whole thing is const automatically (e.g. it is placed in .rodata). I have verified this does not change the binary output of a full kernel build (except for build timestamps embedded in the object files). Reviewed by: yongari, marius MFC after: 1 week
2012-11-05 19:16:27 +00:00
} vr_devs[] = {
Add support for hw-assisted checksums on 6105M. Sponsored by: Soekris Engineering
2007-04-17 22:59:54 +00:00
{ VIA_VENDORID, VIA_DEVICEID_RHINE,
VR_Q_NEEDALIGN,
"VIA VT3043 Rhine I 10/100BaseTX" },
{ VIA_VENDORID, VIA_DEVICEID_RHINE_II,
VR_Q_NEEDALIGN,
"VIA VT86C100A Rhine II 10/100BaseTX" },
{ VIA_VENDORID, VIA_DEVICEID_RHINE_II_2,
0,
"VIA VT6102 Rhine II 10/100BaseTX" },
{ VIA_VENDORID, VIA_DEVICEID_RHINE_III,
0,
"VIA VT6105 Rhine III 10/100BaseTX" },
{ VIA_VENDORID, VIA_DEVICEID_RHINE_III_M,
It seems there are still issues on multicast perfect filtering. Disable it until I find spare time to analyze the issue. Reported by: Goran Lowkrantz <glz <> hidden-powers DOT com> MFC after: 3 days
2008-12-12 01:26:11 +00:00
VR_Q_CSUM,
Add support for hw-assisted checksums on 6105M. Sponsored by: Soekris Engineering
2007-04-17 22:59:54 +00:00
"VIA VT6105M Rhine III 10/100BaseTX" },
{ DELTA_VENDORID, DELTA_DEVICEID_RHINE_II,
VR_Q_NEEDALIGN,
"Delta Electronics Rhine II 10/100BaseTX" },
{ ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II,
VR_Q_NEEDALIGN,
"Addtron Technology Rhine II 10/100BaseTX" },
Improve the if_vr driver ever so slightly. The 6105M and 6102 does not have the DWORD alignment problem, so don't m_defrag() every packet in the transmit path for those. More stringent usage of tx-descriptor ring and its flags. Tested on 6102 and 6105M, other chips may also be able to run without the m_defrag() but I have neither hardware nor docs to find out. Sponsored by: Soekris Engineering
2007-04-17 12:23:57 +00:00
{ 0, 0, 0, NULL }
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
};
Fix style(9) issues with __P removal. Noticed by: bde
2005-02-24 22:33:05 +00:00
static int vr_probe(device_t);
static int vr_attach(device_t);
static int vr_detach(device_t);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
static int vr_shutdown(device_t);
static int vr_suspend(device_t);
static int vr_resume(device_t);
Fix style(9) issues with __P removal. Noticed by: bde
2005-02-24 22:33:05 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
static void vr_dmamap_cb(void *, bus_dma_segment_t *, int, int);
static int vr_dma_alloc(struct vr_softc *);
static void vr_dma_free(struct vr_softc *);
static __inline void vr_discard_rxbuf(struct vr_rxdesc *);
static int vr_newbuf(struct vr_softc *, int);
Fix style(9) issues with __P removal. Noticed by: bde
2005-02-24 22:33:05 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
#ifndef __NO_STRICT_ALIGNMENT
static __inline void vr_fixup_rx(struct mbuf *);
#endif
When user_frac in the polling subsystem is low it is going to busy the CPU for too long period than necessary. Additively, interfaces are kept polled (in the tick) even if no more packets are available. In order to avoid such situations a new generic mechanism can be implemented in proactive way, keeping track of the time spent on any packet and fragmenting the time for any tick, stopping the processing as soon as possible. In order to implement such mechanism, the polling handler needs to change, returning the number of packets processed. While the intended logic is not part of this patch, the polling KPI is broken by this commit, adding an int return value and the new flag IFCAP_POLLING_NOCOUNT (which will signal that the return value is meaningless for the installed handler and checking should be skipped). Bump __FreeBSD_version in order to signal such situation. Reviewed by: emaste Sponsored by: Sandvine Incorporated
2009-05-30 15:14:44 +00:00
static int vr_rxeof(struct vr_softc *);
Fix style(9) issues with __P removal. Noticed by: bde
2005-02-24 22:33:05 +00:00
static void vr_txeof(struct vr_softc *);
static void vr_tick(void *);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
static int vr_error(struct vr_softc *, uint16_t);
static void vr_tx_underrun(struct vr_softc *);
Convert the if_vr(4) driver model to the interrupt filter model and use a taskqueue. This gives a 16% performance improvement under high load on slow systems, especially when vr shares an interrupt with another device, which is common with the Alix x86 boards. Contrary to the other devices, I left the interrupt processing for loop in because there was no significant difference in performance and this should avoid enqueuing more taskqueues unnecessarily. We also decided to move the vr_start_locked() call inside the for loop because we found out that it helps performance since TCP ACKs now have a chance to go out quicker. Reviewed by: yongari (older version, same idea) Discussed with: yongari, jhb
2012-05-12 14:37:25 +00:00
static int vr_intr(void *);
static void vr_int_task(void *, int);
Fix style(9) issues with __P removal. Noticed by: bde
2005-02-24 22:33:05 +00:00
static void vr_start(struct ifnet *);
static void vr_start_locked(struct ifnet *);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
static int vr_encap(struct vr_softc *, struct mbuf **);
Fix style(9) issues with __P removal. Noticed by: bde
2005-02-24 22:33:05 +00:00
static int vr_ioctl(struct ifnet *, u_long, caddr_t);
static void vr_init(void *);
static void vr_init_locked(struct vr_softc *);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
static void vr_tx_start(struct vr_softc *);
static void vr_rx_start(struct vr_softc *);
static int vr_tx_stop(struct vr_softc *);
static int vr_rx_stop(struct vr_softc *);
Fix style(9) issues with __P removal. Noticed by: bde
2005-02-24 22:33:05 +00:00
static void vr_stop(struct vr_softc *);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
static void vr_watchdog(struct vr_softc *);
Fix style(9) issues with __P removal. Noticed by: bde
2005-02-24 22:33:05 +00:00
static int vr_ifmedia_upd(struct ifnet *);
static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *);
Remove __P.
2002-03-20 02:08:01 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
static int vr_miibus_readreg(device_t, int, int);
static int vr_miibus_writereg(device_t, int, int, int);
Fix style(9) issues with __P removal. Noticed by: bde
2005-02-24 22:33:05 +00:00
static void vr_miibus_statchg(device_t);
Fix a multicast handling regression on VT6105M introduced in vr(4) overhauling(r177050). It seems that filtering multicast addresses with multicast CAM entries require accessing 'CAM enable bit' for each CAM entry. Subsequent accessing multicast CAM control register without toggling the 'CAM enable bit' seem to no effects. In order to fix that separate CAM setup from CAM mask configuration and CAM entry modification. While I'm here add VLAN CAM filtering feature which will be enabled in future(FreeBSD now can receive VLAN id insertion/removal event from vlan(4) on the fly). For VT6105M hardware, explicitly disable VLAN hardware tag insertion/stripping and enable VLAN CAM filtering for VLAN id 0. This shall make non-VLAN frames set VR_RXSTAT_VIDHIT bit in Rx status word. Added multicast/VLAN CAM address definition to header file. PR: kern/125010, kern/125024 MFC after: 1 week
2008-07-16 08:35:29 +00:00
static void vr_cam_mask(struct vr_softc *, uint32_t, int);
static int vr_cam_data(struct vr_softc *, int, int, uint8_t *);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
static void vr_set_filter(struct vr_softc *);
Run if_vr(4) through FlexeLint and clean some of the cobwebs found.
2007-04-22 12:55:36 +00:00
static void vr_reset(const struct vr_softc *);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
static int vr_tx_ring_init(struct vr_softc *);
static int vr_rx_ring_init(struct vr_softc *);
static void vr_setwol(struct vr_softc *);
static void vr_clrwol(struct vr_softc *);
static int vr_sysctl_stats(SYSCTL_HANDLER_ARGS);
Sprinkle const.
2011-10-09 20:16:51 +00:00
static const struct vr_tx_threshold_table {
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
int tx_cfg;
int bcr_cfg;
int value;
Remove duplicate const specifiers in many drivers (I hope I got all of them, please let me know if not). Most of these are of the form: static const struct bzzt_type { [...list of members...] } const bzzt_devs[] = { [...list of initializers...] }; The second const is unnecessary, as arrays cannot be modified anyway, and if the elements are const, the whole thing is const automatically (e.g. it is placed in .rodata). I have verified this does not change the binary output of a full kernel build (except for build timestamps embedded in the object files). Reviewed by: yongari, marius MFC after: 1 week
2012-11-05 19:16:27 +00:00
} vr_tx_threshold_tables[] = {
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
{ VR_TXTHRESH_64BYTES, VR_BCR1_TXTHRESH64BYTES, 64 },
{ VR_TXTHRESH_128BYTES, VR_BCR1_TXTHRESH128BYTES, 128 },
{ VR_TXTHRESH_256BYTES, VR_BCR1_TXTHRESH256BYTES, 256 },
{ VR_TXTHRESH_512BYTES, VR_BCR1_TXTHRESH512BYTES, 512 },
{ VR_TXTHRESH_1024BYTES, VR_BCR1_TXTHRESH1024BYTES, 1024 },
{ VR_TXTHRESH_STORENFWD, VR_BCR1_TXTHRESHSTORENFWD, 2048 }
};
Convert the VIA Rhine driver to newbus and set it up to be compiled as a module. Also modified the code to work on FreeBSD/alpha and added device vr0 to the alpha GENERIC config. While I was in the neighborhood, I noticed that I was still using #define NFPX 1 in all of the Makefiles that I'd copied from the fxp module. I don't really use #define Nfoo X so it didn't matter, but I decided to customize this correctly anyway.
1999-08-10 17:15:20 +00:00
static device_method_t vr_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, vr_probe),
DEVMETHOD(device_attach, vr_attach),
DEVMETHOD(device_detach, vr_detach),
DEVMETHOD(device_shutdown, vr_shutdown),
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
DEVMETHOD(device_suspend, vr_suspend),
DEVMETHOD(device_resume, vr_resume),
Convert the VIA Rhine driver to miibus.
1999-09-19 22:03:31 +00:00
/* MII interface */
DEVMETHOD(miibus_readreg, vr_miibus_readreg),
DEVMETHOD(miibus_writereg, vr_miibus_writereg),
DEVMETHOD(miibus_statchg, vr_miibus_statchg),
- There's no need to overwrite the default device method with the default one. Interestingly, these are actually the default for quite some time (bus_generic_driver_added(9) since r52045 and bus_generic_print_child(9) since r52045) but even recently added device drivers do this unnecessarily. Discussed with: jhb, marcel - While at it, use DEVMETHOD_END. Discussed with: jhb - Also while at it, use __FBSDID.
2011-11-22 21:28:20 +00:00
DEVMETHOD_END
Convert the VIA Rhine driver to newbus and set it up to be compiled as a module. Also modified the code to work on FreeBSD/alpha and added device vr0 to the alpha GENERIC config. While I was in the neighborhood, I noticed that I was still using #define NFPX 1 in all of the Makefiles that I'd copied from the fxp module. I don't really use #define Nfoo X so it didn't matter, but I decided to customize this correctly anyway.
1999-08-10 17:15:20 +00:00
};
static driver_t vr_driver = {
Grrr. Okay, changing the devnames was a bad idea. Put them back the way they were.
1999-09-20 08:47:11 +00:00
"vr",
Convert the VIA Rhine driver to newbus and set it up to be compiled as a module. Also modified the code to work on FreeBSD/alpha and added device vr0 to the alpha GENERIC config. While I was in the neighborhood, I noticed that I was still using #define NFPX 1 in all of the Makefiles that I'd copied from the fxp module. I don't really use #define Nfoo X so it didn't matter, but I decided to customize this correctly anyway.
1999-08-10 17:15:20 +00:00
vr_methods,
sizeof(struct vr_softc)
};
static devclass_t vr_devclass;
- Express hard dependencies on bus (pci, isa, pccard) and network layer (ether). - Don't abuse module names to facilitate ifconfig module loading; such abuse isn't really needed. (And if we do need type information associated with a module then we should make it explicit and not use hacks.)
2003-04-15 06:37:30 +00:00
DRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0);
Un-do the changes to the DRIVER_MODULE() declarations in these drivers. This whole idea isn't going to work until somebody makes the bus/kld code smarter. The idea here is to change the module's internal name from "foo" to "if_foo" so that ifconfig can tell a network driver from a non-network one. However doing this doesn't work correctly no matter how you slice it. For everything to work, you have to change the name in both the driver_t struct and the DRIVER_MODULE() declaration. The problems are: - If you change the name in both places, then the kernel thinks that the device's name is now "if_foo", so you get things like: if_foo0: <FOO ethernet> irq foo at device foo on pcifoo if_foo0: Ethernet address: foo:foo:foo:foo:foo:foo This is bogus. Now the device name doesn't agree with the logical interface name. There's no reason for this, and it violates the principle of least astonishment. - If you leave the name in the driver_t struct as "foo" and only change the names in the DRIVER_MODULE() declaration to "if_foo" then attaching drivers to child devices doesn't work because the names don't agree. This breaks miibus: drivers that need to have miibuses and PHY drivers attached never get them. In other words: damned if you do, damned if you don't. This needs to be thought through some more. Since the drivers that use miibus are broken, I have to change these all back in order to make them work again. Yes this will stop ifconfig from being able to demand load driver modules. On the whole, I'd rather have that than having the drivers not work at all.
1999-09-20 19:06:45 +00:00
DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
style: put return types on a line by themselves.
2002-08-24 00:02:03 +00:00
static int
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
vr_miibus_readreg(device_t dev, int phy, int reg)
Switch the if_vr driver from using our generic MII routines over to using the Rhine's internal shift registers which are designed for the job. This reduces the amount of time we wait around shifting bits, and seems to work better with some chips. Also, provide a workaround for some newer cards which report fake PHYs at multiple addresses. (As more cards are ID'd, I'm sure this part of the code will have to be expanded to cover more cases.) Submitted by: Thomas Nystrom <thn@saeab.se> MFC after: 1 week
2003-02-01 01:18:26 +00:00
{
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
struct vr_softc *sc;
int i;
Switch the if_vr driver from using our generic MII routines over to using the Rhine's internal shift registers which are designed for the job. This reduces the amount of time we wait around shifting bits, and seems to work better with some chips. Also, provide a workaround for some newer cards which report fake PHYs at multiple addresses. (As more cards are ID'd, I'm sure this part of the code will have to be expanded to cover more cases.) Submitted by: Thomas Nystrom <thn@saeab.se> MFC after: 1 week
2003-02-01 01:18:26 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc = device_get_softc(dev);
Switch the if_vr driver from using our generic MII routines over to using the Rhine's internal shift registers which are designed for the job. This reduces the amount of time we wait around shifting bits, and seems to work better with some chips. Also, provide a workaround for some newer cards which report fake PHYs at multiple addresses. (As more cards are ID'd, I'm sure this part of the code will have to be expanded to cover more cases.) Submitted by: Thomas Nystrom <thn@saeab.se> MFC after: 1 week
2003-02-01 01:18:26 +00:00
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
/* Set the register address. */
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
CSR_WRITE_1(sc, VR_MIIADDR, reg);
Switch the if_vr driver from using our generic MII routines over to using the Rhine's internal shift registers which are designed for the job. This reduces the amount of time we wait around shifting bits, and seems to work better with some chips. Also, provide a workaround for some newer cards which report fake PHYs at multiple addresses. (As more cards are ID'd, I'm sure this part of the code will have to be expanded to cover more cases.) Submitted by: Thomas Nystrom <thn@saeab.se> MFC after: 1 week
2003-02-01 01:18:26 +00:00
VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB);
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
for (i = 0; i < VR_MII_TIMEOUT; i++) {
DELAY(1);
Switch the if_vr driver from using our generic MII routines over to using the Rhine's internal shift registers which are designed for the job. This reduces the amount of time we wait around shifting bits, and seems to work better with some chips. Also, provide a workaround for some newer cards which report fake PHYs at multiple addresses. (As more cards are ID'd, I'm sure this part of the code will have to be expanded to cover more cases.) Submitted by: Thomas Nystrom <thn@saeab.se> MFC after: 1 week
2003-02-01 01:18:26 +00:00
if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0)
break;
}
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (i == VR_MII_TIMEOUT)
device_printf(sc->vr_dev, "phy read timeout %d:%d\n", phy, reg);
Switch the if_vr driver from using our generic MII routines over to using the Rhine's internal shift registers which are designed for the job. This reduces the amount of time we wait around shifting bits, and seems to work better with some chips. Also, provide a workaround for some newer cards which report fake PHYs at multiple addresses. (As more cards are ID'd, I'm sure this part of the code will have to be expanded to cover more cases.) Submitted by: Thomas Nystrom <thn@saeab.se> MFC after: 1 week
2003-02-01 01:18:26 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
return (CSR_READ_2(sc, VR_MIIDATA));
Switch the if_vr driver from using our generic MII routines over to using the Rhine's internal shift registers which are designed for the job. This reduces the amount of time we wait around shifting bits, and seems to work better with some chips. Also, provide a workaround for some newer cards which report fake PHYs at multiple addresses. (As more cards are ID'd, I'm sure this part of the code will have to be expanded to cover more cases.) Submitted by: Thomas Nystrom <thn@saeab.se> MFC after: 1 week
2003-02-01 01:18:26 +00:00
}
style: put return types on a line by themselves.
2002-08-24 00:02:03 +00:00
static int
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
vr_miibus_writereg(device_t dev, int phy, int reg, int data)
Switch the if_vr driver from using our generic MII routines over to using the Rhine's internal shift registers which are designed for the job. This reduces the amount of time we wait around shifting bits, and seems to work better with some chips. Also, provide a workaround for some newer cards which report fake PHYs at multiple addresses. (As more cards are ID'd, I'm sure this part of the code will have to be expanded to cover more cases.) Submitted by: Thomas Nystrom <thn@saeab.se> MFC after: 1 week
2003-02-01 01:18:26 +00:00
{
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
struct vr_softc *sc;
int i;
Switch the if_vr driver from using our generic MII routines over to using the Rhine's internal shift registers which are designed for the job. This reduces the amount of time we wait around shifting bits, and seems to work better with some chips. Also, provide a workaround for some newer cards which report fake PHYs at multiple addresses. (As more cards are ID'd, I'm sure this part of the code will have to be expanded to cover more cases.) Submitted by: Thomas Nystrom <thn@saeab.se> MFC after: 1 week
2003-02-01 01:18:26 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc = device_get_softc(dev);
Switch the if_vr driver from using our generic MII routines over to using the Rhine's internal shift registers which are designed for the job. This reduces the amount of time we wait around shifting bits, and seems to work better with some chips. Also, provide a workaround for some newer cards which report fake PHYs at multiple addresses. (As more cards are ID'd, I'm sure this part of the code will have to be expanded to cover more cases.) Submitted by: Thomas Nystrom <thn@saeab.se> MFC after: 1 week
2003-02-01 01:18:26 +00:00
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
/* Set the register address and data to write. */
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
CSR_WRITE_1(sc, VR_MIIADDR, reg);
CSR_WRITE_2(sc, VR_MIIDATA, data);
Switch the if_vr driver from using our generic MII routines over to using the Rhine's internal shift registers which are designed for the job. This reduces the amount of time we wait around shifting bits, and seems to work better with some chips. Also, provide a workaround for some newer cards which report fake PHYs at multiple addresses. (As more cards are ID'd, I'm sure this part of the code will have to be expanded to cover more cases.) Submitted by: Thomas Nystrom <thn@saeab.se> MFC after: 1 week
2003-02-01 01:18:26 +00:00
VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
for (i = 0; i < VR_MII_TIMEOUT; i++) {
DELAY(1);
Switch the if_vr driver from using our generic MII routines over to using the Rhine's internal shift registers which are designed for the job. This reduces the amount of time we wait around shifting bits, and seems to work better with some chips. Also, provide a workaround for some newer cards which report fake PHYs at multiple addresses. (As more cards are ID'd, I'm sure this part of the code will have to be expanded to cover more cases.) Submitted by: Thomas Nystrom <thn@saeab.se> MFC after: 1 week
2003-02-01 01:18:26 +00:00
if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0)
break;
}
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (i == VR_MII_TIMEOUT)
device_printf(sc->vr_dev, "phy write timeout %d:%d\n", phy,
reg);
Switch the if_vr driver from using our generic MII routines over to using the Rhine's internal shift registers which are designed for the job. This reduces the amount of time we wait around shifting bits, and seems to work better with some chips. Also, provide a workaround for some newer cards which report fake PHYs at multiple addresses. (As more cards are ID'd, I'm sure this part of the code will have to be expanded to cover more cases.) Submitted by: Thomas Nystrom <thn@saeab.se> MFC after: 1 week
2003-02-01 01:18:26 +00:00
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
return (0);
Switch the if_vr driver from using our generic MII routines over to using the Rhine's internal shift registers which are designed for the job. This reduces the amount of time we wait around shifting bits, and seems to work better with some chips. Also, provide a workaround for some newer cards which report fake PHYs at multiple addresses. (As more cards are ID'd, I'm sure this part of the code will have to be expanded to cover more cases.) Submitted by: Thomas Nystrom <thn@saeab.se> MFC after: 1 week
2003-02-01 01:18:26 +00:00
}
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
/*
* In order to fiddle with the
* 'full-duplex' and '100Mbps' bits in the netconfig register, we
* first have to put the transmit and/or receive logic in the idle state.
*/
static void
Remove link state change callback handler. There is no need to register both status change and link state change callbacks. Implement checking valid link in state change callback and poll active link state in vr_tick(). This allows immediate detection of lost link as well as protecting driver from frequent link flips during link renegotiation. taskq implementation was removed because driver now needs to poll link state in vr_tick(). While I'm here do not report current link state if interface is not running. Tested by: n_hibma MFC after: 1 week
2011-06-22 02:18:45 +00:00
vr_miibus_statchg(device_t dev)
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
{
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
struct vr_softc *sc;
struct mii_data *mii;
struct ifnet *ifp;
int lfdx, mfdx;
uint8_t cr0, cr1, fc;
Switch the if_vr driver from using our generic MII routines over to using the Rhine's internal shift registers which are designed for the job. This reduces the amount of time we wait around shifting bits, and seems to work better with some chips. Also, provide a workaround for some newer cards which report fake PHYs at multiple addresses. (As more cards are ID'd, I'm sure this part of the code will have to be expanded to cover more cases.) Submitted by: Thomas Nystrom <thn@saeab.se> MFC after: 1 week
2003-02-01 01:18:26 +00:00
Remove link state change callback handler. There is no need to register both status change and link state change callbacks. Implement checking valid link in state change callback and poll active link state in vr_tick(). This allows immediate detection of lost link as well as protecting driver from frequent link flips during link renegotiation. taskq implementation was removed because driver now needs to poll link state in vr_tick(). While I'm here do not report current link state if interface is not running. Tested by: n_hibma MFC after: 1 week
2011-06-22 02:18:45 +00:00
sc = device_get_softc(dev);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
mii = device_get_softc(sc->vr_miibus);
ifp = sc->vr_ifp;
if (mii == NULL || ifp == NULL ||
Remove link state change callback handler. There is no need to register both status change and link state change callbacks. Implement checking valid link in state change callback and poll active link state in vr_tick(). This allows immediate detection of lost link as well as protecting driver from frequent link flips during link renegotiation. taskq implementation was removed because driver now needs to poll link state in vr_tick(). While I'm here do not report current link state if interface is not running. Tested by: n_hibma MFC after: 1 week
2011-06-22 02:18:45 +00:00
(ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
return;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Announce flow control capability to PHY drivers and enable flow control for all vr(4) controllers that support it. It's known that old vr(4) controllers(Rhine II) does not support TX pause but Rhine III supports both TX and RX pause. Make TX pause really work on Rhine III by letting controller know available RX buffers. While here, adjust XON/XOFF parameters to get better performance with flow control.
2011-11-28 19:03:59 +00:00
sc->vr_flags &= ~(VR_F_LINK | VR_F_TXPAUSE);
Remove link state change callback handler. There is no need to register both status change and link state change callbacks. Implement checking valid link in state change callback and poll active link state in vr_tick(). This allows immediate detection of lost link as well as protecting driver from frequent link flips during link renegotiation. taskq implementation was removed because driver now needs to poll link state in vr_tick(). While I'm here do not report current link state if interface is not running. Tested by: n_hibma MFC after: 1 week
2011-06-22 02:18:45 +00:00
if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
(IFM_ACTIVE | IFM_AVALID)) {
switch (IFM_SUBTYPE(mii->mii_media_active)) {
case IFM_10_T:
case IFM_100_TX:
Reuse flag variable to represent driver internal states rather than using member variables in softc. While I'm here change media after setting IFF_DRV_RUNNING. This will remove unnecessary link state handling in vr_tick() if controller established a link immediately.
2011-11-28 18:32:35 +00:00
sc->vr_flags |= VR_F_LINK;
Remove link state change callback handler. There is no need to register both status change and link state change callbacks. Implement checking valid link in state change callback and poll active link state in vr_tick(). This allows immediate detection of lost link as well as protecting driver from frequent link flips during link renegotiation. taskq implementation was removed because driver now needs to poll link state in vr_tick(). While I'm here do not report current link state if interface is not running. Tested by: n_hibma MFC after: 1 week
2011-06-22 02:18:45 +00:00
break;
default:
break;
}
}
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
Reuse flag variable to represent driver internal states rather than using member variables in softc. While I'm here change media after setting IFF_DRV_RUNNING. This will remove unnecessary link state handling in vr_tick() if controller established a link immediately.
2011-11-28 18:32:35 +00:00
if ((sc->vr_flags & VR_F_LINK) != 0) {
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
cr0 = CSR_READ_1(sc, VR_CR0);
cr1 = CSR_READ_1(sc, VR_CR1);
mfdx = (cr1 & VR_CR1_FULLDUPLEX) != 0;
lfdx = (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0;
if (mfdx != lfdx) {
if ((cr0 & (VR_CR0_TX_ON | VR_CR0_RX_ON)) != 0) {
if (vr_tx_stop(sc) != 0 ||
vr_rx_stop(sc) != 0) {
device_printf(sc->vr_dev,
"%s: Tx/Rx shutdown error -- "
"resetting\n", __func__);
sc->vr_flags |= VR_F_RESTART;
VR_UNLOCK(sc);
return;
}
}
if (lfdx)
cr1 |= VR_CR1_FULLDUPLEX;
else
cr1 &= ~VR_CR1_FULLDUPLEX;
CSR_WRITE_1(sc, VR_CR1, cr1);
}
fc = 0;
/* Configure flow-control. */
if (sc->vr_revid >= REV_ID_VT6105_A0) {
fc = CSR_READ_1(sc, VR_FLOWCR1);
fc &= ~(VR_FLOWCR1_TXPAUSE | VR_FLOWCR1_RXPAUSE);
if ((IFM_OPTIONS(mii->mii_media_active) &
IFM_ETH_RXPAUSE) != 0)
fc |= VR_FLOWCR1_RXPAUSE;
if ((IFM_OPTIONS(mii->mii_media_active) &
Announce flow control capability to PHY drivers and enable flow control for all vr(4) controllers that support it. It's known that old vr(4) controllers(Rhine II) does not support TX pause but Rhine III supports both TX and RX pause. Make TX pause really work on Rhine III by letting controller know available RX buffers. While here, adjust XON/XOFF parameters to get better performance with flow control.
2011-11-28 19:03:59 +00:00
IFM_ETH_TXPAUSE) != 0) {
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
fc |= VR_FLOWCR1_TXPAUSE;
Announce flow control capability to PHY drivers and enable flow control for all vr(4) controllers that support it. It's known that old vr(4) controllers(Rhine II) does not support TX pause but Rhine III supports both TX and RX pause. Make TX pause really work on Rhine III by letting controller know available RX buffers. While here, adjust XON/XOFF parameters to get better performance with flow control.
2011-11-28 19:03:59 +00:00
sc->vr_flags |= VR_F_TXPAUSE;
}
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
CSR_WRITE_1(sc, VR_FLOWCR1, fc);
} else if (sc->vr_revid >= REV_ID_VT6102_A) {
/* No Tx puase capability available for Rhine II. */
fc = CSR_READ_1(sc, VR_MISC_CR0);
fc &= ~VR_MISCCR0_RXPAUSE;
if ((IFM_OPTIONS(mii->mii_media_active) &
IFM_ETH_RXPAUSE) != 0)
fc |= VR_MISCCR0_RXPAUSE;
CSR_WRITE_1(sc, VR_MISC_CR0, fc);
}
vr_rx_start(sc);
vr_tx_start(sc);
} else {
if (vr_tx_stop(sc) != 0 || vr_rx_stop(sc) != 0) {
device_printf(sc->vr_dev,
"%s: Tx/Rx shutdown error -- resetting\n",
__func__);
sc->vr_flags |= VR_F_RESTART;
}
}
Convert the VIA Rhine driver to miibus.
1999-09-19 22:03:31 +00:00
}
Fix a multicast handling regression on VT6105M introduced in vr(4) overhauling(r177050). It seems that filtering multicast addresses with multicast CAM entries require accessing 'CAM enable bit' for each CAM entry. Subsequent accessing multicast CAM control register without toggling the 'CAM enable bit' seem to no effects. In order to fix that separate CAM setup from CAM mask configuration and CAM entry modification. While I'm here add VLAN CAM filtering feature which will be enabled in future(FreeBSD now can receive VLAN id insertion/removal event from vlan(4) on the fly). For VT6105M hardware, explicitly disable VLAN hardware tag insertion/stripping and enable VLAN CAM filtering for VLAN id 0. This shall make non-VLAN frames set VR_RXSTAT_VIDHIT bit in Rx status word. Added multicast/VLAN CAM address definition to header file. PR: kern/125010, kern/125024 MFC after: 1 week
2008-07-16 08:35:29 +00:00
static void
vr_cam_mask(struct vr_softc *sc, uint32_t mask, int type)
{
if (type == VR_MCAST_CAM)
CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST);
else
CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN);
CSR_WRITE_4(sc, VR_CAMMASK, mask);
CSR_WRITE_1(sc, VR_CAMCTL, 0);
}
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
static int
Fix a multicast handling regression on VT6105M introduced in vr(4) overhauling(r177050). It seems that filtering multicast addresses with multicast CAM entries require accessing 'CAM enable bit' for each CAM entry. Subsequent accessing multicast CAM control register without toggling the 'CAM enable bit' seem to no effects. In order to fix that separate CAM setup from CAM mask configuration and CAM entry modification. While I'm here add VLAN CAM filtering feature which will be enabled in future(FreeBSD now can receive VLAN id insertion/removal event from vlan(4) on the fly). For VT6105M hardware, explicitly disable VLAN hardware tag insertion/stripping and enable VLAN CAM filtering for VLAN id 0. This shall make non-VLAN frames set VR_RXSTAT_VIDHIT bit in Rx status word. Added multicast/VLAN CAM address definition to header file. PR: kern/125010, kern/125024 MFC after: 1 week
2008-07-16 08:35:29 +00:00
vr_cam_data(struct vr_softc *sc, int type, int idx, uint8_t *mac)
Convert the VIA Rhine driver to miibus.
1999-09-19 22:03:31 +00:00
{
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
int i;
Convert the VIA Rhine driver to miibus.
1999-09-19 22:03:31 +00:00
Fix a multicast handling regression on VT6105M introduced in vr(4) overhauling(r177050). It seems that filtering multicast addresses with multicast CAM entries require accessing 'CAM enable bit' for each CAM entry. Subsequent accessing multicast CAM control register without toggling the 'CAM enable bit' seem to no effects. In order to fix that separate CAM setup from CAM mask configuration and CAM entry modification. While I'm here add VLAN CAM filtering feature which will be enabled in future(FreeBSD now can receive VLAN id insertion/removal event from vlan(4) on the fly). For VT6105M hardware, explicitly disable VLAN hardware tag insertion/stripping and enable VLAN CAM filtering for VLAN id 0. This shall make non-VLAN frames set VR_RXSTAT_VIDHIT bit in Rx status word. Added multicast/VLAN CAM address definition to header file. PR: kern/125010, kern/125024 MFC after: 1 week
2008-07-16 08:35:29 +00:00
if (type == VR_MCAST_CAM) {
if (idx < 0 || idx >= VR_CAM_MCAST_CNT || mac == NULL)
return (EINVAL);
CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST);
} else
CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
/* Set CAM entry address. */
CSR_WRITE_1(sc, VR_CAMADDR, idx);
/* Set CAM entry data. */
Fix a multicast handling regression on VT6105M introduced in vr(4) overhauling(r177050). It seems that filtering multicast addresses with multicast CAM entries require accessing 'CAM enable bit' for each CAM entry. Subsequent accessing multicast CAM control register without toggling the 'CAM enable bit' seem to no effects. In order to fix that separate CAM setup from CAM mask configuration and CAM entry modification. While I'm here add VLAN CAM filtering feature which will be enabled in future(FreeBSD now can receive VLAN id insertion/removal event from vlan(4) on the fly). For VT6105M hardware, explicitly disable VLAN hardware tag insertion/stripping and enable VLAN CAM filtering for VLAN id 0. This shall make non-VLAN frames set VR_RXSTAT_VIDHIT bit in Rx status word. Added multicast/VLAN CAM address definition to header file. PR: kern/125010, kern/125024 MFC after: 1 week
2008-07-16 08:35:29 +00:00
if (type == VR_MCAST_CAM) {
for (i = 0; i < ETHER_ADDR_LEN; i++)
CSR_WRITE_1(sc, VR_MCAM0 + i, mac[i]);
} else {
CSR_WRITE_1(sc, VR_VCAM0, mac[0]);
CSR_WRITE_1(sc, VR_VCAM1, mac[1]);
}
DELAY(10);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
/* Write CAM and wait for self-clear of VR_CAMCTL_WRITE bit. */
Fix a multicast handling regression on VT6105M introduced in vr(4) overhauling(r177050). It seems that filtering multicast addresses with multicast CAM entries require accessing 'CAM enable bit' for each CAM entry. Subsequent accessing multicast CAM control register without toggling the 'CAM enable bit' seem to no effects. In order to fix that separate CAM setup from CAM mask configuration and CAM entry modification. While I'm here add VLAN CAM filtering feature which will be enabled in future(FreeBSD now can receive VLAN id insertion/removal event from vlan(4) on the fly). For VT6105M hardware, explicitly disable VLAN hardware tag insertion/stripping and enable VLAN CAM filtering for VLAN id 0. This shall make non-VLAN frames set VR_RXSTAT_VIDHIT bit in Rx status word. Added multicast/VLAN CAM address definition to header file. PR: kern/125010, kern/125024 MFC after: 1 week
2008-07-16 08:35:29 +00:00
CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_WRITE);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
for (i = 0; i < VR_TIMEOUT; i++) {
DELAY(1);
if ((CSR_READ_1(sc, VR_CAMCTL) & VR_CAMCTL_WRITE) == 0)
break;
}
if (i == VR_TIMEOUT)
device_printf(sc->vr_dev, "%s: setting CAM filter timeout!\n",
__func__);
Fix a multicast handling regression on VT6105M introduced in vr(4) overhauling(r177050). It seems that filtering multicast addresses with multicast CAM entries require accessing 'CAM enable bit' for each CAM entry. Subsequent accessing multicast CAM control register without toggling the 'CAM enable bit' seem to no effects. In order to fix that separate CAM setup from CAM mask configuration and CAM entry modification. While I'm here add VLAN CAM filtering feature which will be enabled in future(FreeBSD now can receive VLAN id insertion/removal event from vlan(4) on the fly). For VT6105M hardware, explicitly disable VLAN hardware tag insertion/stripping and enable VLAN CAM filtering for VLAN id 0. This shall make non-VLAN frames set VR_RXSTAT_VIDHIT bit in Rx status word. Added multicast/VLAN CAM address definition to header file. PR: kern/125010, kern/125024 MFC after: 1 week
2008-07-16 08:35:29 +00:00
CSR_WRITE_1(sc, VR_CAMCTL, 0);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
return (i == VR_TIMEOUT ? ETIMEDOUT : 0);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
/*
* Program the 64-bit multicast hash filter.
*/
style: put return types on a line by themselves.
2002-08-24 00:02:03 +00:00
static void
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
vr_set_filter(struct vr_softc *sc)
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
{
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
struct ifnet *ifp;
int h;
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
uint32_t hashes[2] = { 0, 0 };
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
struct ifmultiaddr *ifma;
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
uint8_t rxfilt;
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
int error, mcnt;
uint32_t cam_mask;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
SMPng locking cleanup for vr(4). - Remove recursive locking situations. Remove the MTX_RECURSE bit. - Take the lock for any routine which is not called from within if_vr.c itself; this includes entry points called by newbus, ifnet, callout, ifmedia, and polling subsystems. - Remove spl references from the code added to miibus callbacks in rev 1.60. - Add the INTR_MPSAFE bit. - Tidy up some assignments; locks are not needed for taking the address of something at a known offset, for example. - Tested on the machine this was committed from. Tested on: UP only, !debug.mpsafenet && debug.mpsafenet Reviewed by: rwatson
2004-07-03 02:59:02 +00:00
VR_LOCK_ASSERT(sc);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
ifp = sc->vr_ifp;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
rxfilt = CSR_READ_1(sc, VR_RXCFG);
Fix typo. It restuled in activating unwanted Rx filtering as well as resetting Rx threshold configuration. Submitted by: Joost Mulders < Joost.Mulders <> Sun DOT COM >
2008-11-17 00:50:59 +00:00
rxfilt &= ~(VR_RXCFG_RX_PROMISC | VR_RXCFG_RX_BROAD |
VR_RXCFG_RX_MULTI);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (ifp->if_flags & IFF_BROADCAST)
rxfilt |= VR_RXCFG_RX_BROAD;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
rxfilt |= VR_RXCFG_RX_MULTI;
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (ifp->if_flags & IFF_PROMISC)
rxfilt |= VR_RXCFG_RX_PROMISC;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF);
CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF);
return;
}
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
/* Now program new ones. */
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
error = 0;
Fix a multicast handling regression on VT6105M introduced in vr(4) overhauling(r177050). It seems that filtering multicast addresses with multicast CAM entries require accessing 'CAM enable bit' for each CAM entry. Subsequent accessing multicast CAM control register without toggling the 'CAM enable bit' seem to no effects. In order to fix that separate CAM setup from CAM mask configuration and CAM entry modification. While I'm here add VLAN CAM filtering feature which will be enabled in future(FreeBSD now can receive VLAN id insertion/removal event from vlan(4) on the fly). For VT6105M hardware, explicitly disable VLAN hardware tag insertion/stripping and enable VLAN CAM filtering for VLAN id 0. This shall make non-VLAN frames set VR_RXSTAT_VIDHIT bit in Rx status word. Added multicast/VLAN CAM address definition to header file. PR: kern/125010, kern/125024 MFC after: 1 week
2008-07-16 08:35:29 +00:00
mcnt = 0;
Use if_maddr_rlock()/if_maddr_runlock() rather than IF_ADDR_LOCK()/ IF_ADDR_UNLOCK() across network device drivers when accessing the per-interface multicast address list, if_multiaddrs. This will allow us to change the locking strategy without affecting our driver programming interface or binary interface. For two wireless drivers, remove unnecessary locking, since they don't actually access the multicast address list. Approved by: re (kib) MFC after: 6 weeks
2009-06-26 11:45:06 +00:00
if_maddr_rlock(ifp);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if ((sc->vr_quirks & VR_Q_CAM) != 0) {
/*
* For hardwares that have CAM capability, use
* 32 entries multicast perfect filter.
*/
cam_mask = 0;
ifnet: Replace if_addr_lock rwlock with epoch + mutex Run on LLNW canaries and tested by pho@ gallatin: Using a 14-core, 28-HTT single socket E5-2697 v3 with a 40GbE MLX5 based ConnectX 4-LX NIC, I see an almost 12% improvement in received packet rate, and a larger improvement in bytes delivered all the way to userspace. When the host receiving 64 streams of netperf -H $DUT -t UDP_STREAM -- -m 1, I see, using nstat -I mce0 1 before the patch: InMpps OMpps InGbs OGbs err TCP Est %CPU syscalls csw irq GBfree 4.98 0.00 4.42 0.00 4235592 33 83.80 4720653 2149771 1235 247.32 4.73 0.00 4.20 0.00 4025260 33 82.99 4724900 2139833 1204 247.32 4.72 0.00 4.20 0.00 4035252 33 82.14 4719162 2132023 1264 247.32 4.71 0.00 4.21 0.00 4073206 33 83.68 4744973 2123317 1347 247.32 4.72 0.00 4.21 0.00 4061118 33 80.82 4713615 2188091 1490 247.32 4.72 0.00 4.21 0.00 4051675 33 85.29 4727399 2109011 1205 247.32 4.73 0.00 4.21 0.00 4039056 33 84.65 4724735 2102603 1053 247.32 After the patch InMpps OMpps InGbs OGbs err TCP Est %CPU syscalls csw irq GBfree 5.43 0.00 4.20 0.00 3313143 33 84.96 5434214 1900162 2656 245.51 5.43 0.00 4.20 0.00 3308527 33 85.24 5439695 1809382 2521 245.51 5.42 0.00 4.19 0.00 3316778 33 87.54 5416028 1805835 2256 245.51 5.42 0.00 4.19 0.00 3317673 33 90.44 5426044 1763056 2332 245.51 5.42 0.00 4.19 0.00 3314839 33 88.11 5435732 1792218 2499 245.52 5.44 0.00 4.19 0.00 3293228 33 91.84 5426301 1668597 2121 245.52 Similarly, netperf reports 230Mb/s before the patch, and 270Mb/s after the patch Reviewed by: gallatin Sponsored by: Limelight Networks Differential Revision: https://reviews.freebsd.org/D15366
2018-05-18 20:13:34 +00:00
CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (ifma->ifma_addr->sa_family != AF_LINK)
continue;
Fix a multicast handling regression on VT6105M introduced in vr(4) overhauling(r177050). It seems that filtering multicast addresses with multicast CAM entries require accessing 'CAM enable bit' for each CAM entry. Subsequent accessing multicast CAM control register without toggling the 'CAM enable bit' seem to no effects. In order to fix that separate CAM setup from CAM mask configuration and CAM entry modification. While I'm here add VLAN CAM filtering feature which will be enabled in future(FreeBSD now can receive VLAN id insertion/removal event from vlan(4) on the fly). For VT6105M hardware, explicitly disable VLAN hardware tag insertion/stripping and enable VLAN CAM filtering for VLAN id 0. This shall make non-VLAN frames set VR_RXSTAT_VIDHIT bit in Rx status word. Added multicast/VLAN CAM address definition to header file. PR: kern/125010, kern/125024 MFC after: 1 week
2008-07-16 08:35:29 +00:00
error = vr_cam_data(sc, VR_MCAST_CAM, mcnt,
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
if (error != 0) {
cam_mask = 0;
break;
}
cam_mask |= 1 << mcnt;
mcnt++;
}
Fix a multicast handling regression on VT6105M introduced in vr(4) overhauling(r177050). It seems that filtering multicast addresses with multicast CAM entries require accessing 'CAM enable bit' for each CAM entry. Subsequent accessing multicast CAM control register without toggling the 'CAM enable bit' seem to no effects. In order to fix that separate CAM setup from CAM mask configuration and CAM entry modification. While I'm here add VLAN CAM filtering feature which will be enabled in future(FreeBSD now can receive VLAN id insertion/removal event from vlan(4) on the fly). For VT6105M hardware, explicitly disable VLAN hardware tag insertion/stripping and enable VLAN CAM filtering for VLAN id 0. This shall make non-VLAN frames set VR_RXSTAT_VIDHIT bit in Rx status word. Added multicast/VLAN CAM address definition to header file. PR: kern/125010, kern/125024 MFC after: 1 week
2008-07-16 08:35:29 +00:00
vr_cam_mask(sc, VR_MCAST_CAM, cam_mask);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
}
if ((sc->vr_quirks & VR_Q_CAM) == 0 || error != 0) {
/*
* If there are too many multicast addresses or
* setting multicast CAM filter failed, use hash
* table based filtering.
*/
Fix a multicast handling regression on VT6105M introduced in vr(4) overhauling(r177050). It seems that filtering multicast addresses with multicast CAM entries require accessing 'CAM enable bit' for each CAM entry. Subsequent accessing multicast CAM control register without toggling the 'CAM enable bit' seem to no effects. In order to fix that separate CAM setup from CAM mask configuration and CAM entry modification. While I'm here add VLAN CAM filtering feature which will be enabled in future(FreeBSD now can receive VLAN id insertion/removal event from vlan(4) on the fly). For VT6105M hardware, explicitly disable VLAN hardware tag insertion/stripping and enable VLAN CAM filtering for VLAN id 0. This shall make non-VLAN frames set VR_RXSTAT_VIDHIT bit in Rx status word. Added multicast/VLAN CAM address definition to header file. PR: kern/125010, kern/125024 MFC after: 1 week
2008-07-16 08:35:29 +00:00
mcnt = 0;
ifnet: Replace if_addr_lock rwlock with epoch + mutex Run on LLNW canaries and tested by pho@ gallatin: Using a 14-core, 28-HTT single socket E5-2697 v3 with a 40GbE MLX5 based ConnectX 4-LX NIC, I see an almost 12% improvement in received packet rate, and a larger improvement in bytes delivered all the way to userspace. When the host receiving 64 streams of netperf -H $DUT -t UDP_STREAM -- -m 1, I see, using nstat -I mce0 1 before the patch: InMpps OMpps InGbs OGbs err TCP Est %CPU syscalls csw irq GBfree 4.98 0.00 4.42 0.00 4235592 33 83.80 4720653 2149771 1235 247.32 4.73 0.00 4.20 0.00 4025260 33 82.99 4724900 2139833 1204 247.32 4.72 0.00 4.20 0.00 4035252 33 82.14 4719162 2132023 1264 247.32 4.71 0.00 4.21 0.00 4073206 33 83.68 4744973 2123317 1347 247.32 4.72 0.00 4.21 0.00 4061118 33 80.82 4713615 2188091 1490 247.32 4.72 0.00 4.21 0.00 4051675 33 85.29 4727399 2109011 1205 247.32 4.73 0.00 4.21 0.00 4039056 33 84.65 4724735 2102603 1053 247.32 After the patch InMpps OMpps InGbs OGbs err TCP Est %CPU syscalls csw irq GBfree 5.43 0.00 4.20 0.00 3313143 33 84.96 5434214 1900162 2656 245.51 5.43 0.00 4.20 0.00 3308527 33 85.24 5439695 1809382 2521 245.51 5.42 0.00 4.19 0.00 3316778 33 87.54 5416028 1805835 2256 245.51 5.42 0.00 4.19 0.00 3317673 33 90.44 5426044 1763056 2332 245.51 5.42 0.00 4.19 0.00 3314839 33 88.11 5435732 1792218 2499 245.52 5.44 0.00 4.19 0.00 3293228 33 91.84 5426301 1668597 2121 245.52 Similarly, netperf reports 230Mb/s before the patch, and 270Mb/s after the patch Reviewed by: gallatin Sponsored by: Limelight Networks Differential Revision: https://reviews.freebsd.org/D15366
2018-05-18 20:13:34 +00:00
CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (ifma->ifma_addr->sa_family != AF_LINK)
continue;
h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
if (h < 32)
hashes[0] |= (1 << h);
else
hashes[1] |= (1 << (h - 32));
mcnt++;
}
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
Use if_maddr_rlock()/if_maddr_runlock() rather than IF_ADDR_LOCK()/ IF_ADDR_UNLOCK() across network device drivers when accessing the per-interface multicast address list, if_multiaddrs. This will allow us to change the locking strategy without affecting our driver programming interface or binary interface. For two wireless drivers, remove unnecessary locking, since they don't actually access the multicast address list. Approved by: re (kib) MFC after: 6 weeks
2009-06-26 11:45:06 +00:00
if_maddr_runlock(ifp);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (mcnt > 0)
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
rxfilt |= VR_RXCFG_RX_MULTI;
CSR_WRITE_4(sc, VR_MAR0, hashes[0]);
CSR_WRITE_4(sc, VR_MAR1, hashes[1]);
CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
}
style: put return types on a line by themselves.
2002-08-24 00:02:03 +00:00
static void
Run if_vr(4) through FlexeLint and clean some of the cobwebs found.
2007-04-22 12:55:36 +00:00
vr_reset(const struct vr_softc *sc)
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
{
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
int i;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
- Use if_printf() and device_printf() and remove vr_unit from the softc. I had to initialize the ifnet a bit earlier in attach so that the if_printf()'s in vr_reset() didn't explode with a page fault. - Use M_ZERO with contigmalloc() rather than an explicit bzero.
2005-10-27 21:18:37 +00:00
/*VR_LOCK_ASSERT(sc);*/ /* XXX: Called during attach w/o lock. */
SMPng locking cleanup for vr(4). - Remove recursive locking situations. Remove the MTX_RECURSE bit. - Take the lock for any routine which is not called from within if_vr.c itself; this includes entry points called by newbus, ifnet, callout, ifmedia, and polling subsystems. - Remove spl references from the code added to miibus callbacks in rev 1.60. - Add the INTR_MPSAFE bit. - Tidy up some assignments; locks are not needed for taking the address of something at a known offset, for example. - Tested on the machine this was committed from. Tested on: UP only, !debug.mpsafenet && debug.mpsafenet Reviewed by: rwatson
2004-07-03 02:59:02 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
CSR_WRITE_1(sc, VR_CR1, VR_CR1_RESET);
if (sc->vr_revid < REV_ID_VT6102_A) {
/* VT86C100A needs more delay after reset. */
DELAY(100);
}
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
for (i = 0; i < VR_TIMEOUT; i++) {
DELAY(10);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (!(CSR_READ_1(sc, VR_CR1) & VR_CR1_RESET))
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
break;
}
Import some relevant changes from Via's if_fet driver: 1. Detect the revision of the Rhine chip we're using. 2. Use the force reset command on revisions which support it whenever the normal reset command fails. This should solve a wide range of "my vr0 locks up with reset failed messages" problems. (Although the root causes should be eventually tracked down.) Tested by: grenville armitage <garmitage@swin.edu.au> Obtained from: Via's if_fet driver MFC after: 3 days Approved by: re
2002-11-25 05:15:27 +00:00
if (i == VR_TIMEOUT) {
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (sc->vr_revid < REV_ID_VT6102_A)
Consistently use if_printf() only in interface methods: if_start, if_ioctl, if_watchdog, etc, or in functions that are used by these methods only. In all other cases use device_printf(). This also fixes several panics, when if_printf() is called before softc->ifp was initialized. Submitted by: Alex Lyashkov <umka sevcity.net>
2006-09-15 10:40:54 +00:00
device_printf(sc->vr_dev, "reset never completed!\n");
Import some relevant changes from Via's if_fet driver: 1. Detect the revision of the Rhine chip we're using. 2. Use the force reset command on revisions which support it whenever the normal reset command fails. This should solve a wide range of "my vr0 locks up with reset failed messages" problems. (Although the root causes should be eventually tracked down.) Tested by: grenville armitage <garmitage@swin.edu.au> Obtained from: Via's if_fet driver MFC after: 3 days Approved by: re
2002-11-25 05:15:27 +00:00
else {
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
/* Use newer force reset command. */
device_printf(sc->vr_dev,
"Using force reset command.\n");
Import some relevant changes from Via's if_fet driver: 1. Detect the revision of the Rhine chip we're using. 2. Use the force reset command on revisions which support it whenever the normal reset command fails. This should solve a wide range of "my vr0 locks up with reset failed messages" problems. (Although the root causes should be eventually tracked down.) Tested by: grenville armitage <garmitage@swin.edu.au> Obtained from: Via's if_fet driver MFC after: 3 days Approved by: re
2002-11-25 05:15:27 +00:00
VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
/*
* Wait a little while for the chip to get its brains
* in order.
*/
DELAY(2000);
Import some relevant changes from Via's if_fet driver: 1. Detect the revision of the Rhine chip we're using. 2. Use the force reset command on revisions which support it whenever the normal reset command fails. This should solve a wide range of "my vr0 locks up with reset failed messages" problems. (Although the root causes should be eventually tracked down.) Tested by: grenville armitage <garmitage@swin.edu.au> Obtained from: Via's if_fet driver MFC after: 3 days Approved by: re
2002-11-25 05:15:27 +00:00
}
}
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
Improve the if_vr driver ever so slightly. The 6105M and 6102 does not have the DWORD alignment problem, so don't m_defrag() every packet in the transmit path for those. More stringent usage of tx-descriptor ring and its flags. Tested on 6102 and 6105M, other chips may also be able to run without the m_defrag() but I have neither hardware nor docs to find out. Sponsored by: Soekris Engineering
2007-04-17 12:23:57 +00:00
/*
* Probe for a VIA Rhine chip. Check the PCI vendor and device
* IDs against our list and return a match or NULL
*/
Sprinkle const.
2011-10-09 20:16:51 +00:00
static const struct vr_type *
Improve the if_vr driver ever so slightly. The 6105M and 6102 does not have the DWORD alignment problem, so don't m_defrag() every packet in the transmit path for those. More stringent usage of tx-descriptor ring and its flags. Tested on 6102 and 6105M, other chips may also be able to run without the m_defrag() but I have neither hardware nor docs to find out. Sponsored by: Soekris Engineering
2007-04-17 12:23:57 +00:00
vr_match(device_t dev)
{
Sprinkle const.
2011-10-09 20:16:51 +00:00
const struct vr_type *t = vr_devs;
Improve the if_vr driver ever so slightly. The 6105M and 6102 does not have the DWORD alignment problem, so don't m_defrag() every packet in the transmit path for those. More stringent usage of tx-descriptor ring and its flags. Tested on 6102 and 6105M, other chips may also be able to run without the m_defrag() but I have neither hardware nor docs to find out. Sponsored by: Soekris Engineering
2007-04-17 12:23:57 +00:00
for (t = vr_devs; t->vr_name != NULL; t++)
if ((pci_get_vendor(dev) == t->vr_vid) &&
(pci_get_device(dev) == t->vr_did))
return (t);
return (NULL);
}
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
/*
* Probe for a VIA Rhine chip. Check the PCI vendor and device
* IDs against our list and return a device name if we find a match.
*/
style: put return types on a line by themselves.
2002-08-24 00:02:03 +00:00
static int
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
vr_probe(device_t dev)
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
{
Sprinkle const.
2011-10-09 20:16:51 +00:00
const struct vr_type *t;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Improve the if_vr driver ever so slightly. The 6105M and 6102 does not have the DWORD alignment problem, so don't m_defrag() every packet in the transmit path for those. More stringent usage of tx-descriptor ring and its flags. Tested on 6102 and 6105M, other chips may also be able to run without the m_defrag() but I have neither hardware nor docs to find out. Sponsored by: Soekris Engineering
2007-04-17 12:23:57 +00:00
t = vr_match(dev);
if (t != NULL) {
device_set_desc(dev, t->vr_name);
return (BUS_PROBE_DEFAULT);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
return (ENXIO);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
/*
* Attach the interface. Allocate softc structures, do ifmedia
* setup and ethernet/BPF attach.
*/
style: put return types on a line by themselves.
2002-08-24 00:02:03 +00:00
static int
Run if_vr(4) through FlexeLint and clean some of the cobwebs found.
2007-04-22 12:55:36 +00:00
vr_attach(device_t dev)
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
{
struct vr_softc *sc;
struct ifnet *ifp;
Sprinkle const.
2011-10-09 20:16:51 +00:00
const struct vr_type *t;
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
uint8_t eaddr[ETHER_ADDR_LEN];
int error, rid;
Convert the PHY drivers to honor the mii_flags passed down and convert the NIC drivers as well as the PHY drivers to take advantage of the mii_attach() introduced in r213878 to get rid of certain hacks. For the most part these were: - Artificially limiting miibus_{read,write}reg methods to certain PHY addresses; we now let mii_attach() only probe the PHY at the desired address(es) instead. - PHY drivers setting MIIF_* flags based on the NIC driver they hang off from, partly even based on grabbing and using the softc of the parent; we now pass these flags down from the NIC to the PHY drivers via mii_attach(). This got us rid of all such hacks except those of brgphy() in combination with bce(4) and bge(4), which is way beyond what can be expressed with simple flags. While at it, I took the opportunity to change the NIC drivers to pass up the error returned by mii_attach() (previously by mii_phy_probe()) and unify the error message used in this case where and as appropriate as mii_attach() actually can fail for a number of reasons, not just because of no PHY(s) being present at the expected address(es). Reviewed by: jhb, yongari
2010-10-15 14:52:11 +00:00
int i, phy, pmc;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Convert the VIA Rhine driver to newbus and set it up to be compiled as a module. Also modified the code to work on FreeBSD/alpha and added device vr0 to the alpha GENERIC config. While I was in the neighborhood, I noticed that I was still using #define NFPX 1 in all of the Makefiles that I'd copied from the fxp module. I don't really use #define Nfoo X so it didn't matter, but I decided to customize this correctly anyway.
1999-08-10 17:15:20 +00:00
sc = device_get_softc(dev);
Consistently use if_printf() only in interface methods: if_start, if_ioctl, if_watchdog, etc, or in functions that are used by these methods only. In all other cases use device_printf(). This also fixes several panics, when if_printf() is called before softc->ifp was initialized. Submitted by: Alex Lyashkov <umka sevcity.net>
2006-09-15 10:40:54 +00:00
sc->vr_dev = dev;
Improve the if_vr driver ever so slightly. The 6105M and 6102 does not have the DWORD alignment problem, so don't m_defrag() every packet in the transmit path for those. More stringent usage of tx-descriptor ring and its flags. Tested on 6102 and 6105M, other chips may also be able to run without the m_defrag() but I have neither hardware nor docs to find out. Sponsored by: Soekris Engineering
2007-04-17 12:23:57 +00:00
t = vr_match(dev);
KASSERT(t != NULL, ("Lost if_vr device match"));
sc->vr_quirks = t->vr_quirks;
device_printf(dev, "Quirks: 0x%x\n", sc->vr_quirks);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Change callers of mtx_init() to pass in an appropriate lock type name. In most cases NULL is passed, but in some cases such as network driver locks (which use the MTX_NETWORK_LOCK macro) and UMA zone locks, a name is used. Tested on: i386, alpha, sparc64
2002-04-04 21:03:38 +00:00
mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
SMPng locking cleanup for vr(4). - Remove recursive locking situations. Remove the MTX_RECURSE bit. - Take the lock for any routine which is not called from within if_vr.c itself; this includes entry points called by newbus, ifnet, callout, ifmedia, and polling subsystems. - Remove spl references from the code added to miibus callbacks in rev 1.60. - Add the INTR_MPSAFE bit. - Tidy up some assignments; locks are not needed for taking the address of something at a known offset, for example. - Tested on the machine this was committed from. Tested on: UP only, !debug.mpsafenet && debug.mpsafenet Reviewed by: rwatson
2004-07-03 02:59:02 +00:00
MTX_DEF);
- Use callout_*() to manage the callout and make it MPSAFE. - Fix locking in detach(), we only need to lock across vr_stop(). Tested by: Mike Tancsa mike at sentex dot net MFC after: 1 week
2005-10-31 21:37:27 +00:00
callout_init_mtx(&sc->vr_stat_callout, &sc->vr_mtx, 0);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
OID_AUTO, "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
vr_sysctl_stats, "I", "Statistics");
error = 0;
- Use callout_*() to manage the callout and make it MPSAFE. - Fix locking in detach(), we only need to lock across vr_stop(). Tested by: Mike Tancsa mike at sentex dot net MFC after: 1 week
2005-10-31 21:37:27 +00:00
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
/*
* Map control/status registers.
*/
Big round of minor updates: - Use pci_get_powerstate()/pci_set_powerstate() in all the other drivers that need them so we don't have to fiddle with the PCI power management registers directly. - Use pci_enable_busmaster()/pci_enable_io() to turn on busmastering and PIO/memory mapped accesses. - Add support to the RealTek driver for the D-Link DFE-530TX+ which has a RealTek 8139 with its own PCI ID. (Submitted by Jason Wright) - Have the SiS 900/National DP83815 driver be sure to disable PME mode in sis_reset(). This apparently fixes a problem on some motherboards where the DP83815 chip fails to receive packets. (Submitted by Chuck McCrobie <mccrobie@cablespeed.com>)
2001-02-21 20:54:22 +00:00
pci_enable_busmaster(dev);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc->vr_revid = pci_get_revid(dev);
device_printf(dev, "Revision: 0x%x\n", sc->vr_revid);
Convert the VIA Rhine driver to newbus and set it up to be compiled as a module. Also modified the code to work on FreeBSD/alpha and added device vr0 to the alpha GENERIC config. While I was in the neighborhood, I noticed that I was still using #define NFPX 1 in all of the Makefiles that I'd copied from the fxp module. I don't really use #define Nfoo X so it didn't matter, but I decided to customize this correctly anyway.
1999-08-10 17:15:20 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc->vr_res_id = PCIR_BAR(0);
sc->vr_res_type = SYS_RES_IOPORT;
sc->vr_res = bus_alloc_resource_any(dev, sc->vr_res_type,
&sc->vr_res_id, RF_ACTIVE);
Convert the VIA Rhine driver to newbus and set it up to be compiled as a module. Also modified the code to work on FreeBSD/alpha and added device vr0 to the alpha GENERIC config. While I was in the neighborhood, I noticed that I was still using #define NFPX 1 in all of the Makefiles that I'd copied from the fxp module. I don't really use #define Nfoo X so it didn't matter, but I decided to customize this correctly anyway.
1999-08-10 17:15:20 +00:00
if (sc->vr_res == NULL) {
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
device_printf(dev, "couldn't map ports\n");
Convert the VIA Rhine driver to newbus and set it up to be compiled as a module. Also modified the code to work on FreeBSD/alpha and added device vr0 to the alpha GENERIC config. While I was in the neighborhood, I noticed that I was still using #define NFPX 1 in all of the Makefiles that I'd copied from the fxp module. I don't really use #define Nfoo X so it didn't matter, but I decided to customize this correctly anyway.
1999-08-10 17:15:20 +00:00
error = ENXIO;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
goto fail;
}
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
/* Allocate interrupt. */
Convert the VIA Rhine driver to newbus and set it up to be compiled as a module. Also modified the code to work on FreeBSD/alpha and added device vr0 to the alpha GENERIC config. While I was in the neighborhood, I noticed that I was still using #define NFPX 1 in all of the Makefiles that I'd copied from the fxp module. I don't really use #define Nfoo X so it didn't matter, but I decided to customize this correctly anyway.
1999-08-10 17:15:20 +00:00
rid = 0;
Convert callers to the new bus_alloc_resource_any(9) API. Submitted by: Mark Santcroos <marks@ripe.net> Reviewed by: imp, dfr, bde
2004-03-17 17:50:55 +00:00
sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
Convert the VIA Rhine driver to newbus and set it up to be compiled as a module. Also modified the code to work on FreeBSD/alpha and added device vr0 to the alpha GENERIC config. While I was in the neighborhood, I noticed that I was still using #define NFPX 1 in all of the Makefiles that I'd copied from the fxp module. I don't really use #define Nfoo X so it didn't matter, but I decided to customize this correctly anyway.
1999-08-10 17:15:20 +00:00
RF_SHAREABLE | RF_ACTIVE);
if (sc->vr_irq == NULL) {
- Use if_printf() and device_printf() and remove vr_unit from the softc. I had to initialize the ifnet a bit earlier in attach so that the if_printf()'s in vr_reset() didn't explode with a page fault. - Use M_ZERO with contigmalloc() rather than an explicit bzero.
2005-10-27 21:18:37 +00:00
device_printf(dev, "couldn't map interrupt\n");
Convert the VIA Rhine driver to newbus and set it up to be compiled as a module. Also modified the code to work on FreeBSD/alpha and added device vr0 to the alpha GENERIC config. While I was in the neighborhood, I noticed that I was still using #define NFPX 1 in all of the Makefiles that I'd copied from the fxp module. I don't really use #define Nfoo X so it didn't matter, but I decided to customize this correctly anyway.
1999-08-10 17:15:20 +00:00
error = ENXIO;
goto fail;
}
- Use if_printf() and device_printf() and remove vr_unit from the softc. I had to initialize the ifnet a bit earlier in attach so that the if_printf()'s in vr_reset() didn't explode with a page fault. - Use M_ZERO with contigmalloc() rather than an explicit bzero.
2005-10-27 21:18:37 +00:00
/* Allocate ifnet structure. */
ifp = sc->vr_ifp = if_alloc(IFT_ETHER);
if (ifp == NULL) {
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
device_printf(dev, "couldn't allocate ifnet structure\n");
- Use if_printf() and device_printf() and remove vr_unit from the softc. I had to initialize the ifnet a bit earlier in attach so that the if_printf()'s in vr_reset() didn't explode with a page fault. - Use M_ZERO with contigmalloc() rather than an explicit bzero.
2005-10-27 21:18:37 +00:00
error = ENOSPC;
goto fail;
}
ifp->if_softc = sc;
if_initname(ifp, device_get_name(dev), device_get_unit(dev));
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = vr_ioctl;
ifp->if_start = vr_start;
ifp->if_init = vr_init;
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
IFQ_SET_MAXLEN(&ifp->if_snd, VR_TX_RING_CNT - 1);
ifp->if_snd.ifq_maxlen = VR_TX_RING_CNT - 1;
- Use if_printf() and device_printf() and remove vr_unit from the softc. I had to initialize the ifnet a bit earlier in attach so that the if_printf()'s in vr_reset() didn't explode with a page fault. - Use M_ZERO with contigmalloc() rather than an explicit bzero.
2005-10-27 21:18:37 +00:00
IFQ_SET_READY(&ifp->if_snd);
Add support for hw-assisted checksums on 6105M. Sponsored by: Soekris Engineering
2007-04-17 22:59:54 +00:00
Convert the if_vr(4) driver model to the interrupt filter model and use a taskqueue. This gives a 16% performance improvement under high load on slow systems, especially when vr shares an interrupt with another device, which is common with the Alix x86 boards. Contrary to the other devices, I left the interrupt processing for loop in because there was no significant difference in performance and this should avoid enqueuing more taskqueues unnecessarily. We also decided to move the vr_start_locked() call inside the for loop because we found out that it helps performance since TCP ACKs now have a chance to go out quicker. Reviewed by: yongari (older version, same idea) Discussed with: yongari, jhb
2012-05-12 14:37:25 +00:00
TASK_INIT(&sc->vr_inttask, 0, vr_int_task, sc);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
/* Configure Tx FIFO threshold. */
sc->vr_txthresh = VR_TXTHRESH_MIN;
if (sc->vr_revid < REV_ID_VT6105_A0) {
/*
* Use store and forward mode for Rhine I/II.
* Otherwise they produce a lot of Tx underruns and
* it would take a while to get working FIFO threshold
* value.
*/
sc->vr_txthresh = VR_TXTHRESH_MAX;
}
if ((sc->vr_quirks & VR_Q_CSUM) != 0) {
ifp->if_hwassist = VR_CSUM_FEATURES;
Add support for hw-assisted checksums on 6105M. Sponsored by: Soekris Engineering
2007-04-17 22:59:54 +00:00
ifp->if_capabilities |= IFCAP_HWCSUM;
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
/*
* To update checksum field the hardware may need to
* store entire frames into FIFO before transmitting.
*/
sc->vr_txthresh = VR_TXTHRESH_MAX;
Add support for hw-assisted checksums on 6105M. Sponsored by: Soekris Engineering
2007-04-17 22:59:54 +00:00
}
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (sc->vr_revid >= REV_ID_VT6102_A &&
Do a sweep of the tree replacing calls to pci_find_extcap() with calls to pci_find_cap() instead.
2011-03-23 13:10:15 +00:00
pci_find_cap(dev, PCIY_PMG, &pmc) == 0)
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
ifp->if_capabilities |= IFCAP_WOL_UCAST | IFCAP_WOL_MAGIC;
/* Rhine supports oversized VLAN frame. */
Add VLAN capability. Submitted by: Slawa Olhovchenkov <slw@zxy.spb.ru>
2007-04-23 12:19:02 +00:00
ifp->if_capabilities |= IFCAP_VLAN_MTU;
- Use if_printf() and device_printf() and remove vr_unit from the softc. I had to initialize the ifnet a bit earlier in attach so that the if_printf()'s in vr_reset() didn't explode with a page fault. - Use M_ZERO with contigmalloc() rather than an explicit bzero.
2005-10-27 21:18:37 +00:00
ifp->if_capenable = ifp->if_capabilities;
#ifdef DEVICE_POLLING
ifp->if_capabilities |= IFCAP_POLLING;
#endif
Close PR 22208: bring chip out of suspend mode, because Windows might have put the chip to sleep at shutdown. This is really only for the VT6102, but it doesn't hurt the older chips.
2001-05-14 19:13:02 +00:00
/*
* Windows may put the chip in suspend mode when it
* shuts down. Be sure to kick it in the head to wake it
* up again.
*/
Do a sweep of the tree replacing calls to pci_find_extcap() with calls to pci_find_cap() instead.
2011-03-23 13:10:15 +00:00
if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0)
Not all VIA Rhine chips support 256 register space. So touching VR_STICKHW register would result in unexpected results on these hardwares. wpaul said the following for the issue. The vr_attach() routine unconditionally does this for all supported chips: /* * Windows may put the chip in suspend mode when it * shuts down. Be sure to kick it in the head to wake it * up again. */ VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); The problem is, the VR_STICKHW register is not valid on all Rhine devices. The VT86C100A chip, which is present on the D-Link DFE-530TX boards, doesn't support power management, and its register space is only 128 bytes wide. The VR_STICKHW register offset falls outside this range. This may go unnoticed in most scenarios, but if you happen to have another PCI device in your system which is assigned the register space immediately after that of the Rhine, the vr(4) driver will incorrectly stomp it. In my case, the BIOS on my test board decided to put the register space for my PRO/100 ethernet board right next to the Rhine, and the Rhine driver ended up clobbering the IMR register of the PRO/100 device. (Long story short: the board kept locking up on boot. Took me the better part of the morning suss out why.) The strictly correct thing to do would be to check the PCI config space to make sure the device supports the power management capability and only write to the VR_STICKHW register if it does. Instead of inspecting chip revision numbers for the availability of VR_STICKHW register, check the existence of power management capability of the hardware as wpaul suggested. Reported by: wpaul Suggested by: wpaul OK'ed by: jhb
2007-10-12 03:32:55 +00:00
VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1));
Close PR 22208: bring chip out of suspend mode, because Windows might have put the chip to sleep at shutdown. This is really only for the VT6102, but it doesn't hurt the older chips.
2001-05-14 19:13:02 +00:00
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
/*
* Get station address. The way the Rhine chips work,
* you're not allowed to directly access the EEPROM once
* they've been programmed a special way. Consequently,
* we need to read the node address from the PAR0 and PAR1
* registers.
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
* Reloading EEPROM also overwrites VR_CFGA, VR_CFGB,
* VR_CFGC and VR_CFGD such that memory mapped IO configured
* by driver is reset to default state.
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
*/
VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
for (i = VR_TIMEOUT; i > 0; i--) {
DELAY(1);
if ((CSR_READ_1(sc, VR_EECSR) & VR_EECSR_LOAD) == 0)
break;
}
if (i == 0)
device_printf(dev, "Reloading EEPROM timeout!\n");
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
for (i = 0; i < ETHER_ADDR_LEN; i++)
eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
/* Reset the adapter. */
vr_reset(sc);
/* Ack intr & disable further interrupts. */
CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
CSR_WRITE_2(sc, VR_IMR, 0);
if (sc->vr_revid >= REV_ID_VT6102_A)
CSR_WRITE_2(sc, VR_MII_IMR, 0);
if (sc->vr_revid < REV_ID_VT6102_A) {
pci_write_config(dev, VR_PCI_MODE2,
pci_read_config(dev, VR_PCI_MODE2, 1) |
VR_MODE2_MODE10T, 1);
} else {
/* Report error instead of retrying forever. */
pci_write_config(dev, VR_PCI_MODE2,
pci_read_config(dev, VR_PCI_MODE2, 1) |
VR_MODE2_PCEROPT, 1);
/* Detect MII coding error. */
pci_write_config(dev, VR_PCI_MODE3,
pci_read_config(dev, VR_PCI_MODE3, 1) |
VR_MODE3_MIION, 1);
if (sc->vr_revid >= REV_ID_VT6105_LOM &&
sc->vr_revid < REV_ID_VT6105M_A0)
pci_write_config(dev, VR_PCI_MODE2,
pci_read_config(dev, VR_PCI_MODE2, 1) |
VR_MODE2_MODE10T, 1);
/* Enable Memory-Read-Multiple. */
if (sc->vr_revid >= REV_ID_VT6107_A1 &&
sc->vr_revid < REV_ID_VT6105M_A0)
pci_write_config(dev, VR_PCI_MODE2,
pci_read_config(dev, VR_PCI_MODE2, 1) |
VR_MODE2_MRDPL, 1);
}
/* Disable MII AUTOPOLL. */
VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL);
Convert the VIA Rhine driver to miibus.
1999-09-19 22:03:31 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (vr_dma_alloc(sc) != 0) {
Convert the VIA Rhine driver to newbus and set it up to be compiled as a module. Also modified the code to work on FreeBSD/alpha and added device vr0 to the alpha GENERIC config. While I was in the neighborhood, I noticed that I was still using #define NFPX 1 in all of the Makefiles that I'd copied from the fxp module. I don't really use #define Nfoo X so it didn't matter, but I decided to customize this correctly anyway.
1999-08-10 17:15:20 +00:00
error = ENXIO;
goto fail;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
Convert the PHY drivers to honor the mii_flags passed down and convert the NIC drivers as well as the PHY drivers to take advantage of the mii_attach() introduced in r213878 to get rid of certain hacks. For the most part these were: - Artificially limiting miibus_{read,write}reg methods to certain PHY addresses; we now let mii_attach() only probe the PHY at the desired address(es) instead. - PHY drivers setting MIIF_* flags based on the NIC driver they hang off from, partly even based on grabbing and using the softc of the parent; we now pass these flags down from the NIC to the PHY drivers via mii_attach(). This got us rid of all such hacks except those of brgphy() in combination with bce(4) and bge(4), which is way beyond what can be expressed with simple flags. While at it, I took the opportunity to change the NIC drivers to pass up the error returned by mii_attach() (previously by mii_phy_probe()) and unify the error message used in this case where and as appropriate as mii_attach() actually can fail for a number of reasons, not just because of no PHY(s) being present at the expected address(es). Reviewed by: jhb, yongari
2010-10-15 14:52:11 +00:00
/* Do MII setup. */
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (sc->vr_revid >= REV_ID_VT6105_A0)
Convert the PHY drivers to honor the mii_flags passed down and convert the NIC drivers as well as the PHY drivers to take advantage of the mii_attach() introduced in r213878 to get rid of certain hacks. For the most part these were: - Artificially limiting miibus_{read,write}reg methods to certain PHY addresses; we now let mii_attach() only probe the PHY at the desired address(es) instead. - PHY drivers setting MIIF_* flags based on the NIC driver they hang off from, partly even based on grabbing and using the softc of the parent; we now pass these flags down from the NIC to the PHY drivers via mii_attach(). This got us rid of all such hacks except those of brgphy() in combination with bce(4) and bge(4), which is way beyond what can be expressed with simple flags. While at it, I took the opportunity to change the NIC drivers to pass up the error returned by mii_attach() (previously by mii_phy_probe()) and unify the error message used in this case where and as appropriate as mii_attach() actually can fail for a number of reasons, not just because of no PHY(s) being present at the expected address(es). Reviewed by: jhb, yongari
2010-10-15 14:52:11 +00:00
phy = 1;
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
else
Convert the PHY drivers to honor the mii_flags passed down and convert the NIC drivers as well as the PHY drivers to take advantage of the mii_attach() introduced in r213878 to get rid of certain hacks. For the most part these were: - Artificially limiting miibus_{read,write}reg methods to certain PHY addresses; we now let mii_attach() only probe the PHY at the desired address(es) instead. - PHY drivers setting MIIF_* flags based on the NIC driver they hang off from, partly even based on grabbing and using the softc of the parent; we now pass these flags down from the NIC to the PHY drivers via mii_attach(). This got us rid of all such hacks except those of brgphy() in combination with bce(4) and bge(4), which is way beyond what can be expressed with simple flags. While at it, I took the opportunity to change the NIC drivers to pass up the error returned by mii_attach() (previously by mii_phy_probe()) and unify the error message used in this case where and as appropriate as mii_attach() actually can fail for a number of reasons, not just because of no PHY(s) being present at the expected address(es). Reviewed by: jhb, yongari
2010-10-15 14:52:11 +00:00
phy = CSR_READ_1(sc, VR_PHYADDR) & VR_PHYADDR_MASK;
error = mii_attach(dev, &sc->vr_miibus, ifp, vr_ifmedia_upd,
Announce flow control capability to PHY drivers and enable flow control for all vr(4) controllers that support it. It's known that old vr(4) controllers(Rhine II) does not support TX pause but Rhine III supports both TX and RX pause. Make TX pause really work on Rhine III by letting controller know available RX buffers. While here, adjust XON/XOFF parameters to get better performance with flow control.
2011-11-28 19:03:59 +00:00
vr_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY,
sc->vr_revid >= REV_ID_VT6102_A ? MIIF_DOPAUSE : 0);
Convert the PHY drivers to honor the mii_flags passed down and convert the NIC drivers as well as the PHY drivers to take advantage of the mii_attach() introduced in r213878 to get rid of certain hacks. For the most part these were: - Artificially limiting miibus_{read,write}reg methods to certain PHY addresses; we now let mii_attach() only probe the PHY at the desired address(es) instead. - PHY drivers setting MIIF_* flags based on the NIC driver they hang off from, partly even based on grabbing and using the softc of the parent; we now pass these flags down from the NIC to the PHY drivers via mii_attach(). This got us rid of all such hacks except those of brgphy() in combination with bce(4) and bge(4), which is way beyond what can be expressed with simple flags. While at it, I took the opportunity to change the NIC drivers to pass up the error returned by mii_attach() (previously by mii_phy_probe()) and unify the error message used in this case where and as appropriate as mii_attach() actually can fail for a number of reasons, not just because of no PHY(s) being present at the expected address(es). Reviewed by: jhb, yongari
2010-10-15 14:52:11 +00:00
if (error != 0) {
device_printf(dev, "attaching PHYs failed\n");
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
goto fail;
}
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
/* Call MI attach routine. */
o track either_ifattach/ether_ifdetach API changes o use if_input for input packet processing o don't strip the Ethernet header for input packets o use BPF_* macros bpf tapping o call ether_ioctl to handle default ioctl case o track vlan changes Reviewed by: many Approved by: re
2002-11-14 23:49:09 +00:00
ether_ifattach(ifp, eaddr);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
/*
* Tell the upper layer(s) we support long frames.
* Must appear after the call to ether_ifattach() because
* ether_ifattach() sets ifi_hdrlen to the default value.
*/
Use define from if_var.h to access a field inside struct if_data, that resides in struct ifnet. Sponsored by: Nginx, Inc.
2014-08-30 19:55:54 +00:00
ifp->if_hdrlen = sizeof(struct ether_vlan_header);
Clean up locking and resource management for pci/if_* - Remove locking of the softc in the attach method, instead depending on bus_setup_intr being at the end of attach (delaying interrupt enable until after ether_ifattach is called) - Call *_detach directly in the error case of attach, depending on checking in detach to only free resources that were allocated. This puts all resource freeing in one place, avoiding thinkos that lead to memory leaks. - Add bus_child_present check to calls to *_stop in the detach method to be sure hw is present before touching its registers. - Remove bzero softc calls since device_t should do this for us. - dc: move interrupt allocation back where it was before. It was unnecessary to move it. This reverts part of 1.88 - rl: move irq allocation before ether_ifattach. Problems might have been caused by allocating the irq after enabling interrupts on the card. - rl: call rl_stop before ether_ifdetach - sf: call sf_stop before ether_ifdetach - sis: add missed free of sis_tag - sis: check errors from tag creation - sis: move dmamem_alloc and dmamap_load to happen at same time as tag creation - sk: remove duplicate initialization of sk_dev - ste: add missed bus_generic_detach - ti: call ti_stop before ether_ifdetach - ti: add missed error setting in ti_rdata alloc failure - vr: add missed error setting in I/O, memory mapping cases - xl: add missed error setting in I/O, memory mapping cases - xl: remove multi-level goto on attach failure - xl: move dmamem_alloc and dmamap_load to happen at same time as tag creation - Calls to free(9) are unconditional because it is valid to call free with a null pointer. Reviewed by: imp, mdodd
2003-03-31 17:29:43 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
/* Hook interrupt last to avoid having to lock softc. */
SMPng locking cleanup for vr(4). - Remove recursive locking situations. Remove the MTX_RECURSE bit. - Take the lock for any routine which is not called from within if_vr.c itself; this includes entry points called by newbus, ifnet, callout, ifmedia, and polling subsystems. - Remove spl references from the code added to miibus callbacks in rev 1.60. - Add the INTR_MPSAFE bit. - Tidy up some assignments; locks are not needed for taking the address of something at a known offset, for example. - Tested on the machine this was committed from. Tested on: UP only, !debug.mpsafenet && debug.mpsafenet Reviewed by: rwatson
2004-07-03 02:59:02 +00:00
error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET | INTR_MPSAFE,
Convert the if_vr(4) driver model to the interrupt filter model and use a taskqueue. This gives a 16% performance improvement under high load on slow systems, especially when vr shares an interrupt with another device, which is common with the Alix x86 boards. Contrary to the other devices, I left the interrupt processing for loop in because there was no significant difference in performance and this should avoid enqueuing more taskqueues unnecessarily. We also decided to move the vr_start_locked() call inside the for loop because we found out that it helps performance since TCP ACKs now have a chance to go out quicker. Reviewed by: yongari (older version, same idea) Discussed with: yongari, jhb
2012-05-12 14:37:25 +00:00
vr_intr, NULL, sc, &sc->vr_intrhand);
Clean up locking and resource management for pci/if_* - Remove locking of the softc in the attach method, instead depending on bus_setup_intr being at the end of attach (delaying interrupt enable until after ether_ifattach is called) - Call *_detach directly in the error case of attach, depending on checking in detach to only free resources that were allocated. This puts all resource freeing in one place, avoiding thinkos that lead to memory leaks. - Add bus_child_present check to calls to *_stop in the detach method to be sure hw is present before touching its registers. - Remove bzero softc calls since device_t should do this for us. - dc: move interrupt allocation back where it was before. It was unnecessary to move it. This reverts part of 1.88 - rl: move irq allocation before ether_ifattach. Problems might have been caused by allocating the irq after enabling interrupts on the card. - rl: call rl_stop before ether_ifdetach - sf: call sf_stop before ether_ifdetach - sis: add missed free of sis_tag - sis: check errors from tag creation - sis: move dmamem_alloc and dmamap_load to happen at same time as tag creation - sk: remove duplicate initialization of sk_dev - ste: add missed bus_generic_detach - ti: call ti_stop before ether_ifdetach - ti: add missed error setting in ti_rdata alloc failure - vr: add missed error setting in I/O, memory mapping cases - xl: add missed error setting in I/O, memory mapping cases - xl: remove multi-level goto on attach failure - xl: move dmamem_alloc and dmamap_load to happen at same time as tag creation - Calls to free(9) are unconditional because it is valid to call free with a null pointer. Reviewed by: imp, mdodd
2003-03-31 17:29:43 +00:00
if (error) {
- Use if_printf() and device_printf() and remove vr_unit from the softc. I had to initialize the ifnet a bit earlier in attach so that the if_printf()'s in vr_reset() didn't explode with a page fault. - Use M_ZERO with contigmalloc() rather than an explicit bzero.
2005-10-27 21:18:37 +00:00
device_printf(dev, "couldn't set up irq\n");
Revise attach/detach resource cleanup - Unconditionally call *_stop() if device is in the tree. This is to prevent callouts from happening after the device is gone. Checks for bus_child_present() should be added in the future to keep from touching potentially non-existent hardware in *_detach(). Found by iedowse@. - Always check for and free miibus children, even if the device is not in the tree since some failure cases could have gotten here. - Call ether_ifdetach() in the irq setup failure case - ti(4), xl(4): move ifmedia_init() calls to the beginning of attach so that ifmedia_removeall() can be unconditionally called on detach. There is no way to detect whether ifmedia has been initialized without using a separate variable (as tl(4) does). - Add comments to indicate assumptions of code path
2003-04-17 20:32:06 +00:00
ether_ifdetach(ifp);
Clean up locking and resource management for pci/if_* - Remove locking of the softc in the attach method, instead depending on bus_setup_intr being at the end of attach (delaying interrupt enable until after ether_ifattach is called) - Call *_detach directly in the error case of attach, depending on checking in detach to only free resources that were allocated. This puts all resource freeing in one place, avoiding thinkos that lead to memory leaks. - Add bus_child_present check to calls to *_stop in the detach method to be sure hw is present before touching its registers. - Remove bzero softc calls since device_t should do this for us. - dc: move interrupt allocation back where it was before. It was unnecessary to move it. This reverts part of 1.88 - rl: move irq allocation before ether_ifattach. Problems might have been caused by allocating the irq after enabling interrupts on the card. - rl: call rl_stop before ether_ifdetach - sf: call sf_stop before ether_ifdetach - sis: add missed free of sis_tag - sis: check errors from tag creation - sis: move dmamem_alloc and dmamap_load to happen at same time as tag creation - sk: remove duplicate initialization of sk_dev - ste: add missed bus_generic_detach - ti: call ti_stop before ether_ifdetach - ti: add missed error setting in ti_rdata alloc failure - vr: add missed error setting in I/O, memory mapping cases - xl: add missed error setting in I/O, memory mapping cases - xl: remove multi-level goto on attach failure - xl: move dmamem_alloc and dmamap_load to happen at same time as tag creation - Calls to free(9) are unconditional because it is valid to call free with a null pointer. Reviewed by: imp, mdodd
2003-03-31 17:29:43 +00:00
goto fail;
}
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
fail:
Clean up locking and resource management for pci/if_* - Remove locking of the softc in the attach method, instead depending on bus_setup_intr being at the end of attach (delaying interrupt enable until after ether_ifattach is called) - Call *_detach directly in the error case of attach, depending on checking in detach to only free resources that were allocated. This puts all resource freeing in one place, avoiding thinkos that lead to memory leaks. - Add bus_child_present check to calls to *_stop in the detach method to be sure hw is present before touching its registers. - Remove bzero softc calls since device_t should do this for us. - dc: move interrupt allocation back where it was before. It was unnecessary to move it. This reverts part of 1.88 - rl: move irq allocation before ether_ifattach. Problems might have been caused by allocating the irq after enabling interrupts on the card. - rl: call rl_stop before ether_ifdetach - sf: call sf_stop before ether_ifdetach - sis: add missed free of sis_tag - sis: check errors from tag creation - sis: move dmamem_alloc and dmamap_load to happen at same time as tag creation - sk: remove duplicate initialization of sk_dev - ste: add missed bus_generic_detach - ti: call ti_stop before ether_ifdetach - ti: add missed error setting in ti_rdata alloc failure - vr: add missed error setting in I/O, memory mapping cases - xl: add missed error setting in I/O, memory mapping cases - xl: remove multi-level goto on attach failure - xl: move dmamem_alloc and dmamap_load to happen at same time as tag creation - Calls to free(9) are unconditional because it is valid to call free with a null pointer. Reviewed by: imp, mdodd
2003-03-31 17:29:43 +00:00
if (error)
vr_detach(dev);
First round of converting network drivers from spls to mutexes. This takes care of all the 10/100 and gigE PCI drivers that I've done. Next will be the wireless drivers, then the USB ones. I may pick up some stragglers along the way. I'm sort of playing this by ear: if anyone spots any places where I've screwed up horribly, please let me know.
2000-10-13 17:54:19 +00:00
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
return (error);
Convert the VIA Rhine driver to newbus and set it up to be compiled as a module. Also modified the code to work on FreeBSD/alpha and added device vr0 to the alpha GENERIC config. While I was in the neighborhood, I noticed that I was still using #define NFPX 1 in all of the Makefiles that I'd copied from the fxp module. I don't really use #define Nfoo X so it didn't matter, but I decided to customize this correctly anyway.
1999-08-10 17:15:20 +00:00
}
Revise attach/detach resource cleanup - Unconditionally call *_stop() if device is in the tree. This is to prevent callouts from happening after the device is gone. Checks for bus_child_present() should be added in the future to keep from touching potentially non-existent hardware in *_detach(). Found by iedowse@. - Always check for and free miibus children, even if the device is not in the tree since some failure cases could have gotten here. - Call ether_ifdetach() in the irq setup failure case - ti(4), xl(4): move ifmedia_init() calls to the beginning of attach so that ifmedia_removeall() can be unconditionally called on detach. There is no way to detect whether ifmedia has been initialized without using a separate variable (as tl(4) does). - Add comments to indicate assumptions of code path
2003-04-17 20:32:06 +00:00
/*
* Shutdown hardware and free up resources. This can be called any
* time after the mutex has been initialized. It is called in both
* the error case in attach and the normal detach case so it needs
* to be careful about only freeing resources that have actually been
* allocated.
*/
style: put return types on a line by themselves.
2002-08-24 00:02:03 +00:00
static int
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
vr_detach(device_t dev)
Convert the VIA Rhine driver to newbus and set it up to be compiled as a module. Also modified the code to work on FreeBSD/alpha and added device vr0 to the alpha GENERIC config. While I was in the neighborhood, I noticed that I was still using #define NFPX 1 in all of the Makefiles that I'd copied from the fxp module. I don't really use #define Nfoo X so it didn't matter, but I decided to customize this correctly anyway.
1999-08-10 17:15:20 +00:00
{
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
struct vr_softc *sc = device_get_softc(dev);
Stop embedding struct ifnet at the top of driver softcs. Instead the struct ifnet or the layer 2 common structure it was embedded in have been replaced with a struct ifnet pointer to be filled by a call to the new function, if_alloc(). The layer 2 common structure is also allocated via if_alloc() based on the interface type. It is hung off the new struct ifnet member, if_l2com. This change removes the size of these structures from the kernel ABI and will allow us to better manage them as interfaces come and go. Other changes of note: - Struct arpcom is no longer referenced in normal interface code. Instead the Ethernet address is accessed via the IFP2ENADDR() macro. To enforce this ac_enaddr has been renamed to _ac_enaddr. - The second argument to ether_ifattach is now always the mac address from driver private storage rather than sometimes being ac_enaddr. Reviewed by: sobomax, sam
2005-06-10 16:49:24 +00:00
struct ifnet *ifp = sc->vr_ifp;
Convert the VIA Rhine driver to newbus and set it up to be compiled as a module. Also modified the code to work on FreeBSD/alpha and added device vr0 to the alpha GENERIC config. While I was in the neighborhood, I noticed that I was still using #define NFPX 1 in all of the Makefiles that I'd copied from the fxp module. I don't really use #define Nfoo X so it didn't matter, but I decided to customize this correctly anyway.
1999-08-10 17:15:20 +00:00
Add missing ()'s so that these drivers all compile again. Noticed by: jake Tested on: i386 (compile)
2003-03-31 20:22:00 +00:00
KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized"));
SMPng locking cleanup for vr(4). - Remove recursive locking situations. Remove the MTX_RECURSE bit. - Take the lock for any routine which is not called from within if_vr.c itself; this includes entry points called by newbus, ifnet, callout, ifmedia, and polling subsystems. - Remove spl references from the code added to miibus callbacks in rev 1.60. - Add the INTR_MPSAFE bit. - Tidy up some assignments; locks are not needed for taking the address of something at a known offset, for example. - Tested on the machine this was committed from. Tested on: UP only, !debug.mpsafenet && debug.mpsafenet Reviewed by: rwatson
2004-07-03 02:59:02 +00:00
Big polling(4) cleanup. o Axe poll in trap. o Axe IFF_POLLING flag from if_flags. o Rework revision 1.21 (Giant removal), in such a way that poll_mtx is not dropped during call to polling handler. This fixes problem with idle polling. o Make registration and deregistration from polling in a functional way, insted of next tick/interrupt. o Obsolete kern.polling.enable. Polling is turned on/off with ifconfig. Detailed kern_poll.c changes: - Remove polling handler flags, introduced in 1.21. The are not needed now. - Forget and do not check if_flags, if_capenable and if_drv_flags. - Call all registered polling handlers unconditionally. - Do not drop poll_mtx, when entering polling handlers. - In ether_poll() NET_LOCK_GIANT prior to locking poll_mtx. - In netisr_poll() axe the block, where polling code asks drivers to unregister. - In netisr_poll() and ether_poll() do polling always, if any handlers are present. - In ether_poll_[de]register() remove a lot of error hiding code. Assert that arguments are correct, instead. - In ether_poll_[de]register() use standard return values in case of error or success. - Introduce poll_switch() that is a sysctl handler for kern.polling.enable. poll_switch() goes through interface list and enabled/disables polling. A message that kern.polling.enable is deprecated is printed. Detailed driver changes: - On attach driver announces IFCAP_POLLING in if_capabilities, but not in if_capenable. - On detach driver calls ether_poll_deregister() if polling is enabled. - In polling handler driver obtains its lock and checks IFF_DRV_RUNNING flag. If there is no, then unlocks and returns. - In ioctl handler driver checks for IFCAP_POLLING flag requested to be set or cleared. Driver first calls ether_poll_[de]register(), then obtains driver lock and [dis/en]ables interrupts. - In interrupt handler driver checks IFCAP_POLLING flag in if_capenable. If present, then returns.This is important to protect from spurious interrupts. Reviewed by: ru, sam, jhb
2005-10-01 18:56:19 +00:00
#ifdef DEVICE_POLLING
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING)
Big polling(4) cleanup. o Axe poll in trap. o Axe IFF_POLLING flag from if_flags. o Rework revision 1.21 (Giant removal), in such a way that poll_mtx is not dropped during call to polling handler. This fixes problem with idle polling. o Make registration and deregistration from polling in a functional way, insted of next tick/interrupt. o Obsolete kern.polling.enable. Polling is turned on/off with ifconfig. Detailed kern_poll.c changes: - Remove polling handler flags, introduced in 1.21. The are not needed now. - Forget and do not check if_flags, if_capenable and if_drv_flags. - Call all registered polling handlers unconditionally. - Do not drop poll_mtx, when entering polling handlers. - In ether_poll() NET_LOCK_GIANT prior to locking poll_mtx. - In netisr_poll() axe the block, where polling code asks drivers to unregister. - In netisr_poll() and ether_poll() do polling always, if any handlers are present. - In ether_poll_[de]register() remove a lot of error hiding code. Assert that arguments are correct, instead. - In ether_poll_[de]register() use standard return values in case of error or success. - Introduce poll_switch() that is a sysctl handler for kern.polling.enable. poll_switch() goes through interface list and enabled/disables polling. A message that kern.polling.enable is deprecated is printed. Detailed driver changes: - On attach driver announces IFCAP_POLLING in if_capabilities, but not in if_capenable. - On detach driver calls ether_poll_deregister() if polling is enabled. - In polling handler driver obtains its lock and checks IFF_DRV_RUNNING flag. If there is no, then unlocks and returns. - In ioctl handler driver checks for IFCAP_POLLING flag requested to be set or cleared. Driver first calls ether_poll_[de]register(), then obtains driver lock and [dis/en]ables interrupts. - In interrupt handler driver checks IFCAP_POLLING flag in if_capenable. If present, then returns.This is important to protect from spurious interrupts. Reviewed by: ru, sam, jhb
2005-10-01 18:56:19 +00:00
ether_poll_deregister(ifp);
#endif
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
/* These should only be active if attach succeeded. */
Use newly minted device_is_attached rather than device_is_alive to see if attach succeeded. device_is_alive just tells us that probe succeeded. Since we were using it to do things like detach net interfaces, this caused problems when there were errors in the attach routine. Symptoms of problem reported by: martin blapp
2003-04-21 18:34:04 +00:00
if (device_is_attached(dev)) {
- Use callout_*() to manage the callout and make it MPSAFE. - Fix locking in detach(), we only need to lock across vr_stop(). Tested by: Mike Tancsa mike at sentex dot net MFC after: 1 week
2005-10-31 21:37:27 +00:00
VR_LOCK(sc);
Reuse flag variable to represent driver internal states rather than using member variables in softc. While I'm here change media after setting IFF_DRV_RUNNING. This will remove unnecessary link state handling in vr_tick() if controller established a link immediately.
2011-11-28 18:32:35 +00:00
sc->vr_flags |= VR_F_DETACHED;
Revise attach/detach resource cleanup - Unconditionally call *_stop() if device is in the tree. This is to prevent callouts from happening after the device is gone. Checks for bus_child_present() should be added in the future to keep from touching potentially non-existent hardware in *_detach(). Found by iedowse@. - Always check for and free miibus children, even if the device is not in the tree since some failure cases could have gotten here. - Call ether_ifdetach() in the irq setup failure case - ti(4), xl(4): move ifmedia_init() calls to the beginning of attach so that ifmedia_removeall() can be unconditionally called on detach. There is no way to detect whether ifmedia has been initialized without using a separate variable (as tl(4) does). - Add comments to indicate assumptions of code path
2003-04-17 20:32:06 +00:00
vr_stop(sc);
- Use callout_*() to manage the callout and make it MPSAFE. - Fix locking in detach(), we only need to lock across vr_stop(). Tested by: Mike Tancsa mike at sentex dot net MFC after: 1 week
2005-10-31 21:37:27 +00:00
VR_UNLOCK(sc);
callout_drain(&sc->vr_stat_callout);
Convert the if_vr(4) driver model to the interrupt filter model and use a taskqueue. This gives a 16% performance improvement under high load on slow systems, especially when vr shares an interrupt with another device, which is common with the Alix x86 boards. Contrary to the other devices, I left the interrupt processing for loop in because there was no significant difference in performance and this should avoid enqueuing more taskqueues unnecessarily. We also decided to move the vr_start_locked() call inside the for loop because we found out that it helps performance since TCP ACKs now have a chance to go out quicker. Reviewed by: yongari (older version, same idea) Discussed with: yongari, jhb
2012-05-12 14:37:25 +00:00
taskqueue_drain(taskqueue_fast, &sc->vr_inttask);
Clean up locking and resource management for pci/if_* - Remove locking of the softc in the attach method, instead depending on bus_setup_intr being at the end of attach (delaying interrupt enable until after ether_ifattach is called) - Call *_detach directly in the error case of attach, depending on checking in detach to only free resources that were allocated. This puts all resource freeing in one place, avoiding thinkos that lead to memory leaks. - Add bus_child_present check to calls to *_stop in the detach method to be sure hw is present before touching its registers. - Remove bzero softc calls since device_t should do this for us. - dc: move interrupt allocation back where it was before. It was unnecessary to move it. This reverts part of 1.88 - rl: move irq allocation before ether_ifattach. Problems might have been caused by allocating the irq after enabling interrupts on the card. - rl: call rl_stop before ether_ifdetach - sf: call sf_stop before ether_ifdetach - sis: add missed free of sis_tag - sis: check errors from tag creation - sis: move dmamem_alloc and dmamap_load to happen at same time as tag creation - sk: remove duplicate initialization of sk_dev - ste: add missed bus_generic_detach - ti: call ti_stop before ether_ifdetach - ti: add missed error setting in ti_rdata alloc failure - vr: add missed error setting in I/O, memory mapping cases - xl: add missed error setting in I/O, memory mapping cases - xl: remove multi-level goto on attach failure - xl: move dmamem_alloc and dmamap_load to happen at same time as tag creation - Calls to free(9) are unconditional because it is valid to call free with a null pointer. Reviewed by: imp, mdodd
2003-03-31 17:29:43 +00:00
ether_ifdetach(ifp);
}
Revise attach/detach resource cleanup - Unconditionally call *_stop() if device is in the tree. This is to prevent callouts from happening after the device is gone. Checks for bus_child_present() should be added in the future to keep from touching potentially non-existent hardware in *_detach(). Found by iedowse@. - Always check for and free miibus children, even if the device is not in the tree since some failure cases could have gotten here. - Call ether_ifdetach() in the irq setup failure case - ti(4), xl(4): move ifmedia_init() calls to the beginning of attach so that ifmedia_removeall() can be unconditionally called on detach. There is no way to detect whether ifmedia has been initialized without using a separate variable (as tl(4) does). - Add comments to indicate assumptions of code path
2003-04-17 20:32:06 +00:00
if (sc->vr_miibus)
device_delete_child(dev, sc->vr_miibus);
bus_generic_detach(dev);
Convert the VIA Rhine driver to miibus.
1999-09-19 22:03:31 +00:00
Clean up locking and resource management for pci/if_* - Remove locking of the softc in the attach method, instead depending on bus_setup_intr being at the end of attach (delaying interrupt enable until after ether_ifattach is called) - Call *_detach directly in the error case of attach, depending on checking in detach to only free resources that were allocated. This puts all resource freeing in one place, avoiding thinkos that lead to memory leaks. - Add bus_child_present check to calls to *_stop in the detach method to be sure hw is present before touching its registers. - Remove bzero softc calls since device_t should do this for us. - dc: move interrupt allocation back where it was before. It was unnecessary to move it. This reverts part of 1.88 - rl: move irq allocation before ether_ifattach. Problems might have been caused by allocating the irq after enabling interrupts on the card. - rl: call rl_stop before ether_ifdetach - sf: call sf_stop before ether_ifdetach - sis: add missed free of sis_tag - sis: check errors from tag creation - sis: move dmamem_alloc and dmamap_load to happen at same time as tag creation - sk: remove duplicate initialization of sk_dev - ste: add missed bus_generic_detach - ti: call ti_stop before ether_ifdetach - ti: add missed error setting in ti_rdata alloc failure - vr: add missed error setting in I/O, memory mapping cases - xl: add missed error setting in I/O, memory mapping cases - xl: remove multi-level goto on attach failure - xl: move dmamem_alloc and dmamap_load to happen at same time as tag creation - Calls to free(9) are unconditional because it is valid to call free with a null pointer. Reviewed by: imp, mdodd
2003-03-31 17:29:43 +00:00
if (sc->vr_intrhand)
bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
if (sc->vr_irq)
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
if (sc->vr_res)
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
bus_release_resource(dev, sc->vr_res_type, sc->vr_res_id,
sc->vr_res);
Convert the VIA Rhine driver to newbus and set it up to be compiled as a module. Also modified the code to work on FreeBSD/alpha and added device vr0 to the alpha GENERIC config. While I was in the neighborhood, I noticed that I was still using #define NFPX 1 in all of the Makefiles that I'd copied from the fxp module. I don't really use #define Nfoo X so it didn't matter, but I decided to customize this correctly anyway.
1999-08-10 17:15:20 +00:00
In detach method, move if_free() after bus_teardown_intr().
2005-10-13 21:11:20 +00:00
if (ifp)
if_free(ifp);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
vr_dma_free(sc);
Convert the VIA Rhine driver to newbus and set it up to be compiled as a module. Also modified the code to work on FreeBSD/alpha and added device vr0 to the alpha GENERIC config. While I was in the neighborhood, I noticed that I was still using #define NFPX 1 in all of the Makefiles that I'd copied from the fxp module. I don't really use #define Nfoo X so it didn't matter, but I decided to customize this correctly anyway.
1999-08-10 17:15:20 +00:00
First round of converting network drivers from spls to mutexes. This takes care of all the 10/100 and gigE PCI drivers that I've done. Next will be the wireless drivers, then the USB ones. I may pick up some stragglers along the way. I'm sort of playing this by ear: if anyone spots any places where I've screwed up horribly, please let me know.
2000-10-13 17:54:19 +00:00
mtx_destroy(&sc->vr_mtx);
Convert the VIA Rhine driver to newbus and set it up to be compiled as a module. Also modified the code to work on FreeBSD/alpha and added device vr0 to the alpha GENERIC config. While I was in the neighborhood, I noticed that I was still using #define NFPX 1 in all of the Makefiles that I'd copied from the fxp module. I don't really use #define Nfoo X so it didn't matter, but I decided to customize this correctly anyway.
1999-08-10 17:15:20 +00:00
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
return (0);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
struct vr_dmamap_arg {
bus_addr_t vr_busaddr;
};
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
static void
vr_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
{
struct vr_dmamap_arg *ctx;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (error != 0)
return;
ctx = arg;
ctx->vr_busaddr = segs[0].ds_addr;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
style: put return types on a line by themselves.
2002-08-24 00:02:03 +00:00
static int
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
vr_dma_alloc(struct vr_softc *sc)
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
{
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
struct vr_dmamap_arg ctx;
struct vr_txdesc *txd;
struct vr_rxdesc *rxd;
bus_size_t tx_alignment;
int error, i;
/* Create parent DMA tag. */
error = bus_dma_tag_create(
bus_get_dma_tag(sc->vr_dev), /* parent */
1, 0, /* alignment, boundary */
BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
0, /* nsegments */
BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
0, /* flags */
NULL, NULL, /* lockfunc, lockarg */
&sc->vr_cdata.vr_parent_tag);
if (error != 0) {
device_printf(sc->vr_dev, "failed to create parent DMA tag\n");
goto fail;
}
/* Create tag for Tx ring. */
error = bus_dma_tag_create(
sc->vr_cdata.vr_parent_tag, /* parent */
VR_RING_ALIGN, 0, /* alignment, boundary */
BUS_SPACE_MAXADDR, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
VR_TX_RING_SIZE, /* maxsize */
1, /* nsegments */
VR_TX_RING_SIZE, /* maxsegsize */
0, /* flags */
NULL, NULL, /* lockfunc, lockarg */
&sc->vr_cdata.vr_tx_ring_tag);
if (error != 0) {
device_printf(sc->vr_dev, "failed to create Tx ring DMA tag\n");
goto fail;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
/* Create tag for Rx ring. */
error = bus_dma_tag_create(
sc->vr_cdata.vr_parent_tag, /* parent */
VR_RING_ALIGN, 0, /* alignment, boundary */
BUS_SPACE_MAXADDR, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
VR_RX_RING_SIZE, /* maxsize */
1, /* nsegments */
VR_RX_RING_SIZE, /* maxsegsize */
0, /* flags */
NULL, NULL, /* lockfunc, lockarg */
&sc->vr_cdata.vr_rx_ring_tag);
if (error != 0) {
device_printf(sc->vr_dev, "failed to create Rx ring DMA tag\n");
goto fail;
}
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if ((sc->vr_quirks & VR_Q_NEEDALIGN) != 0)
tx_alignment = sizeof(uint32_t);
else
tx_alignment = 1;
/* Create tag for Tx buffers. */
error = bus_dma_tag_create(
sc->vr_cdata.vr_parent_tag, /* parent */
tx_alignment, 0, /* alignment, boundary */
BUS_SPACE_MAXADDR, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
MCLBYTES * VR_MAXFRAGS, /* maxsize */
VR_MAXFRAGS, /* nsegments */
MCLBYTES, /* maxsegsize */
0, /* flags */
NULL, NULL, /* lockfunc, lockarg */
&sc->vr_cdata.vr_tx_tag);
if (error != 0) {
device_printf(sc->vr_dev, "failed to create Tx DMA tag\n");
goto fail;
}
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
/* Create tag for Rx buffers. */
error = bus_dma_tag_create(
sc->vr_cdata.vr_parent_tag, /* parent */
VR_RX_ALIGN, 0, /* alignment, boundary */
BUS_SPACE_MAXADDR, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
MCLBYTES, /* maxsize */
1, /* nsegments */
MCLBYTES, /* maxsegsize */
0, /* flags */
NULL, NULL, /* lockfunc, lockarg */
&sc->vr_cdata.vr_rx_tag);
if (error != 0) {
device_printf(sc->vr_dev, "failed to create Rx DMA tag\n");
goto fail;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
/* Allocate DMA'able memory and load the DMA map for Tx ring. */
error = bus_dmamem_alloc(sc->vr_cdata.vr_tx_ring_tag,
(void **)&sc->vr_rdata.vr_tx_ring, BUS_DMA_WAITOK |
BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->vr_cdata.vr_tx_ring_map);
if (error != 0) {
device_printf(sc->vr_dev,
"failed to allocate DMA'able memory for Tx ring\n");
goto fail;
}
Convert the VIA Rhine driver to newbus and set it up to be compiled as a module. Also modified the code to work on FreeBSD/alpha and added device vr0 to the alpha GENERIC config. While I was in the neighborhood, I noticed that I was still using #define NFPX 1 in all of the Makefiles that I'd copied from the fxp module. I don't really use #define Nfoo X so it didn't matter, but I decided to customize this correctly anyway.
1999-08-10 17:15:20 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
ctx.vr_busaddr = 0;
error = bus_dmamap_load(sc->vr_cdata.vr_tx_ring_tag,
sc->vr_cdata.vr_tx_ring_map, sc->vr_rdata.vr_tx_ring,
VR_TX_RING_SIZE, vr_dmamap_cb, &ctx, 0);
if (error != 0 || ctx.vr_busaddr == 0) {
device_printf(sc->vr_dev,
"failed to load DMA'able memory for Tx ring\n");
goto fail;
}
sc->vr_rdata.vr_tx_ring_paddr = ctx.vr_busaddr;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
/* Allocate DMA'able memory and load the DMA map for Rx ring. */
error = bus_dmamem_alloc(sc->vr_cdata.vr_rx_ring_tag,
(void **)&sc->vr_rdata.vr_rx_ring, BUS_DMA_WAITOK |
BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->vr_cdata.vr_rx_ring_map);
if (error != 0) {
device_printf(sc->vr_dev,
"failed to allocate DMA'able memory for Rx ring\n");
goto fail;
}
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
ctx.vr_busaddr = 0;
error = bus_dmamap_load(sc->vr_cdata.vr_rx_ring_tag,
sc->vr_cdata.vr_rx_ring_map, sc->vr_rdata.vr_rx_ring,
VR_RX_RING_SIZE, vr_dmamap_cb, &ctx, 0);
if (error != 0 || ctx.vr_busaddr == 0) {
device_printf(sc->vr_dev,
"failed to load DMA'able memory for Rx ring\n");
goto fail;
}
sc->vr_rdata.vr_rx_ring_paddr = ctx.vr_busaddr;
/* Create DMA maps for Tx buffers. */
for (i = 0; i < VR_TX_RING_CNT; i++) {
txd = &sc->vr_cdata.vr_txdesc[i];
txd->tx_m = NULL;
txd->tx_dmamap = NULL;
error = bus_dmamap_create(sc->vr_cdata.vr_tx_tag, 0,
&txd->tx_dmamap);
if (error != 0) {
device_printf(sc->vr_dev,
"failed to create Tx dmamap\n");
goto fail;
}
}
/* Create DMA maps for Rx buffers. */
if ((error = bus_dmamap_create(sc->vr_cdata.vr_rx_tag, 0,
&sc->vr_cdata.vr_rx_sparemap)) != 0) {
device_printf(sc->vr_dev,
"failed to create spare Rx dmamap\n");
goto fail;
}
for (i = 0; i < VR_RX_RING_CNT; i++) {
rxd = &sc->vr_cdata.vr_rxdesc[i];
rxd->rx_m = NULL;
rxd->rx_dmamap = NULL;
error = bus_dmamap_create(sc->vr_cdata.vr_rx_tag, 0,
&rxd->rx_dmamap);
if (error != 0) {
device_printf(sc->vr_dev,
"failed to create Rx dmamap\n");
goto fail;
}
}
fail:
return (error);
}
static void
vr_dma_free(struct vr_softc *sc)
{
struct vr_txdesc *txd;
struct vr_rxdesc *rxd;
int i;
/* Tx ring. */
if (sc->vr_cdata.vr_tx_ring_tag) {
Fix various NIC drivers to properly cleanup static DMA resources. In particular, don't check the value of the bus_dma map against NULL to determine if either bus_dmamem_alloc() or bus_dmamap_load() succeeded. Instead, assume that bus_dmamap_load() succeeeded (and thus that bus_dmamap_unload() should be called) if the bus address for a resource is non-zero, and assume that bus_dmamem_alloc() succeeded (and thus that bus_dmamem_free() should be called) if the virtual address for a resource is not NULL. In many cases these bugs could result in leaks when a driver was detached. Reviewed by: yongari MFC after: 2 weeks
2014-06-11 14:53:58 +00:00
if (sc->vr_rdata.vr_tx_ring_paddr)
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
bus_dmamap_unload(sc->vr_cdata.vr_tx_ring_tag,
sc->vr_cdata.vr_tx_ring_map);
Fix various NIC drivers to properly cleanup static DMA resources. In particular, don't check the value of the bus_dma map against NULL to determine if either bus_dmamem_alloc() or bus_dmamap_load() succeeded. Instead, assume that bus_dmamap_load() succeeeded (and thus that bus_dmamap_unload() should be called) if the bus address for a resource is non-zero, and assume that bus_dmamem_alloc() succeeded (and thus that bus_dmamem_free() should be called) if the virtual address for a resource is not NULL. In many cases these bugs could result in leaks when a driver was detached. Reviewed by: yongari MFC after: 2 weeks
2014-06-11 14:53:58 +00:00
if (sc->vr_rdata.vr_tx_ring)
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
bus_dmamem_free(sc->vr_cdata.vr_tx_ring_tag,
sc->vr_rdata.vr_tx_ring,
sc->vr_cdata.vr_tx_ring_map);
sc->vr_rdata.vr_tx_ring = NULL;
Fix various NIC drivers to properly cleanup static DMA resources. In particular, don't check the value of the bus_dma map against NULL to determine if either bus_dmamem_alloc() or bus_dmamap_load() succeeded. Instead, assume that bus_dmamap_load() succeeeded (and thus that bus_dmamap_unload() should be called) if the bus address for a resource is non-zero, and assume that bus_dmamem_alloc() succeeded (and thus that bus_dmamem_free() should be called) if the virtual address for a resource is not NULL. In many cases these bugs could result in leaks when a driver was detached. Reviewed by: yongari MFC after: 2 weeks
2014-06-11 14:53:58 +00:00
sc->vr_rdata.vr_tx_ring_paddr = 0;
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
bus_dma_tag_destroy(sc->vr_cdata.vr_tx_ring_tag);
sc->vr_cdata.vr_tx_ring_tag = NULL;
}
/* Rx ring. */
if (sc->vr_cdata.vr_rx_ring_tag) {
Fix various NIC drivers to properly cleanup static DMA resources. In particular, don't check the value of the bus_dma map against NULL to determine if either bus_dmamem_alloc() or bus_dmamap_load() succeeded. Instead, assume that bus_dmamap_load() succeeeded (and thus that bus_dmamap_unload() should be called) if the bus address for a resource is non-zero, and assume that bus_dmamem_alloc() succeeded (and thus that bus_dmamem_free() should be called) if the virtual address for a resource is not NULL. In many cases these bugs could result in leaks when a driver was detached. Reviewed by: yongari MFC after: 2 weeks
2014-06-11 14:53:58 +00:00
if (sc->vr_rdata.vr_rx_ring_paddr)
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
bus_dmamap_unload(sc->vr_cdata.vr_rx_ring_tag,
sc->vr_cdata.vr_rx_ring_map);
Fix various NIC drivers to properly cleanup static DMA resources. In particular, don't check the value of the bus_dma map against NULL to determine if either bus_dmamem_alloc() or bus_dmamap_load() succeeded. Instead, assume that bus_dmamap_load() succeeeded (and thus that bus_dmamap_unload() should be called) if the bus address for a resource is non-zero, and assume that bus_dmamem_alloc() succeeded (and thus that bus_dmamem_free() should be called) if the virtual address for a resource is not NULL. In many cases these bugs could result in leaks when a driver was detached. Reviewed by: yongari MFC after: 2 weeks
2014-06-11 14:53:58 +00:00
if (sc->vr_rdata.vr_rx_ring)
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
bus_dmamem_free(sc->vr_cdata.vr_rx_ring_tag,
sc->vr_rdata.vr_rx_ring,
sc->vr_cdata.vr_rx_ring_map);
sc->vr_rdata.vr_rx_ring = NULL;
Fix various NIC drivers to properly cleanup static DMA resources. In particular, don't check the value of the bus_dma map against NULL to determine if either bus_dmamem_alloc() or bus_dmamap_load() succeeded. Instead, assume that bus_dmamap_load() succeeeded (and thus that bus_dmamap_unload() should be called) if the bus address for a resource is non-zero, and assume that bus_dmamem_alloc() succeeded (and thus that bus_dmamem_free() should be called) if the virtual address for a resource is not NULL. In many cases these bugs could result in leaks when a driver was detached. Reviewed by: yongari MFC after: 2 weeks
2014-06-11 14:53:58 +00:00
sc->vr_rdata.vr_rx_ring_paddr = 0;
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
bus_dma_tag_destroy(sc->vr_cdata.vr_rx_ring_tag);
sc->vr_cdata.vr_rx_ring_tag = NULL;
}
/* Tx buffers. */
if (sc->vr_cdata.vr_tx_tag) {
for (i = 0; i < VR_TX_RING_CNT; i++) {
txd = &sc->vr_cdata.vr_txdesc[i];
if (txd->tx_dmamap) {
bus_dmamap_destroy(sc->vr_cdata.vr_tx_tag,
txd->tx_dmamap);
txd->tx_dmamap = NULL;
}
}
bus_dma_tag_destroy(sc->vr_cdata.vr_tx_tag);
sc->vr_cdata.vr_tx_tag = NULL;
}
/* Rx buffers. */
if (sc->vr_cdata.vr_rx_tag) {
for (i = 0; i < VR_RX_RING_CNT; i++) {
rxd = &sc->vr_cdata.vr_rxdesc[i];
if (rxd->rx_dmamap) {
bus_dmamap_destroy(sc->vr_cdata.vr_rx_tag,
rxd->rx_dmamap);
rxd->rx_dmamap = NULL;
}
}
if (sc->vr_cdata.vr_rx_sparemap) {
bus_dmamap_destroy(sc->vr_cdata.vr_rx_tag,
sc->vr_cdata.vr_rx_sparemap);
sc->vr_cdata.vr_rx_sparemap = 0;
}
bus_dma_tag_destroy(sc->vr_cdata.vr_rx_tag);
sc->vr_cdata.vr_rx_tag = NULL;
}
if (sc->vr_cdata.vr_parent_tag) {
bus_dma_tag_destroy(sc->vr_cdata.vr_parent_tag);
sc->vr_cdata.vr_parent_tag = NULL;
}
}
/*
* Initialize the transmit descriptors.
*/
static int
vr_tx_ring_init(struct vr_softc *sc)
{
struct vr_ring_data *rd;
struct vr_txdesc *txd;
bus_addr_t addr;
int i;
sc->vr_cdata.vr_tx_prod = 0;
sc->vr_cdata.vr_tx_cons = 0;
sc->vr_cdata.vr_tx_cnt = 0;
sc->vr_cdata.vr_tx_pkts = 0;
rd = &sc->vr_rdata;
bzero(rd->vr_tx_ring, VR_TX_RING_SIZE);
for (i = 0; i < VR_TX_RING_CNT; i++) {
if (i == VR_TX_RING_CNT - 1)
addr = VR_TX_RING_ADDR(sc, 0);
else
addr = VR_TX_RING_ADDR(sc, i + 1);
rd->vr_tx_ring[i].vr_nextphys = htole32(VR_ADDR_LO(addr));
txd = &sc->vr_cdata.vr_txdesc[i];
txd->tx_m = NULL;
}
bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag,
sc->vr_cdata.vr_tx_ring_map,
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
return (0);
}
/*
* Initialize the RX descriptors and allocate mbufs for them. Note that
* we arrange the descriptors in a closed ring, so that the last descriptor
* points back to the first.
*/
static int
vr_rx_ring_init(struct vr_softc *sc)
{
struct vr_ring_data *rd;
struct vr_rxdesc *rxd;
bus_addr_t addr;
int i;
sc->vr_cdata.vr_rx_cons = 0;
rd = &sc->vr_rdata;
bzero(rd->vr_rx_ring, VR_RX_RING_SIZE);
for (i = 0; i < VR_RX_RING_CNT; i++) {
rxd = &sc->vr_cdata.vr_rxdesc[i];
rxd->rx_m = NULL;
rxd->desc = &rd->vr_rx_ring[i];
if (i == VR_RX_RING_CNT - 1)
addr = VR_RX_RING_ADDR(sc, 0);
else
addr = VR_RX_RING_ADDR(sc, i + 1);
rd->vr_rx_ring[i].vr_nextphys = htole32(VR_ADDR_LO(addr));
if (vr_newbuf(sc, i) != 0)
return (ENOBUFS);
}
bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag,
sc->vr_cdata.vr_rx_ring_map,
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
return (0);
}
static __inline void
vr_discard_rxbuf(struct vr_rxdesc *rxd)
{
struct vr_desc *desc;
desc = rxd->desc;
desc->vr_ctl = htole32(VR_RXCTL | (MCLBYTES - sizeof(uint64_t)));
desc->vr_status = htole32(VR_RXSTAT_OWN);
}
/*
* Initialize an RX descriptor and attach an MBUF cluster.
* Note: the length fields are only 11 bits wide, which means the
* largest size we can specify is 2047. This is important because
* MCLBYTES is 2048, so we have to subtract one otherwise we'll
* overflow the field and make a mess.
*/
static int
vr_newbuf(struct vr_softc *sc, int idx)
{
struct vr_desc *desc;
struct vr_rxdesc *rxd;
struct mbuf *m;
bus_dma_segment_t segs[1];
bus_dmamap_t map;
int nsegs;
Mechanically substitute flags from historic mbuf allocator with malloc(9) flags in sys/dev.
2012-12-04 09:32:43 +00:00
m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (m == NULL)
return (ENOBUFS);
m->m_len = m->m_pkthdr.len = MCLBYTES;
m_adj(m, sizeof(uint64_t));
if (bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_rx_tag,
sc->vr_cdata.vr_rx_sparemap, m, segs, &nsegs, 0) != 0) {
m_freem(m);
return (ENOBUFS);
}
KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
rxd = &sc->vr_cdata.vr_rxdesc[idx];
if (rxd->rx_m != NULL) {
bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap,
BUS_DMASYNC_POSTREAD);
bus_dmamap_unload(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap);
}
map = rxd->rx_dmamap;
rxd->rx_dmamap = sc->vr_cdata.vr_rx_sparemap;
sc->vr_cdata.vr_rx_sparemap = map;
bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap,
BUS_DMASYNC_PREREAD);
rxd->rx_m = m;
desc = rxd->desc;
desc->vr_data = htole32(VR_ADDR_LO(segs[0].ds_addr));
desc->vr_ctl = htole32(VR_RXCTL | segs[0].ds_len);
desc->vr_status = htole32(VR_RXSTAT_OWN);
return (0);
}
#ifndef __NO_STRICT_ALIGNMENT
static __inline void
vr_fixup_rx(struct mbuf *m)
{
uint16_t *src, *dst;
int i;
src = mtod(m, uint16_t *);
dst = src - 1;
for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
*dst++ = *src++;
m->m_data -= ETHER_ALIGN;
}
#endif
/*
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
* A frame has been uploaded: pass the resulting mbuf chain up to
* the higher level protocols.
*/
When user_frac in the polling subsystem is low it is going to busy the CPU for too long period than necessary. Additively, interfaces are kept polled (in the tick) even if no more packets are available. In order to avoid such situations a new generic mechanism can be implemented in proactive way, keeping track of the time spent on any packet and fragmenting the time for any tick, stopping the processing as soon as possible. In order to implement such mechanism, the polling handler needs to change, returning the number of packets processed. While the intended logic is not part of this patch, the polling KPI is broken by this commit, adding an int return value and the new flag IFCAP_POLLING_NOCOUNT (which will signal that the return value is meaningless for the installed handler and checking should be skipped). Bump __FreeBSD_version in order to signal such situation. Reviewed by: emaste Sponsored by: Sandvine Incorporated
2009-05-30 15:14:44 +00:00
static int
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
vr_rxeof(struct vr_softc *sc)
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
{
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
struct vr_rxdesc *rxd;
struct mbuf *m;
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
struct ifnet *ifp;
Remove further cobwebs: Two layers of pointless substructures.
2007-04-22 15:48:29 +00:00
struct vr_desc *cur_rx;
When user_frac in the polling subsystem is low it is going to busy the CPU for too long period than necessary. Additively, interfaces are kept polled (in the tick) even if no more packets are available. In order to avoid such situations a new generic mechanism can be implemented in proactive way, keeping track of the time spent on any packet and fragmenting the time for any tick, stopping the processing as soon as possible. In order to implement such mechanism, the polling handler needs to change, returning the number of packets processed. While the intended logic is not part of this patch, the polling KPI is broken by this commit, adding an int return value and the new flag IFCAP_POLLING_NOCOUNT (which will signal that the return value is meaningless for the installed handler and checking should be skipped). Bump __FreeBSD_version in order to signal such situation. Reviewed by: emaste Sponsored by: Sandvine Incorporated
2009-05-30 15:14:44 +00:00
int cons, prog, total_len, rx_npkts;
Add support for hw-assisted checksums on 6105M. Sponsored by: Soekris Engineering
2007-04-17 22:59:54 +00:00
uint32_t rxstat, rxctl;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Drop the driver lock around calls to if_input to avoid a LOR when the packets are immediately returned for sending (e.g. when bridging or packet forwarding). There are more efficient ways to do this but for now use the least intrusive approach. Reviewed by: imp, rwatson
2003-11-14 19:00:32 +00:00
VR_LOCK_ASSERT(sc);
Stop embedding struct ifnet at the top of driver softcs. Instead the struct ifnet or the layer 2 common structure it was embedded in have been replaced with a struct ifnet pointer to be filled by a call to the new function, if_alloc(). The layer 2 common structure is also allocated via if_alloc() based on the interface type. It is hung off the new struct ifnet member, if_l2com. This change removes the size of these structures from the kernel ABI and will allow us to better manage them as interfaces come and go. Other changes of note: - Struct arpcom is no longer referenced in normal interface code. Instead the Ethernet address is accessed via the IFP2ENADDR() macro. To enforce this ac_enaddr has been renamed to _ac_enaddr. - The second argument to ether_ifattach is now always the mac address from driver private storage rather than sometimes being ac_enaddr. Reviewed by: sobomax, sam
2005-06-10 16:49:24 +00:00
ifp = sc->vr_ifp;
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
cons = sc->vr_cdata.vr_rx_cons;
When user_frac in the polling subsystem is low it is going to busy the CPU for too long period than necessary. Additively, interfaces are kept polled (in the tick) even if no more packets are available. In order to avoid such situations a new generic mechanism can be implemented in proactive way, keeping track of the time spent on any packet and fragmenting the time for any tick, stopping the processing as soon as possible. In order to implement such mechanism, the polling handler needs to change, returning the number of packets processed. While the intended logic is not part of this patch, the polling KPI is broken by this commit, adding an int return value and the new flag IFCAP_POLLING_NOCOUNT (which will signal that the return value is meaningless for the installed handler and checking should be skipped). Bump __FreeBSD_version in order to signal such situation. Reviewed by: emaste Sponsored by: Sandvine Incorporated
2009-05-30 15:14:44 +00:00
rx_npkts = 0;
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag,
sc->vr_cdata.vr_rx_ring_map,
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
for (prog = 0; prog < VR_RX_RING_CNT; VR_INC(cons, VR_RX_RING_CNT)) {
- Rewritten TX to use only two pointers to track producer/consumer. - Added polling(4) support! - Bugfix: don't forget to set IFF_OACTIVE when TX list is full. - Minor: tidy up vr_encap().
2004-04-05 17:39:57 +00:00
#ifdef DEVICE_POLLING
Big polling(4) cleanup. o Axe poll in trap. o Axe IFF_POLLING flag from if_flags. o Rework revision 1.21 (Giant removal), in such a way that poll_mtx is not dropped during call to polling handler. This fixes problem with idle polling. o Make registration and deregistration from polling in a functional way, insted of next tick/interrupt. o Obsolete kern.polling.enable. Polling is turned on/off with ifconfig. Detailed kern_poll.c changes: - Remove polling handler flags, introduced in 1.21. The are not needed now. - Forget and do not check if_flags, if_capenable and if_drv_flags. - Call all registered polling handlers unconditionally. - Do not drop poll_mtx, when entering polling handlers. - In ether_poll() NET_LOCK_GIANT prior to locking poll_mtx. - In netisr_poll() axe the block, where polling code asks drivers to unregister. - In netisr_poll() and ether_poll() do polling always, if any handlers are present. - In ether_poll_[de]register() remove a lot of error hiding code. Assert that arguments are correct, instead. - In ether_poll_[de]register() use standard return values in case of error or success. - Introduce poll_switch() that is a sysctl handler for kern.polling.enable. poll_switch() goes through interface list and enabled/disables polling. A message that kern.polling.enable is deprecated is printed. Detailed driver changes: - On attach driver announces IFCAP_POLLING in if_capabilities, but not in if_capenable. - On detach driver calls ether_poll_deregister() if polling is enabled. - In polling handler driver obtains its lock and checks IFF_DRV_RUNNING flag. If there is no, then unlocks and returns. - In ioctl handler driver checks for IFCAP_POLLING flag requested to be set or cleared. Driver first calls ether_poll_[de]register(), then obtains driver lock and [dis/en]ables interrupts. - In interrupt handler driver checks IFCAP_POLLING flag in if_capenable. If present, then returns.This is important to protect from spurious interrupts. Reviewed by: ru, sam, jhb
2005-10-01 18:56:19 +00:00
if (ifp->if_capenable & IFCAP_POLLING) {
- Rewritten TX to use only two pointers to track producer/consumer. - Added polling(4) support! - Bugfix: don't forget to set IFF_OACTIVE when TX list is full. - Minor: tidy up vr_encap().
2004-04-05 17:39:57 +00:00
if (sc->rxcycles <= 0)
break;
sc->rxcycles--;
}
Big polling(4) cleanup. o Axe poll in trap. o Axe IFF_POLLING flag from if_flags. o Rework revision 1.21 (Giant removal), in such a way that poll_mtx is not dropped during call to polling handler. This fixes problem with idle polling. o Make registration and deregistration from polling in a functional way, insted of next tick/interrupt. o Obsolete kern.polling.enable. Polling is turned on/off with ifconfig. Detailed kern_poll.c changes: - Remove polling handler flags, introduced in 1.21. The are not needed now. - Forget and do not check if_flags, if_capenable and if_drv_flags. - Call all registered polling handlers unconditionally. - Do not drop poll_mtx, when entering polling handlers. - In ether_poll() NET_LOCK_GIANT prior to locking poll_mtx. - In netisr_poll() axe the block, where polling code asks drivers to unregister. - In netisr_poll() and ether_poll() do polling always, if any handlers are present. - In ether_poll_[de]register() remove a lot of error hiding code. Assert that arguments are correct, instead. - In ether_poll_[de]register() use standard return values in case of error or success. - Introduce poll_switch() that is a sysctl handler for kern.polling.enable. poll_switch() goes through interface list and enabled/disables polling. A message that kern.polling.enable is deprecated is printed. Detailed driver changes: - On attach driver announces IFCAP_POLLING in if_capabilities, but not in if_capenable. - On detach driver calls ether_poll_deregister() if polling is enabled. - In polling handler driver obtains its lock and checks IFF_DRV_RUNNING flag. If there is no, then unlocks and returns. - In ioctl handler driver checks for IFCAP_POLLING flag requested to be set or cleared. Driver first calls ether_poll_[de]register(), then obtains driver lock and [dis/en]ables interrupts. - In interrupt handler driver checks IFCAP_POLLING flag in if_capenable. If present, then returns.This is important to protect from spurious interrupts. Reviewed by: ru, sam, jhb
2005-10-01 18:56:19 +00:00
#endif
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
cur_rx = &sc->vr_rdata.vr_rx_ring[cons];
rxstat = le32toh(cur_rx->vr_status);
rxctl = le32toh(cur_rx->vr_ctl);
if ((rxstat & VR_RXSTAT_OWN) == VR_RXSTAT_OWN)
break;
prog++;
rxd = &sc->vr_cdata.vr_rxdesc[cons];
m = rxd->rx_m;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
/*
* If an error occurs, update stats, clear the
* status word and leave the mbuf cluster in place:
* it should simply get re-used next time this descriptor
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
* comes up in the ring.
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
* We don't support SG in Rx path yet, so discard
* partial frame.
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
*/
Fix VR_RXSTAT_RX_OK bit definition which lasted for more than 9 years. All datasheet I have indicates the bit 15 is the VR_RXSTAT_RX_OK. The bit 14 is reserved for all Rhine family except VT6105M. VT6105M uses that bit to indicate a VLAN frame with matching CAM VLAN id. Use the VR_RXSTAT_RX_OK instead of VR_RXSTAT_RXERR when vr(4) checks the validity of received frame. This should fix occasional dropping frames on VT6105M. Tested by: Goran Lowkrantz ( goran.lowkrantz at ismobile dot com ) MFC after: 1 week
2008-07-16 08:02:23 +00:00
if ((rxstat & VR_RXSTAT_RX_OK) == 0 ||
(rxstat & (VR_RXSTAT_FIRSTFRAG | VR_RXSTAT_LASTFRAG)) !=
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
(VR_RXSTAT_FIRSTFRAG | VR_RXSTAT_LASTFRAG)) {
Mechanically convert to if_inc_counter().
2014-09-18 20:17:27 +00:00
if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc->vr_stat.rx_errors++;
Fixes from Thomas Nystrom to fix hanging problems experienced by vr cards under load. This patch has been tested by Thomas and other for more than a month now, and all (known) hangs seem to be solved. Thomas's explanation of the patch: * Fix the problem with the printing of the RX-error. * Code from if_fet do better deal with the RX-recovery including a timeout of the RX-turnoff. * The call to vr_rxeof before vr_rxeoc have been moved to a point where the RX-part of the chip is turned off. Otherwise there is a window where new data could have been written to the buffer chain before the RX-part is turned off. If this happens the chip will see a busy rx-buffer. I have no evidence that this have occured but god knows what the chip will do in this case! * I have added a timeout of the TX-turnoff. I have checked and in my 900 MHz system the flags for turnoff (both RX & TX) is seen at the first check in the loop. * I could see that I got the VR_ISR_DROPPED interrupt sometimes and started to thinking about this. I then realized that no recovery is needed for this case and therefore I only count it as an rxerror (which was not done before). * Finally I have changed the FIFO RX threshhold to 128 bytes. When I did this the VR_ISR_DROPPED interrupt went away. Theory: The chip will receive a complete frame before it tries to write it out to memory then the RX threshold is set to store'n'forward. IF the frame is large AND the next rx frame also is large AND the bus is busy transfering a TX frame to the TX fifo THEN the second received frame wont fit in the FIFO and is then dropped. By having the RX threshold set to 128 the RX fifo is emptied faster. MFC after: 5 days
2003-01-31 07:37:06 +00:00
if (rxstat & VR_RXSTAT_CRCERR)
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc->vr_stat.rx_crc_errors++;
Fixes from Thomas Nystrom to fix hanging problems experienced by vr cards under load. This patch has been tested by Thomas and other for more than a month now, and all (known) hangs seem to be solved. Thomas's explanation of the patch: * Fix the problem with the printing of the RX-error. * Code from if_fet do better deal with the RX-recovery including a timeout of the RX-turnoff. * The call to vr_rxeof before vr_rxeoc have been moved to a point where the RX-part of the chip is turned off. Otherwise there is a window where new data could have been written to the buffer chain before the RX-part is turned off. If this happens the chip will see a busy rx-buffer. I have no evidence that this have occured but god knows what the chip will do in this case! * I have added a timeout of the TX-turnoff. I have checked and in my 900 MHz system the flags for turnoff (both RX & TX) is seen at the first check in the loop. * I could see that I got the VR_ISR_DROPPED interrupt sometimes and started to thinking about this. I then realized that no recovery is needed for this case and therefore I only count it as an rxerror (which was not done before). * Finally I have changed the FIFO RX threshhold to 128 bytes. When I did this the VR_ISR_DROPPED interrupt went away. Theory: The chip will receive a complete frame before it tries to write it out to memory then the RX threshold is set to store'n'forward. IF the frame is large AND the next rx frame also is large AND the bus is busy transfering a TX frame to the TX fifo THEN the second received frame wont fit in the FIFO and is then dropped. By having the RX threshold set to 128 the RX fifo is emptied faster. MFC after: 5 days
2003-01-31 07:37:06 +00:00
if (rxstat & VR_RXSTAT_FRAMEALIGNERR)
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc->vr_stat.rx_alignment++;
Fixes from Thomas Nystrom to fix hanging problems experienced by vr cards under load. This patch has been tested by Thomas and other for more than a month now, and all (known) hangs seem to be solved. Thomas's explanation of the patch: * Fix the problem with the printing of the RX-error. * Code from if_fet do better deal with the RX-recovery including a timeout of the RX-turnoff. * The call to vr_rxeof before vr_rxeoc have been moved to a point where the RX-part of the chip is turned off. Otherwise there is a window where new data could have been written to the buffer chain before the RX-part is turned off. If this happens the chip will see a busy rx-buffer. I have no evidence that this have occured but god knows what the chip will do in this case! * I have added a timeout of the TX-turnoff. I have checked and in my 900 MHz system the flags for turnoff (both RX & TX) is seen at the first check in the loop. * I could see that I got the VR_ISR_DROPPED interrupt sometimes and started to thinking about this. I then realized that no recovery is needed for this case and therefore I only count it as an rxerror (which was not done before). * Finally I have changed the FIFO RX threshhold to 128 bytes. When I did this the VR_ISR_DROPPED interrupt went away. Theory: The chip will receive a complete frame before it tries to write it out to memory then the RX threshold is set to store'n'forward. IF the frame is large AND the next rx frame also is large AND the bus is busy transfering a TX frame to the TX fifo THEN the second received frame wont fit in the FIFO and is then dropped. By having the RX threshold set to 128 the RX fifo is emptied faster. MFC after: 5 days
2003-01-31 07:37:06 +00:00
if (rxstat & VR_RXSTAT_FIFOOFLOW)
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc->vr_stat.rx_fifo_overflows++;
Fixes from Thomas Nystrom to fix hanging problems experienced by vr cards under load. This patch has been tested by Thomas and other for more than a month now, and all (known) hangs seem to be solved. Thomas's explanation of the patch: * Fix the problem with the printing of the RX-error. * Code from if_fet do better deal with the RX-recovery including a timeout of the RX-turnoff. * The call to vr_rxeof before vr_rxeoc have been moved to a point where the RX-part of the chip is turned off. Otherwise there is a window where new data could have been written to the buffer chain before the RX-part is turned off. If this happens the chip will see a busy rx-buffer. I have no evidence that this have occured but god knows what the chip will do in this case! * I have added a timeout of the TX-turnoff. I have checked and in my 900 MHz system the flags for turnoff (both RX & TX) is seen at the first check in the loop. * I could see that I got the VR_ISR_DROPPED interrupt sometimes and started to thinking about this. I then realized that no recovery is needed for this case and therefore I only count it as an rxerror (which was not done before). * Finally I have changed the FIFO RX threshhold to 128 bytes. When I did this the VR_ISR_DROPPED interrupt went away. Theory: The chip will receive a complete frame before it tries to write it out to memory then the RX threshold is set to store'n'forward. IF the frame is large AND the next rx frame also is large AND the bus is busy transfering a TX frame to the TX fifo THEN the second received frame wont fit in the FIFO and is then dropped. By having the RX threshold set to 128 the RX fifo is emptied faster. MFC after: 5 days
2003-01-31 07:37:06 +00:00
if (rxstat & VR_RXSTAT_GIANT)
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc->vr_stat.rx_giants++;
Fixes from Thomas Nystrom to fix hanging problems experienced by vr cards under load. This patch has been tested by Thomas and other for more than a month now, and all (known) hangs seem to be solved. Thomas's explanation of the patch: * Fix the problem with the printing of the RX-error. * Code from if_fet do better deal with the RX-recovery including a timeout of the RX-turnoff. * The call to vr_rxeof before vr_rxeoc have been moved to a point where the RX-part of the chip is turned off. Otherwise there is a window where new data could have been written to the buffer chain before the RX-part is turned off. If this happens the chip will see a busy rx-buffer. I have no evidence that this have occured but god knows what the chip will do in this case! * I have added a timeout of the TX-turnoff. I have checked and in my 900 MHz system the flags for turnoff (both RX & TX) is seen at the first check in the loop. * I could see that I got the VR_ISR_DROPPED interrupt sometimes and started to thinking about this. I then realized that no recovery is needed for this case and therefore I only count it as an rxerror (which was not done before). * Finally I have changed the FIFO RX threshhold to 128 bytes. When I did this the VR_ISR_DROPPED interrupt went away. Theory: The chip will receive a complete frame before it tries to write it out to memory then the RX threshold is set to store'n'forward. IF the frame is large AND the next rx frame also is large AND the bus is busy transfering a TX frame to the TX fifo THEN the second received frame wont fit in the FIFO and is then dropped. By having the RX threshold set to 128 the RX fifo is emptied faster. MFC after: 5 days
2003-01-31 07:37:06 +00:00
if (rxstat & VR_RXSTAT_RUNT)
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc->vr_stat.rx_runts++;
Fixes from Thomas Nystrom to fix hanging problems experienced by vr cards under load. This patch has been tested by Thomas and other for more than a month now, and all (known) hangs seem to be solved. Thomas's explanation of the patch: * Fix the problem with the printing of the RX-error. * Code from if_fet do better deal with the RX-recovery including a timeout of the RX-turnoff. * The call to vr_rxeof before vr_rxeoc have been moved to a point where the RX-part of the chip is turned off. Otherwise there is a window where new data could have been written to the buffer chain before the RX-part is turned off. If this happens the chip will see a busy rx-buffer. I have no evidence that this have occured but god knows what the chip will do in this case! * I have added a timeout of the TX-turnoff. I have checked and in my 900 MHz system the flags for turnoff (both RX & TX) is seen at the first check in the loop. * I could see that I got the VR_ISR_DROPPED interrupt sometimes and started to thinking about this. I then realized that no recovery is needed for this case and therefore I only count it as an rxerror (which was not done before). * Finally I have changed the FIFO RX threshhold to 128 bytes. When I did this the VR_ISR_DROPPED interrupt went away. Theory: The chip will receive a complete frame before it tries to write it out to memory then the RX threshold is set to store'n'forward. IF the frame is large AND the next rx frame also is large AND the bus is busy transfering a TX frame to the TX fifo THEN the second received frame wont fit in the FIFO and is then dropped. By having the RX threshold set to 128 the RX fifo is emptied faster. MFC after: 5 days
2003-01-31 07:37:06 +00:00
if (rxstat & VR_RXSTAT_BUFFERR)
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc->vr_stat.rx_no_buffers++;
#ifdef VR_SHOW_ERRORS
device_printf(sc->vr_dev, "%s: receive error = 0x%b\n",
__func__, rxstat & 0xff, VR_RXSTAT_ERR_BITS);
#endif
vr_discard_rxbuf(rxd);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
continue;
}
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (vr_newbuf(sc, cons) != 0) {
Mechanically convert to if_inc_counter().
2014-09-18 20:17:27 +00:00
if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc->vr_stat.rx_errors++;
sc->vr_stat.rx_no_mbufs++;
vr_discard_rxbuf(rxd);
continue;
Add support for hw-assisted checksums on 6105M. Sponsored by: Soekris Engineering
2007-04-17 22:59:54 +00:00
}
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
The VIA Rhine appears to be yet another chip that always includes the ethernet CRC in received frames and has no option to turn this behavior off. Trim the CRC off manually in vr_rxeof().
1998-12-24 18:03:17 +00:00
/*
* XXX The VIA Rhine chip includes the CRC with every
* received frame, and there's no way to turn this
* behavior off (at least, I can't find anything in
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
* the manual that explains how to do it) so we have
The VIA Rhine appears to be yet another chip that always includes the ethernet CRC in received frames and has no option to turn this behavior off. Trim the CRC off manually in vr_rxeof().
1998-12-24 18:03:17 +00:00
* to trim off the CRC manually.
*/
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
total_len = VR_RXBYTES(rxstat);
The VIA Rhine appears to be yet another chip that always includes the ethernet CRC in received frames and has no option to turn this behavior off. Trim the CRC off manually in vr_rxeof().
1998-12-24 18:03:17 +00:00
total_len -= ETHER_CRC_LEN;
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
m->m_pkthdr.len = m->m_len = total_len;
#ifndef __NO_STRICT_ALIGNMENT
/*
* RX buffers must be 32-bit aligned.
* Ignore the alignment problems on the non-strict alignment
* platform. The performance hit incurred due to unaligned
* accesses is much smaller than the hit produced by forcing
* buffer copies all the time.
*/
vr_fixup_rx(m);
#endif
m->m_pkthdr.rcvif = ifp;
Mechanically convert to if_inc_counter().
2014-09-18 20:17:27 +00:00
if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc->vr_stat.rx_ok++;
if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
(rxstat & VR_RXSTAT_FRAG) == 0 &&
(rxctl & VR_RXCTL_IP) != 0) {
/* Checksum is valid for non-fragmented IP packets. */
m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
if ((rxctl & VR_RXCTL_IPOK) == VR_RXCTL_IPOK) {
m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
if (rxctl & (VR_RXCTL_TCP | VR_RXCTL_UDP)) {
m->m_pkthdr.csum_flags |=
CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
if ((rxctl & VR_RXCTL_TCPUDPOK) != 0)
m->m_pkthdr.csum_data = 0xffff;
}
}
}
Drop the driver lock around calls to if_input to avoid a LOR when the packets are immediately returned for sending (e.g. when bridging or packet forwarding). There are more efficient ways to do this but for now use the least intrusive approach. Reviewed by: imp, rwatson
2003-11-14 19:00:32 +00:00
VR_UNLOCK(sc);
o track either_ifattach/ether_ifdetach API changes o use if_input for input packet processing o don't strip the Ethernet header for input packets o use BPF_* macros bpf tapping o call ether_ioctl to handle default ioctl case o track vlan changes Reviewed by: many Approved by: re
2002-11-14 23:49:09 +00:00
(*ifp->if_input)(ifp, m);
Drop the driver lock around calls to if_input to avoid a LOR when the packets are immediately returned for sending (e.g. when bridging or packet forwarding). There are more efficient ways to do this but for now use the least intrusive approach. Reviewed by: imp, rwatson
2003-11-14 19:00:32 +00:00
VR_LOCK(sc);
When user_frac in the polling subsystem is low it is going to busy the CPU for too long period than necessary. Additively, interfaces are kept polled (in the tick) even if no more packets are available. In order to avoid such situations a new generic mechanism can be implemented in proactive way, keeping track of the time spent on any packet and fragmenting the time for any tick, stopping the processing as soon as possible. In order to implement such mechanism, the polling handler needs to change, returning the number of packets processed. While the intended logic is not part of this patch, the polling KPI is broken by this commit, adding an int return value and the new flag IFCAP_POLLING_NOCOUNT (which will signal that the return value is meaningless for the installed handler and checking should be skipped). Bump __FreeBSD_version in order to signal such situation. Reviewed by: emaste Sponsored by: Sandvine Incorporated
2009-05-30 15:14:44 +00:00
rx_npkts++;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
SMPng locking cleanup for vr(4). - Remove recursive locking situations. Remove the MTX_RECURSE bit. - Take the lock for any routine which is not called from within if_vr.c itself; this includes entry points called by newbus, ifnet, callout, ifmedia, and polling subsystems. - Remove spl references from the code added to miibus callbacks in rev 1.60. - Add the INTR_MPSAFE bit. - Tidy up some assignments; locks are not needed for taking the address of something at a known offset, for example. - Tested on the machine this was committed from. Tested on: UP only, !debug.mpsafenet && debug.mpsafenet Reviewed by: rwatson
2004-07-03 02:59:02 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (prog > 0) {
Announce flow control capability to PHY drivers and enable flow control for all vr(4) controllers that support it. It's known that old vr(4) controllers(Rhine II) does not support TX pause but Rhine III supports both TX and RX pause. Make TX pause really work on Rhine III by letting controller know available RX buffers. While here, adjust XON/XOFF parameters to get better performance with flow control.
2011-11-28 19:03:59 +00:00
/*
* Let controller know how many number of RX buffers
* are posted but avoid expensive register access if
* TX pause capability was not negotiated with link
* partner.
*/
if ((sc->vr_flags & VR_F_TXPAUSE) != 0) {
if (prog >= VR_RX_RING_CNT)
prog = VR_RX_RING_CNT - 1;
CSR_WRITE_1(sc, VR_FLOWCR0, prog);
}
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc->vr_cdata.vr_rx_cons = cons;
bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag,
sc->vr_cdata.vr_rx_ring_map,
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
}
When user_frac in the polling subsystem is low it is going to busy the CPU for too long period than necessary. Additively, interfaces are kept polled (in the tick) even if no more packets are available. In order to avoid such situations a new generic mechanism can be implemented in proactive way, keeping track of the time spent on any packet and fragmenting the time for any tick, stopping the processing as soon as possible. In order to implement such mechanism, the polling handler needs to change, returning the number of packets processed. While the intended logic is not part of this patch, the polling KPI is broken by this commit, adding an int return value and the new flag IFCAP_POLLING_NOCOUNT (which will signal that the return value is meaningless for the installed handler and checking should be skipped). Bump __FreeBSD_version in order to signal such situation. Reviewed by: emaste Sponsored by: Sandvine Incorporated
2009-05-30 15:14:44 +00:00
return (rx_npkts);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
/*
* A frame was downloaded to the chip. It's safe for us to clean up
* the list buffers.
*/
style: put return types on a line by themselves.
2002-08-24 00:02:03 +00:00
static void
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
vr_txeof(struct vr_softc *sc)
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
{
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
struct vr_txdesc *txd;
Remove further cobwebs: Two layers of pointless substructures.
2007-04-22 15:48:29 +00:00
struct vr_desc *cur_tx;
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
struct ifnet *ifp;
uint32_t txctl, txstat;
int cons, prod;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
SMPng locking cleanup for vr(4). - Remove recursive locking situations. Remove the MTX_RECURSE bit. - Take the lock for any routine which is not called from within if_vr.c itself; this includes entry points called by newbus, ifnet, callout, ifmedia, and polling subsystems. - Remove spl references from the code added to miibus callbacks in rev 1.60. - Add the INTR_MPSAFE bit. - Tidy up some assignments; locks are not needed for taking the address of something at a known offset, for example. - Tested on the machine this was committed from. Tested on: UP only, !debug.mpsafenet && debug.mpsafenet Reviewed by: rwatson
2004-07-03 02:59:02 +00:00
VR_LOCK_ASSERT(sc);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
cons = sc->vr_cdata.vr_tx_cons;
prod = sc->vr_cdata.vr_tx_prod;
if (cons == prod)
return;
bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag,
sc->vr_cdata.vr_tx_ring_map,
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
ifp = sc->vr_ifp;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
/*
* Go through our tx list and free mbufs for those
* frames that have been transmitted.
*/
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
for (; cons != prod; VR_INC(cons, VR_TX_RING_CNT)) {
cur_tx = &sc->vr_rdata.vr_tx_ring[cons];
txctl = le32toh(cur_tx->vr_ctl);
txstat = le32toh(cur_tx->vr_status);
if ((txstat & VR_TXSTAT_OWN) == VR_TXSTAT_OWN)
Improve handling of TX errors. Early reports indicate that this elimiates the driver lockup problem reported by many. Concepts used were taken from Via's if_fet driver. Verification and implementation were done by Thomas Nystrom. Submitted by: Thomas Nystrom <thn@saeab.se> MFC after: 3 days
2002-08-15 04:04:53 +00:00
break;
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc->vr_cdata.vr_tx_cnt--;
ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
/* Only the first descriptor in the chain is valid. */
if ((txctl & VR_TXCTL_FIRSTFRAG) == 0)
continue;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
txd = &sc->vr_cdata.vr_txdesc[cons];
KASSERT(txd->tx_m != NULL, ("%s: accessing NULL mbuf!\n",
__func__));
if ((txstat & VR_TXSTAT_ERRSUM) != 0) {
Mechanically convert to if_inc_counter().
2014-09-18 20:17:27 +00:00
if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc->vr_stat.tx_errors++;
if ((txstat & VR_TXSTAT_ABRT) != 0) {
/* Give up and restart Tx. */
sc->vr_stat.tx_abort++;
bus_dmamap_sync(sc->vr_cdata.vr_tx_tag,
txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->vr_cdata.vr_tx_tag,
txd->tx_dmamap);
m_freem(txd->tx_m);
txd->tx_m = NULL;
VR_INC(cons, VR_TX_RING_CNT);
sc->vr_cdata.vr_tx_cons = cons;
if (vr_tx_stop(sc) != 0) {
device_printf(sc->vr_dev,
"%s: Tx shutdown error -- "
"resetting\n", __func__);
sc->vr_flags |= VR_F_RESTART;
return;
}
vr_tx_start(sc);
break;
}
if ((sc->vr_revid < REV_ID_VT3071_A &&
(txstat & VR_TXSTAT_UNDERRUN)) ||
(txstat & (VR_TXSTAT_UDF | VR_TXSTAT_TBUFF))) {
sc->vr_stat.tx_underrun++;
/* Retry and restart Tx. */
sc->vr_cdata.vr_tx_cnt++;
sc->vr_cdata.vr_tx_cons = cons;
cur_tx->vr_status = htole32(VR_TXSTAT_OWN);
bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag,
sc->vr_cdata.vr_tx_ring_map,
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
vr_tx_underrun(sc);
return;
}
if ((txstat & VR_TXSTAT_DEFER) != 0) {
Mechanically convert to if_inc_counter().
2014-09-18 20:17:27 +00:00
if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc->vr_stat.tx_collisions++;
}
if ((txstat & VR_TXSTAT_LATECOLL) != 0) {
Mechanically convert to if_inc_counter().
2014-09-18 20:17:27 +00:00
if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc->vr_stat.tx_late_collisions++;
}
} else {
sc->vr_stat.tx_ok++;
Mechanically convert to if_inc_counter().
2014-09-18 20:17:27 +00:00
if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap,
BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap);
if (sc->vr_revid < REV_ID_VT3071_A) {
Mechanically convert to if_inc_counter().
2014-09-18 20:17:27 +00:00
if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
(txstat & VR_TXSTAT_COLLCNT) >> 3);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc->vr_stat.tx_collisions +=
(txstat & VR_TXSTAT_COLLCNT) >> 3;
} else {
Mechanically convert to if_inc_counter().
2014-09-18 20:17:27 +00:00
if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (txstat & 0x0f));
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc->vr_stat.tx_collisions += (txstat & 0x0f);
}
m_freem(txd->tx_m);
txd->tx_m = NULL;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc->vr_cdata.vr_tx_cons = cons;
if (sc->vr_cdata.vr_tx_cnt == 0)
sc->vr_watchdog_timer = 0;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
style: put return types on a line by themselves.
2002-08-24 00:02:03 +00:00
static void
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
vr_tick(void *xsc)
Convert the VIA Rhine driver to miibus.
1999-09-19 22:03:31 +00:00
{
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
struct vr_softc *sc;
Convert the VIA Rhine driver to miibus.
1999-09-19 22:03:31 +00:00
struct mii_data *mii;
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc = (struct vr_softc *)xsc;
- Use callout_*() to manage the callout and make it MPSAFE. - Fix locking in detach(), we only need to lock across vr_stop(). Tested by: Mike Tancsa mike at sentex dot net MFC after: 1 week
2005-10-31 21:37:27 +00:00
VR_LOCK_ASSERT(sc);
- Another whitespace pass; make locking calls more obvious. - Use C99 types for vr_miibus_readreg().
2004-07-03 02:52:32 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if ((sc->vr_flags & VR_F_RESTART) != 0) {
Consistently use if_printf() only in interface methods: if_start, if_ioctl, if_watchdog, etc, or in functions that are used by these methods only. In all other cases use device_printf(). This also fixes several panics, when if_printf() is called before softc->ifp was initialized. Submitted by: Alex Lyashkov <umka sevcity.net>
2006-09-15 10:40:54 +00:00
device_printf(sc->vr_dev, "restarting\n");
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc->vr_stat.num_restart++;
Remove unnecessary controller reinitialization. CAM filter handling was rewritten long time ago so it should not require controller reinitialization. PR: kern/87506
2010-08-24 18:40:11 +00:00
sc->vr_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
Further locking improvements for vr(4): - Add *_locked() entry points as needed to avoid unnecessary lock thrashing. - Use these entry points wisely. - Only acquire the lock once when servicing an interrupt. - Check 'suspended' on interrupt to avoid racing detach. - Correct a mis-spelled comment. - Don't take the lock in vr_reset() to avoid lock thrashing in attach. - Comment this. Reviewed by: -net (silence)
2004-07-09 00:17:14 +00:00
vr_init_locked(sc);
Fixes from Thomas Nystrom to fix hanging problems experienced by vr cards under load. This patch has been tested by Thomas and other for more than a month now, and all (known) hangs seem to be solved. Thomas's explanation of the patch: * Fix the problem with the printing of the RX-error. * Code from if_fet do better deal with the RX-recovery including a timeout of the RX-turnoff. * The call to vr_rxeof before vr_rxeoc have been moved to a point where the RX-part of the chip is turned off. Otherwise there is a window where new data could have been written to the buffer chain before the RX-part is turned off. If this happens the chip will see a busy rx-buffer. I have no evidence that this have occured but god knows what the chip will do in this case! * I have added a timeout of the TX-turnoff. I have checked and in my 900 MHz system the flags for turnoff (both RX & TX) is seen at the first check in the loop. * I could see that I got the VR_ISR_DROPPED interrupt sometimes and started to thinking about this. I then realized that no recovery is needed for this case and therefore I only count it as an rxerror (which was not done before). * Finally I have changed the FIFO RX threshhold to 128 bytes. When I did this the VR_ISR_DROPPED interrupt went away. Theory: The chip will receive a complete frame before it tries to write it out to memory then the RX threshold is set to store'n'forward. IF the frame is large AND the next rx frame also is large AND the bus is busy transfering a TX frame to the TX fifo THEN the second received frame wont fit in the FIFO and is then dropped. By having the RX threshold set to 128 the RX fifo is emptied faster. MFC after: 5 days
2003-01-31 07:37:06 +00:00
sc->vr_flags &= ~VR_F_RESTART;
}
Convert the VIA Rhine driver to miibus.
1999-09-19 22:03:31 +00:00
mii = device_get_softc(sc->vr_miibus);
mii_tick(mii);
Reuse flag variable to represent driver internal states rather than using member variables in softc. While I'm here change media after setting IFF_DRV_RUNNING. This will remove unnecessary link state handling in vr_tick() if controller established a link immediately.
2011-11-28 18:32:35 +00:00
if ((sc->vr_flags & VR_F_LINK) == 0)
Remove link state change callback handler. There is no need to register both status change and link state change callbacks. Implement checking valid link in state change callback and poll active link state in vr_tick(). This allows immediate detection of lost link as well as protecting driver from frequent link flips during link renegotiation. taskq implementation was removed because driver now needs to poll link state in vr_tick(). While I'm here do not report current link state if interface is not running. Tested by: n_hibma MFC after: 1 week
2011-06-22 02:18:45 +00:00
vr_miibus_statchg(sc->vr_dev);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
vr_watchdog(sc);
- Use callout_*() to manage the callout and make it MPSAFE. - Fix locking in detach(), we only need to lock across vr_stop(). Tested by: Mike Tancsa mike at sentex dot net MFC after: 1 week
2005-10-31 21:37:27 +00:00
callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc);
Convert the VIA Rhine driver to miibus.
1999-09-19 22:03:31 +00:00
}
- Rewritten TX to use only two pointers to track producer/consumer. - Added polling(4) support! - Bugfix: don't forget to set IFF_OACTIVE when TX list is full. - Minor: tidy up vr_encap().
2004-04-05 17:39:57 +00:00
#ifdef DEVICE_POLLING
static poll_handler_t vr_poll;
Further locking improvements for vr(4): - Add *_locked() entry points as needed to avoid unnecessary lock thrashing. - Use these entry points wisely. - Only acquire the lock once when servicing an interrupt. - Check 'suspended' on interrupt to avoid racing detach. - Correct a mis-spelled comment. - Don't take the lock in vr_reset() to avoid lock thrashing in attach. - Comment this. Reviewed by: -net (silence)
2004-07-09 00:17:14 +00:00
static poll_handler_t vr_poll_locked;
- Rewritten TX to use only two pointers to track producer/consumer. - Added polling(4) support! - Bugfix: don't forget to set IFF_OACTIVE when TX list is full. - Minor: tidy up vr_encap().
2004-04-05 17:39:57 +00:00
When user_frac in the polling subsystem is low it is going to busy the CPU for too long period than necessary. Additively, interfaces are kept polled (in the tick) even if no more packets are available. In order to avoid such situations a new generic mechanism can be implemented in proactive way, keeping track of the time spent on any packet and fragmenting the time for any tick, stopping the processing as soon as possible. In order to implement such mechanism, the polling handler needs to change, returning the number of packets processed. While the intended logic is not part of this patch, the polling KPI is broken by this commit, adding an int return value and the new flag IFCAP_POLLING_NOCOUNT (which will signal that the return value is meaningless for the installed handler and checking should be skipped). Bump __FreeBSD_version in order to signal such situation. Reviewed by: emaste Sponsored by: Sandvine Incorporated
2009-05-30 15:14:44 +00:00
static int
- Rewritten TX to use only two pointers to track producer/consumer. - Added polling(4) support! - Bugfix: don't forget to set IFF_OACTIVE when TX list is full. - Minor: tidy up vr_encap().
2004-04-05 17:39:57 +00:00
vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
{
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
struct vr_softc *sc;
When user_frac in the polling subsystem is low it is going to busy the CPU for too long period than necessary. Additively, interfaces are kept polled (in the tick) even if no more packets are available. In order to avoid such situations a new generic mechanism can be implemented in proactive way, keeping track of the time spent on any packet and fragmenting the time for any tick, stopping the processing as soon as possible. In order to implement such mechanism, the polling handler needs to change, returning the number of packets processed. While the intended logic is not part of this patch, the polling KPI is broken by this commit, adding an int return value and the new flag IFCAP_POLLING_NOCOUNT (which will signal that the return value is meaningless for the installed handler and checking should be skipped). Bump __FreeBSD_version in order to signal such situation. Reviewed by: emaste Sponsored by: Sandvine Incorporated
2009-05-30 15:14:44 +00:00
int rx_npkts;
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc = ifp->if_softc;
When user_frac in the polling subsystem is low it is going to busy the CPU for too long period than necessary. Additively, interfaces are kept polled (in the tick) even if no more packets are available. In order to avoid such situations a new generic mechanism can be implemented in proactive way, keeping track of the time spent on any packet and fragmenting the time for any tick, stopping the processing as soon as possible. In order to implement such mechanism, the polling handler needs to change, returning the number of packets processed. While the intended logic is not part of this patch, the polling KPI is broken by this commit, adding an int return value and the new flag IFCAP_POLLING_NOCOUNT (which will signal that the return value is meaningless for the installed handler and checking should be skipped). Bump __FreeBSD_version in order to signal such situation. Reviewed by: emaste Sponsored by: Sandvine Incorporated
2009-05-30 15:14:44 +00:00
rx_npkts = 0;
- Rewritten TX to use only two pointers to track producer/consumer. - Added polling(4) support! - Bugfix: don't forget to set IFF_OACTIVE when TX list is full. - Minor: tidy up vr_encap().
2004-04-05 17:39:57 +00:00
VR_LOCK(sc);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
When user_frac in the polling subsystem is low it is going to busy the CPU for too long period than necessary. Additively, interfaces are kept polled (in the tick) even if no more packets are available. In order to avoid such situations a new generic mechanism can be implemented in proactive way, keeping track of the time spent on any packet and fragmenting the time for any tick, stopping the processing as soon as possible. In order to implement such mechanism, the polling handler needs to change, returning the number of packets processed. While the intended logic is not part of this patch, the polling KPI is broken by this commit, adding an int return value and the new flag IFCAP_POLLING_NOCOUNT (which will signal that the return value is meaningless for the installed handler and checking should be skipped). Bump __FreeBSD_version in order to signal such situation. Reviewed by: emaste Sponsored by: Sandvine Incorporated
2009-05-30 15:14:44 +00:00
rx_npkts = vr_poll_locked(ifp, cmd, count);
Further locking improvements for vr(4): - Add *_locked() entry points as needed to avoid unnecessary lock thrashing. - Use these entry points wisely. - Only acquire the lock once when servicing an interrupt. - Check 'suspended' on interrupt to avoid racing detach. - Correct a mis-spelled comment. - Don't take the lock in vr_reset() to avoid lock thrashing in attach. - Comment this. Reviewed by: -net (silence)
2004-07-09 00:17:14 +00:00
VR_UNLOCK(sc);
When user_frac in the polling subsystem is low it is going to busy the CPU for too long period than necessary. Additively, interfaces are kept polled (in the tick) even if no more packets are available. In order to avoid such situations a new generic mechanism can be implemented in proactive way, keeping track of the time spent on any packet and fragmenting the time for any tick, stopping the processing as soon as possible. In order to implement such mechanism, the polling handler needs to change, returning the number of packets processed. While the intended logic is not part of this patch, the polling KPI is broken by this commit, adding an int return value and the new flag IFCAP_POLLING_NOCOUNT (which will signal that the return value is meaningless for the installed handler and checking should be skipped). Bump __FreeBSD_version in order to signal such situation. Reviewed by: emaste Sponsored by: Sandvine Incorporated
2009-05-30 15:14:44 +00:00
return (rx_npkts);
Further locking improvements for vr(4): - Add *_locked() entry points as needed to avoid unnecessary lock thrashing. - Use these entry points wisely. - Only acquire the lock once when servicing an interrupt. - Check 'suspended' on interrupt to avoid racing detach. - Correct a mis-spelled comment. - Don't take the lock in vr_reset() to avoid lock thrashing in attach. - Comment this. Reviewed by: -net (silence)
2004-07-09 00:17:14 +00:00
}
When user_frac in the polling subsystem is low it is going to busy the CPU for too long period than necessary. Additively, interfaces are kept polled (in the tick) even if no more packets are available. In order to avoid such situations a new generic mechanism can be implemented in proactive way, keeping track of the time spent on any packet and fragmenting the time for any tick, stopping the processing as soon as possible. In order to implement such mechanism, the polling handler needs to change, returning the number of packets processed. While the intended logic is not part of this patch, the polling KPI is broken by this commit, adding an int return value and the new flag IFCAP_POLLING_NOCOUNT (which will signal that the return value is meaningless for the installed handler and checking should be skipped). Bump __FreeBSD_version in order to signal such situation. Reviewed by: emaste Sponsored by: Sandvine Incorporated
2009-05-30 15:14:44 +00:00
static int
Further locking improvements for vr(4): - Add *_locked() entry points as needed to avoid unnecessary lock thrashing. - Use these entry points wisely. - Only acquire the lock once when servicing an interrupt. - Check 'suspended' on interrupt to avoid racing detach. - Correct a mis-spelled comment. - Don't take the lock in vr_reset() to avoid lock thrashing in attach. - Comment this. Reviewed by: -net (silence)
2004-07-09 00:17:14 +00:00
vr_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
{
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
struct vr_softc *sc;
When user_frac in the polling subsystem is low it is going to busy the CPU for too long period than necessary. Additively, interfaces are kept polled (in the tick) even if no more packets are available. In order to avoid such situations a new generic mechanism can be implemented in proactive way, keeping track of the time spent on any packet and fragmenting the time for any tick, stopping the processing as soon as possible. In order to implement such mechanism, the polling handler needs to change, returning the number of packets processed. While the intended logic is not part of this patch, the polling KPI is broken by this commit, adding an int return value and the new flag IFCAP_POLLING_NOCOUNT (which will signal that the return value is meaningless for the installed handler and checking should be skipped). Bump __FreeBSD_version in order to signal such situation. Reviewed by: emaste Sponsored by: Sandvine Incorporated
2009-05-30 15:14:44 +00:00
int rx_npkts;
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc = ifp->if_softc;
Further locking improvements for vr(4): - Add *_locked() entry points as needed to avoid unnecessary lock thrashing. - Use these entry points wisely. - Only acquire the lock once when servicing an interrupt. - Check 'suspended' on interrupt to avoid racing detach. - Correct a mis-spelled comment. - Don't take the lock in vr_reset() to avoid lock thrashing in attach. - Comment this. Reviewed by: -net (silence)
2004-07-09 00:17:14 +00:00
VR_LOCK_ASSERT(sc);
- Another whitespace pass; make locking calls more obvious. - Use C99 types for vr_miibus_readreg().
2004-07-03 02:52:32 +00:00
- Rewritten TX to use only two pointers to track producer/consumer. - Added polling(4) support! - Bugfix: don't forget to set IFF_OACTIVE when TX list is full. - Minor: tidy up vr_encap().
2004-04-05 17:39:57 +00:00
sc->rxcycles = count;
When user_frac in the polling subsystem is low it is going to busy the CPU for too long period than necessary. Additively, interfaces are kept polled (in the tick) even if no more packets are available. In order to avoid such situations a new generic mechanism can be implemented in proactive way, keeping track of the time spent on any packet and fragmenting the time for any tick, stopping the processing as soon as possible. In order to implement such mechanism, the polling handler needs to change, returning the number of packets processed. While the intended logic is not part of this patch, the polling KPI is broken by this commit, adding an int return value and the new flag IFCAP_POLLING_NOCOUNT (which will signal that the return value is meaningless for the installed handler and checking should be skipped). Bump __FreeBSD_version in order to signal such situation. Reviewed by: emaste Sponsored by: Sandvine Incorporated
2009-05-30 15:14:44 +00:00
rx_npkts = vr_rxeof(sc);
- Rewritten TX to use only two pointers to track producer/consumer. - Added polling(4) support! - Bugfix: don't forget to set IFF_OACTIVE when TX list is full. - Minor: tidy up vr_encap().
2004-04-05 17:39:57 +00:00
vr_txeof(sc);
Unbreak DEVICE_POLLING build / LINT. Sorry! Submitted by: roam
2004-08-02 10:08:28 +00:00
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
Further locking improvements for vr(4): - Add *_locked() entry points as needed to avoid unnecessary lock thrashing. - Use these entry points wisely. - Only acquire the lock once when servicing an interrupt. - Check 'suspended' on interrupt to avoid racing detach. - Correct a mis-spelled comment. - Don't take the lock in vr_reset() to avoid lock thrashing in attach. - Comment this. Reviewed by: -net (silence)
2004-07-09 00:17:14 +00:00
vr_start_locked(ifp);
- Rewritten TX to use only two pointers to track producer/consumer. - Added polling(4) support! - Bugfix: don't forget to set IFF_OACTIVE when TX list is full. - Minor: tidy up vr_encap().
2004-04-05 17:39:57 +00:00
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
if (cmd == POLL_AND_CHECK_STATUS) {
uint16_t status;
- Rewritten TX to use only two pointers to track producer/consumer. - Added polling(4) support! - Bugfix: don't forget to set IFF_OACTIVE when TX list is full. - Minor: tidy up vr_encap().
2004-04-05 17:39:57 +00:00
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
/* Also check status register. */
- Rewritten TX to use only two pointers to track producer/consumer. - Added polling(4) support! - Bugfix: don't forget to set IFF_OACTIVE when TX list is full. - Minor: tidy up vr_encap().
2004-04-05 17:39:57 +00:00
status = CSR_READ_2(sc, VR_ISR);
if (status)
CSR_WRITE_2(sc, VR_ISR, status);
if ((status & VR_INTRS) == 0)
When user_frac in the polling subsystem is low it is going to busy the CPU for too long period than necessary. Additively, interfaces are kept polled (in the tick) even if no more packets are available. In order to avoid such situations a new generic mechanism can be implemented in proactive way, keeping track of the time spent on any packet and fragmenting the time for any tick, stopping the processing as soon as possible. In order to implement such mechanism, the polling handler needs to change, returning the number of packets processed. While the intended logic is not part of this patch, the polling KPI is broken by this commit, adding an int return value and the new flag IFCAP_POLLING_NOCOUNT (which will signal that the return value is meaningless for the installed handler and checking should be skipped). Bump __FreeBSD_version in order to signal such situation. Reviewed by: emaste Sponsored by: Sandvine Incorporated
2009-05-30 15:14:44 +00:00
return (rx_npkts);
- Rewritten TX to use only two pointers to track producer/consumer. - Added polling(4) support! - Bugfix: don't forget to set IFF_OACTIVE when TX list is full. - Minor: tidy up vr_encap().
2004-04-05 17:39:57 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if ((status & (VR_ISR_BUSERR | VR_ISR_LINKSTAT2 |
VR_ISR_STATSOFLOW)) != 0) {
if (vr_error(sc, status) != 0)
When user_frac in the polling subsystem is low it is going to busy the CPU for too long period than necessary. Additively, interfaces are kept polled (in the tick) even if no more packets are available. In order to avoid such situations a new generic mechanism can be implemented in proactive way, keeping track of the time spent on any packet and fragmenting the time for any tick, stopping the processing as soon as possible. In order to implement such mechanism, the polling handler needs to change, returning the number of packets processed. While the intended logic is not part of this patch, the polling KPI is broken by this commit, adding an int return value and the new flag IFCAP_POLLING_NOCOUNT (which will signal that the return value is meaningless for the installed handler and checking should be skipped). Bump __FreeBSD_version in order to signal such situation. Reviewed by: emaste Sponsored by: Sandvine Incorporated
2009-05-30 15:14:44 +00:00
return (rx_npkts);
- Rewritten TX to use only two pointers to track producer/consumer. - Added polling(4) support! - Bugfix: don't forget to set IFF_OACTIVE when TX list is full. - Minor: tidy up vr_encap().
2004-04-05 17:39:57 +00:00
}
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if ((status & (VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) != 0) {
#ifdef VR_SHOW_ERRORS
device_printf(sc->vr_dev, "%s: receive error : 0x%b\n",
__func__, status, VR_ISR_ERR_BITS);
#endif
vr_rx_start(sc);
- Rewritten TX to use only two pointers to track producer/consumer. - Added polling(4) support! - Bugfix: don't forget to set IFF_OACTIVE when TX list is full. - Minor: tidy up vr_encap().
2004-04-05 17:39:57 +00:00
}
}
When user_frac in the polling subsystem is low it is going to busy the CPU for too long period than necessary. Additively, interfaces are kept polled (in the tick) even if no more packets are available. In order to avoid such situations a new generic mechanism can be implemented in proactive way, keeping track of the time spent on any packet and fragmenting the time for any tick, stopping the processing as soon as possible. In order to implement such mechanism, the polling handler needs to change, returning the number of packets processed. While the intended logic is not part of this patch, the polling KPI is broken by this commit, adding an int return value and the new flag IFCAP_POLLING_NOCOUNT (which will signal that the return value is meaningless for the installed handler and checking should be skipped). Bump __FreeBSD_version in order to signal such situation. Reviewed by: emaste Sponsored by: Sandvine Incorporated
2009-05-30 15:14:44 +00:00
return (rx_npkts);
- Rewritten TX to use only two pointers to track producer/consumer. - Added polling(4) support! - Bugfix: don't forget to set IFF_OACTIVE when TX list is full. - Minor: tidy up vr_encap().
2004-04-05 17:39:57 +00:00
}
#endif /* DEVICE_POLLING */
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
/* Back off the transmit threshold. */
static void
vr_tx_underrun(struct vr_softc *sc)
{
int thresh;
device_printf(sc->vr_dev, "Tx underrun -- ");
if (sc->vr_txthresh < VR_TXTHRESH_MAX) {
thresh = sc->vr_txthresh;
sc->vr_txthresh++;
if (sc->vr_txthresh >= VR_TXTHRESH_MAX) {
sc->vr_txthresh = VR_TXTHRESH_MAX;
printf("using store and forward mode\n");
} else
printf("increasing Tx threshold(%d -> %d)\n",
vr_tx_threshold_tables[thresh].value,
vr_tx_threshold_tables[thresh + 1].value);
} else
printf("\n");
sc->vr_stat.tx_underrun++;
if (vr_tx_stop(sc) != 0) {
device_printf(sc->vr_dev, "%s: Tx shutdown error -- "
"resetting\n", __func__);
sc->vr_flags |= VR_F_RESTART;
return;
}
vr_tx_start(sc);
}
Convert the if_vr(4) driver model to the interrupt filter model and use a taskqueue. This gives a 16% performance improvement under high load on slow systems, especially when vr shares an interrupt with another device, which is common with the Alix x86 boards. Contrary to the other devices, I left the interrupt processing for loop in because there was no significant difference in performance and this should avoid enqueuing more taskqueues unnecessarily. We also decided to move the vr_start_locked() call inside the for loop because we found out that it helps performance since TCP ACKs now have a chance to go out quicker. Reviewed by: yongari (older version, same idea) Discussed with: yongari, jhb
2012-05-12 14:37:25 +00:00
static int
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
vr_intr(void *arg)
Convert the if_vr(4) driver model to the interrupt filter model and use a taskqueue. This gives a 16% performance improvement under high load on slow systems, especially when vr shares an interrupt with another device, which is common with the Alix x86 boards. Contrary to the other devices, I left the interrupt processing for loop in because there was no significant difference in performance and this should avoid enqueuing more taskqueues unnecessarily. We also decided to move the vr_start_locked() call inside the for loop because we found out that it helps performance since TCP ACKs now have a chance to go out quicker. Reviewed by: yongari (older version, same idea) Discussed with: yongari, jhb
2012-05-12 14:37:25 +00:00
{
struct vr_softc *sc;
uint16_t status;
sc = (struct vr_softc *)arg;
status = CSR_READ_2(sc, VR_ISR);
if (status == 0 || status == 0xffff || (status & VR_INTRS) == 0)
return (FILTER_STRAY);
/* Disable interrupts. */
CSR_WRITE_2(sc, VR_IMR, 0x0000);
Remove taskqueue_enqueue_fast(). taskqueue_enqueue() was changed to support both fast and non-fast taskqueues 10 years ago in r154167. It has been a compat shim ever since. It's time for the compat shim to go. Submitted by: Howard Su <howard0su@gmail.com> Reviewed by: sephe Differential Revision: https://reviews.freebsd.org/D5131
2016-03-01 17:47:32 +00:00
taskqueue_enqueue(taskqueue_fast, &sc->vr_inttask);
Convert the if_vr(4) driver model to the interrupt filter model and use a taskqueue. This gives a 16% performance improvement under high load on slow systems, especially when vr shares an interrupt with another device, which is common with the Alix x86 boards. Contrary to the other devices, I left the interrupt processing for loop in because there was no significant difference in performance and this should avoid enqueuing more taskqueues unnecessarily. We also decided to move the vr_start_locked() call inside the for loop because we found out that it helps performance since TCP ACKs now have a chance to go out quicker. Reviewed by: yongari (older version, same idea) Discussed with: yongari, jhb
2012-05-12 14:37:25 +00:00
return (FILTER_HANDLED);
}
static void
vr_int_task(void *arg, int npending)
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
{
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
struct vr_softc *sc;
struct ifnet *ifp;
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
uint16_t status;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc = (struct vr_softc *)arg;
First round of converting network drivers from spls to mutexes. This takes care of all the 10/100 and gigE PCI drivers that I've done. Next will be the wireless drivers, then the USB ones. I may pick up some stragglers along the way. I'm sort of playing this by ear: if anyone spots any places where I've screwed up horribly, please let me know.
2000-10-13 17:54:19 +00:00
VR_LOCK(sc);
Further locking improvements for vr(4): - Add *_locked() entry points as needed to avoid unnecessary lock thrashing. - Use these entry points wisely. - Only acquire the lock once when servicing an interrupt. - Check 'suspended' on interrupt to avoid racing detach. - Correct a mis-spelled comment. - Don't take the lock in vr_reset() to avoid lock thrashing in attach. - Comment this. Reviewed by: -net (silence)
2004-07-09 00:17:14 +00:00
Reuse flag variable to represent driver internal states rather than using member variables in softc. While I'm here change media after setting IFF_DRV_RUNNING. This will remove unnecessary link state handling in vr_tick() if controller established a link immediately.
2011-11-28 18:32:35 +00:00
if ((sc->vr_flags & VR_F_SUSPENDED) != 0)
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
goto done_locked;
status = CSR_READ_2(sc, VR_ISR);
ifp = sc->vr_ifp;
- Rewritten TX to use only two pointers to track producer/consumer. - Added polling(4) support! - Bugfix: don't forget to set IFF_OACTIVE when TX list is full. - Minor: tidy up vr_encap().
2004-04-05 17:39:57 +00:00
#ifdef DEVICE_POLLING
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if ((ifp->if_capenable & IFCAP_POLLING) != 0)
Further locking improvements for vr(4): - Add *_locked() entry points as needed to avoid unnecessary lock thrashing. - Use these entry points wisely. - Only acquire the lock once when servicing an interrupt. - Check 'suspended' on interrupt to avoid racing detach. - Correct a mis-spelled comment. - Don't take the lock in vr_reset() to avoid lock thrashing in attach. - Comment this. Reviewed by: -net (silence)
2004-07-09 00:17:14 +00:00
goto done_locked;
Big polling(4) cleanup. o Axe poll in trap. o Axe IFF_POLLING flag from if_flags. o Rework revision 1.21 (Giant removal), in such a way that poll_mtx is not dropped during call to polling handler. This fixes problem with idle polling. o Make registration and deregistration from polling in a functional way, insted of next tick/interrupt. o Obsolete kern.polling.enable. Polling is turned on/off with ifconfig. Detailed kern_poll.c changes: - Remove polling handler flags, introduced in 1.21. The are not needed now. - Forget and do not check if_flags, if_capenable and if_drv_flags. - Call all registered polling handlers unconditionally. - Do not drop poll_mtx, when entering polling handlers. - In ether_poll() NET_LOCK_GIANT prior to locking poll_mtx. - In netisr_poll() axe the block, where polling code asks drivers to unregister. - In netisr_poll() and ether_poll() do polling always, if any handlers are present. - In ether_poll_[de]register() remove a lot of error hiding code. Assert that arguments are correct, instead. - In ether_poll_[de]register() use standard return values in case of error or success. - Introduce poll_switch() that is a sysctl handler for kern.polling.enable. poll_switch() goes through interface list and enabled/disables polling. A message that kern.polling.enable is deprecated is printed. Detailed driver changes: - On attach driver announces IFCAP_POLLING in if_capabilities, but not in if_capenable. - On detach driver calls ether_poll_deregister() if polling is enabled. - In polling handler driver obtains its lock and checks IFF_DRV_RUNNING flag. If there is no, then unlocks and returns. - In ioctl handler driver checks for IFCAP_POLLING flag requested to be set or cleared. Driver first calls ether_poll_[de]register(), then obtains driver lock and [dis/en]ables interrupts. - In interrupt handler driver checks IFCAP_POLLING flag in if_capenable. If present, then returns.This is important to protect from spurious interrupts. Reviewed by: ru, sam, jhb
2005-10-01 18:56:19 +00:00
#endif
- Rewritten TX to use only two pointers to track producer/consumer. - Added polling(4) support! - Bugfix: don't forget to set IFF_OACTIVE when TX list is full. - Minor: tidy up vr_encap().
2004-04-05 17:39:57 +00:00
Further locking improvements for vr(4): - Add *_locked() entry points as needed to avoid unnecessary lock thrashing. - Use these entry points wisely. - Only acquire the lock once when servicing an interrupt. - Check 'suspended' on interrupt to avoid racing detach. - Correct a mis-spelled comment. - Don't take the lock in vr_reset() to avoid lock thrashing in attach. - Comment this. Reviewed by: -net (silence)
2004-07-09 00:17:14 +00:00
/* Suppress unwanted interrupts. */
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ||
(sc->vr_flags & VR_F_RESTART) != 0) {
CSR_WRITE_2(sc, VR_IMR, 0);
CSR_WRITE_2(sc, VR_ISR, status);
Further locking improvements for vr(4): - Add *_locked() entry points as needed to avoid unnecessary lock thrashing. - Use these entry points wisely. - Only acquire the lock once when servicing an interrupt. - Check 'suspended' on interrupt to avoid racing detach. - Correct a mis-spelled comment. - Don't take the lock in vr_reset() to avoid lock thrashing in attach. - Comment this. Reviewed by: -net (silence)
2004-07-09 00:17:14 +00:00
goto done_locked;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
for (; (status & VR_INTRS) != 0;) {
CSR_WRITE_2(sc, VR_ISR, status);
if ((status & (VR_ISR_BUSERR | VR_ISR_LINKSTAT2 |
VR_ISR_STATSOFLOW)) != 0) {
if (vr_error(sc, status) != 0) {
VR_UNLOCK(sc);
return;
}
}
vr_rxeof(sc);
if ((status & (VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) != 0) {
#ifdef VR_SHOW_ERRORS
device_printf(sc->vr_dev, "%s: receive error = 0x%b\n",
__func__, status, VR_ISR_ERR_BITS);
#endif
/* Restart Rx if RxDMA SM was stopped. */
vr_rx_start(sc);
}
vr_txeof(sc);
Convert the if_vr(4) driver model to the interrupt filter model and use a taskqueue. This gives a 16% performance improvement under high load on slow systems, especially when vr shares an interrupt with another device, which is common with the Alix x86 boards. Contrary to the other devices, I left the interrupt processing for loop in because there was no significant difference in performance and this should avoid enqueuing more taskqueues unnecessarily. We also decided to move the vr_start_locked() call inside the for loop because we found out that it helps performance since TCP ACKs now have a chance to go out quicker. Reviewed by: yongari (older version, same idea) Discussed with: yongari, jhb
2012-05-12 14:37:25 +00:00
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
vr_start_locked(ifp);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
status = CSR_READ_2(sc, VR_ISR);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
}
Improve the if_vr driver ever so slightly. The 6105M and 6102 does not have the DWORD alignment problem, so don't m_defrag() every packet in the transmit path for those. More stringent usage of tx-descriptor ring and its flags. Tested on 6102 and 6105M, other chips may also be able to run without the m_defrag() but I have neither hardware nor docs to find out. Sponsored by: Soekris Engineering
2007-04-17 12:23:57 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
/* Re-enable interrupts. */
CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
done_locked:
VR_UNLOCK(sc);
}
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
static int
vr_error(struct vr_softc *sc, uint16_t status)
{
uint16_t pcis;
Fixes from Thomas Nystrom to fix hanging problems experienced by vr cards under load. This patch has been tested by Thomas and other for more than a month now, and all (known) hangs seem to be solved. Thomas's explanation of the patch: * Fix the problem with the printing of the RX-error. * Code from if_fet do better deal with the RX-recovery including a timeout of the RX-turnoff. * The call to vr_rxeof before vr_rxeoc have been moved to a point where the RX-part of the chip is turned off. Otherwise there is a window where new data could have been written to the buffer chain before the RX-part is turned off. If this happens the chip will see a busy rx-buffer. I have no evidence that this have occured but god knows what the chip will do in this case! * I have added a timeout of the TX-turnoff. I have checked and in my 900 MHz system the flags for turnoff (both RX & TX) is seen at the first check in the loop. * I could see that I got the VR_ISR_DROPPED interrupt sometimes and started to thinking about this. I then realized that no recovery is needed for this case and therefore I only count it as an rxerror (which was not done before). * Finally I have changed the FIFO RX threshhold to 128 bytes. When I did this the VR_ISR_DROPPED interrupt went away. Theory: The chip will receive a complete frame before it tries to write it out to memory then the RX threshold is set to store'n'forward. IF the frame is large AND the next rx frame also is large AND the bus is busy transfering a TX frame to the TX fifo THEN the second received frame wont fit in the FIFO and is then dropped. By having the RX threshold set to 128 the RX fifo is emptied faster. MFC after: 5 days
2003-01-31 07:37:06 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
status &= VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | VR_ISR_STATSOFLOW;
if ((status & VR_ISR_BUSERR) != 0) {
status &= ~VR_ISR_BUSERR;
sc->vr_stat.bus_errors++;
/* Disable further interrupts. */
CSR_WRITE_2(sc, VR_IMR, 0);
pcis = pci_read_config(sc->vr_dev, PCIR_STATUS, 2);
device_printf(sc->vr_dev, "PCI bus error(0x%04x) -- "
"resetting\n", pcis);
pci_write_config(sc->vr_dev, PCIR_STATUS, pcis, 2);
sc->vr_flags |= VR_F_RESTART;
return (EAGAIN);
}
if ((status & VR_ISR_LINKSTAT2) != 0) {
/* Link state change, duplex changes etc. */
status &= ~VR_ISR_LINKSTAT2;
}
if ((status & VR_ISR_STATSOFLOW) != 0) {
status &= ~VR_ISR_STATSOFLOW;
if (sc->vr_revid >= REV_ID_VT6105M_A0) {
/* Update MIB counters. */
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
}
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (status != 0)
device_printf(sc->vr_dev,
"unhandled interrupt, status = 0x%04x\n", status);
return (0);
}
/*
* Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
* pointers to the fragment pointers.
*/
static int
vr_encap(struct vr_softc *sc, struct mbuf **m_head)
{
struct vr_txdesc *txd;
struct vr_desc *desc;
struct mbuf *m;
bus_dma_segment_t txsegs[VR_MAXFRAGS];
uint32_t csum_flags, txctl;
int error, i, nsegs, prod, si;
int padlen;
VR_LOCK_ASSERT(sc);
M_ASSERTPKTHDR((*m_head));
/*
* Some VIA Rhine wants packet buffers to be longword
* aligned, but very often our mbufs aren't. Rather than
* waste time trying to decide when to copy and when not
* to copy, just do it all the time.
*/
if ((sc->vr_quirks & VR_Q_NEEDALIGN) != 0) {
Mechanically substitute flags from historic mbuf allocator with malloc(9) flags in sys/dev.
2012-12-04 09:32:43 +00:00
m = m_defrag(*m_head, M_NOWAIT);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (m == NULL) {
m_freem(*m_head);
*m_head = NULL;
return (ENOBUFS);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
*m_head = m;
}
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
/*
* The Rhine chip doesn't auto-pad, so we have to make
* sure to pad short frames out to the minimum frame length
* ourselves.
*/
if ((*m_head)->m_pkthdr.len < VR_MIN_FRAMELEN) {
m = *m_head;
padlen = VR_MIN_FRAMELEN - m->m_pkthdr.len;
if (M_WRITABLE(m) == 0) {
/* Get a writable copy. */
Mechanically substitute flags from historic mbuf allocator with malloc(9) flags in sys/dev.
2012-12-04 09:32:43 +00:00
m = m_dup(*m_head, M_NOWAIT);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
m_freem(*m_head);
if (m == NULL) {
*m_head = NULL;
return (ENOBUFS);
- Rewritten TX to use only two pointers to track producer/consumer. - Added polling(4) support! - Bugfix: don't forget to set IFF_OACTIVE when TX list is full. - Minor: tidy up vr_encap().
2004-04-05 17:39:57 +00:00
}
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
*m_head = m;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) {
Mechanically substitute flags from historic mbuf allocator with malloc(9) flags in sys/dev.
2012-12-04 09:32:43 +00:00
m = m_defrag(m, M_NOWAIT);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (m == NULL) {
m_freem(*m_head);
*m_head = NULL;
return (ENOBUFS);
}
}
/*
* Manually pad short frames, and zero the pad space
* to avoid leaking data.
*/
bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
m->m_pkthdr.len += padlen;
m->m_len = m->m_pkthdr.len;
*m_head = m;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
prod = sc->vr_cdata.vr_tx_prod;
txd = &sc->vr_cdata.vr_txdesc[prod];
error = bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap,
*m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
if (error == EFBIG) {
Mechanically substitute flags from historic mbuf allocator with malloc(9) flags in sys/dev.
2012-12-04 09:32:43 +00:00
m = m_collapse(*m_head, M_NOWAIT, VR_MAXFRAGS);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (m == NULL) {
m_freem(*m_head);
*m_head = NULL;
return (ENOBUFS);
}
*m_head = m;
error = bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_tx_tag,
txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
if (error != 0) {
m_freem(*m_head);
*m_head = NULL;
return (error);
}
} else if (error != 0)
return (error);
if (nsegs == 0) {
m_freem(*m_head);
*m_head = NULL;
return (EIO);
}
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
/* Check number of available descriptors. */
if (sc->vr_cdata.vr_tx_cnt + nsegs >= (VR_TX_RING_CNT - 1)) {
bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap);
return (ENOBUFS);
}
Further locking improvements for vr(4): - Add *_locked() entry points as needed to avoid unnecessary lock thrashing. - Use these entry points wisely. - Only acquire the lock once when servicing an interrupt. - Check 'suspended' on interrupt to avoid racing detach. - Correct a mis-spelled comment. - Don't take the lock in vr_reset() to avoid lock thrashing in attach. - Comment this. Reviewed by: -net (silence)
2004-07-09 00:17:14 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
txd->tx_m = *m_head;
bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap,
BUS_DMASYNC_PREWRITE);
/* Set checksum offload. */
csum_flags = 0;
if (((*m_head)->m_pkthdr.csum_flags & VR_CSUM_FEATURES) != 0) {
if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP)
csum_flags |= VR_TXCTL_IPCSUM;
if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP)
csum_flags |= VR_TXCTL_TCPCSUM;
if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP)
csum_flags |= VR_TXCTL_UDPCSUM;
}
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
/*
* Quite contrary to datasheet for VIA Rhine, VR_TXCTL_TLINK bit
* is required for all descriptors regardless of single or
* multiple buffers. Also VR_TXSTAT_OWN bit is valid only for
* the first descriptor for a multi-fragmented frames. Without
* that VIA Rhine chip generates Tx underrun interrupts and can't
* send any frames.
*/
si = prod;
for (i = 0; i < nsegs; i++) {
desc = &sc->vr_rdata.vr_tx_ring[prod];
desc->vr_status = 0;
txctl = txsegs[i].ds_len | VR_TXCTL_TLINK | csum_flags;
if (i == 0)
txctl |= VR_TXCTL_FIRSTFRAG;
desc->vr_ctl = htole32(txctl);
desc->vr_data = htole32(VR_ADDR_LO(txsegs[i].ds_addr));
sc->vr_cdata.vr_tx_cnt++;
VR_INC(prod, VR_TX_RING_CNT);
}
/* Update producer index. */
sc->vr_cdata.vr_tx_prod = prod;
prod = (prod + VR_TX_RING_CNT - 1) % VR_TX_RING_CNT;
desc = &sc->vr_rdata.vr_tx_ring[prod];
/*
* Set EOP on the last desciptor and reuqest Tx completion
* interrupt for every VR_TX_INTR_THRESH-th frames.
*/
VR_INC(sc->vr_cdata.vr_tx_pkts, VR_TX_INTR_THRESH);
if (sc->vr_cdata.vr_tx_pkts == 0)
desc->vr_ctl |= htole32(VR_TXCTL_LASTFRAG | VR_TXCTL_FINT);
else
desc->vr_ctl |= htole32(VR_TXCTL_LASTFRAG);
/* Lastly turn the first descriptor ownership to hardware. */
desc = &sc->vr_rdata.vr_tx_ring[si];
desc->vr_status |= htole32(VR_TXSTAT_OWN);
/* Sync descriptors. */
bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag,
sc->vr_cdata.vr_tx_ring_map,
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
return (0);
}
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
style: put return types on a line by themselves.
2002-08-24 00:02:03 +00:00
static void
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
vr_start(struct ifnet *ifp)
Further locking improvements for vr(4): - Add *_locked() entry points as needed to avoid unnecessary lock thrashing. - Use these entry points wisely. - Only acquire the lock once when servicing an interrupt. - Check 'suspended' on interrupt to avoid racing detach. - Correct a mis-spelled comment. - Don't take the lock in vr_reset() to avoid lock thrashing in attach. - Comment this. Reviewed by: -net (silence)
2004-07-09 00:17:14 +00:00
{
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
struct vr_softc *sc;
Further locking improvements for vr(4): - Add *_locked() entry points as needed to avoid unnecessary lock thrashing. - Use these entry points wisely. - Only acquire the lock once when servicing an interrupt. - Check 'suspended' on interrupt to avoid racing detach. - Correct a mis-spelled comment. - Don't take the lock in vr_reset() to avoid lock thrashing in attach. - Comment this. Reviewed by: -net (silence)
2004-07-09 00:17:14 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc = ifp->if_softc;
Further locking improvements for vr(4): - Add *_locked() entry points as needed to avoid unnecessary lock thrashing. - Use these entry points wisely. - Only acquire the lock once when servicing an interrupt. - Check 'suspended' on interrupt to avoid racing detach. - Correct a mis-spelled comment. - Don't take the lock in vr_reset() to avoid lock thrashing in attach. - Comment this. Reviewed by: -net (silence)
2004-07-09 00:17:14 +00:00
VR_LOCK(sc);
vr_start_locked(ifp);
VR_UNLOCK(sc);
}
static void
vr_start_locked(struct ifnet *ifp)
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
{
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
struct vr_softc *sc;
struct mbuf *m_head;
int enq;
sc = ifp->if_softc;
- Rewritten TX to use only two pointers to track producer/consumer. - Added polling(4) support! - Bugfix: don't forget to set IFF_OACTIVE when TX list is full. - Minor: tidy up vr_encap().
2004-04-05 17:39:57 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
VR_LOCK_ASSERT(sc);
if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
Reuse flag variable to represent driver internal states rather than using member variables in softc. While I'm here change media after setting IFF_DRV_RUNNING. This will remove unnecessary link state handling in vr_tick() if controller established a link immediately.
2011-11-28 18:32:35 +00:00
IFF_DRV_RUNNING || (sc->vr_flags & VR_F_LINK) == 0)
- Rewritten TX to use only two pointers to track producer/consumer. - Added polling(4) support! - Bugfix: don't forget to set IFF_OACTIVE when TX list is full. - Minor: tidy up vr_encap().
2004-04-05 17:39:57 +00:00
return;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
sc->vr_cdata.vr_tx_cnt < VR_TX_RING_CNT - 2; ) {
IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
if (m_head == NULL)
break;
Improve the if_vr driver ever so slightly. The 6105M and 6102 does not have the DWORD alignment problem, so don't m_defrag() every packet in the transmit path for those. More stringent usage of tx-descriptor ring and its flags. Tested on 6102 and 6105M, other chips may also be able to run without the m_defrag() but I have neither hardware nor docs to find out. Sponsored by: Soekris Engineering
2007-04-17 12:23:57 +00:00
/*
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
* Pack the data into the transmit ring. If we
* don't have room, set the OACTIVE flag and wait
* for the NIC to drain the ring.
Improve the if_vr driver ever so slightly. The 6105M and 6102 does not have the DWORD alignment problem, so don't m_defrag() every packet in the transmit path for those. More stringent usage of tx-descriptor ring and its flags. Tested on 6102 and 6105M, other chips may also be able to run without the m_defrag() but I have neither hardware nor docs to find out. Sponsored by: Soekris Engineering
2007-04-17 12:23:57 +00:00
*/
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (vr_encap(sc, &m_head)) {
if (m_head == NULL)
Improve the if_vr driver ever so slightly. The 6105M and 6102 does not have the DWORD alignment problem, so don't m_defrag() every packet in the transmit path for those. More stringent usage of tx-descriptor ring and its flags. Tested on 6102 and 6105M, other chips may also be able to run without the m_defrag() but I have neither hardware nor docs to find out. Sponsored by: Soekris Engineering
2007-04-17 12:23:57 +00:00
break;
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
ifp->if_drv_flags |= IFF_DRV_OACTIVE;
break;
Improve the if_vr driver ever so slightly. The 6105M and 6102 does not have the DWORD alignment problem, so don't m_defrag() every packet in the transmit path for those. More stringent usage of tx-descriptor ring and its flags. Tested on 6102 and 6105M, other chips may also be able to run without the m_defrag() but I have neither hardware nor docs to find out. Sponsored by: Soekris Engineering
2007-04-17 12:23:57 +00:00
}
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
enq++;
Improve the if_vr driver ever so slightly. The 6105M and 6102 does not have the DWORD alignment problem, so don't m_defrag() every packet in the transmit path for those. More stringent usage of tx-descriptor ring and its flags. Tested on 6102 and 6105M, other chips may also be able to run without the m_defrag() but I have neither hardware nor docs to find out. Sponsored by: Soekris Engineering
2007-04-17 12:23:57 +00:00
/*
* If there's a BPF listener, bounce a copy of this frame
* to him.
*/
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
ETHER_BPF_MTAP(ifp, m_head);
}
if (enq > 0) {
/* Tell the chip to start transmitting. */
VR_SETBIT(sc, VR_CR0, VR_CR0_TX_GO);
/* Set a timeout in case the chip goes out to lunch. */
sc->vr_watchdog_timer = 5;
- Rewritten TX to use only two pointers to track producer/consumer. - Added polling(4) support! - Bugfix: don't forget to set IFF_OACTIVE when TX list is full. - Minor: tidy up vr_encap().
2004-04-05 17:39:57 +00:00
}
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
style: put return types on a line by themselves.
2002-08-24 00:02:03 +00:00
static void
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
vr_init(void *xsc)
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
{
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
struct vr_softc *sc;
Further locking improvements for vr(4): - Add *_locked() entry points as needed to avoid unnecessary lock thrashing. - Use these entry points wisely. - Only acquire the lock once when servicing an interrupt. - Check 'suspended' on interrupt to avoid racing detach. - Correct a mis-spelled comment. - Don't take the lock in vr_reset() to avoid lock thrashing in attach. - Comment this. Reviewed by: -net (silence)
2004-07-09 00:17:14 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc = (struct vr_softc *)xsc;
Further locking improvements for vr(4): - Add *_locked() entry points as needed to avoid unnecessary lock thrashing. - Use these entry points wisely. - Only acquire the lock once when servicing an interrupt. - Check 'suspended' on interrupt to avoid racing detach. - Correct a mis-spelled comment. - Don't take the lock in vr_reset() to avoid lock thrashing in attach. - Comment this. Reviewed by: -net (silence)
2004-07-09 00:17:14 +00:00
VR_LOCK(sc);
vr_init_locked(sc);
VR_UNLOCK(sc);
}
static void
vr_init_locked(struct vr_softc *sc)
{
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
struct ifnet *ifp;
Convert the VIA Rhine driver to miibus.
1999-09-19 22:03:31 +00:00
struct mii_data *mii;
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
bus_addr_t addr;
Remember to actually program the MAC address into the unicast filter in vr_init(). The VIA Rhine chip happens to be able to automatically read its station address from the EEPROM automatically when reset, so you don't need to program the filter if you want to keep using the factory default address, but if you want to change it with "ifconfig vr0 ether xx:xx:xx:xx:xx:xx" then we need to manually set it in the init routine.
2001-03-07 18:52:22 +00:00
int i;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Further locking improvements for vr(4): - Add *_locked() entry points as needed to avoid unnecessary lock thrashing. - Use these entry points wisely. - Only acquire the lock once when servicing an interrupt. - Check 'suspended' on interrupt to avoid racing detach. - Correct a mis-spelled comment. - Don't take the lock in vr_reset() to avoid lock thrashing in attach. - Comment this. Reviewed by: -net (silence)
2004-07-09 00:17:14 +00:00
VR_LOCK_ASSERT(sc);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
ifp = sc->vr_ifp;
Convert the VIA Rhine driver to miibus.
1999-09-19 22:03:31 +00:00
mii = device_get_softc(sc->vr_miibus);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Remove unnecessary controller reinitialization. CAM filter handling was rewritten long time ago so it should not require controller reinitialization. PR: kern/87506
2010-08-24 18:40:11 +00:00
if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
return;
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
/* Cancel pending I/O and free all RX/TX buffers. */
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
vr_stop(sc);
vr_reset(sc);
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
/* Set our station address. */
Remember to actually program the MAC address into the unicast filter in vr_init(). The VIA Rhine chip happens to be able to automatically read its station address from the EEPROM automatically when reset, so you don't need to program the filter if you want to keep using the factory default address, but if you want to change it with "ifconfig vr0 ether xx:xx:xx:xx:xx:xx" then we need to manually set it in the init routine.
2001-03-07 18:52:22 +00:00
for (i = 0; i < ETHER_ADDR_LEN; i++)
- Store pointer to the link-level address right in "struct ifnet" rather than in ifindex_table[]; all (except one) accesses are through ifp anyway. IF_LLADDR() works faster, and all (except one) ifaddr_byindex() users were converted to use ifp->if_addr. - Stop storing a (pointer to) Ethernet address in "struct arpcom", and drop the IFP2ENADDR() macro; all users have been converted to use IF_LLADDR() instead.
2005-11-11 16:04:59 +00:00
CSR_WRITE_1(sc, VR_PAR0 + i, IF_LLADDR(sc->vr_ifp)[i]);
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
/* Set DMA size. */
Make sure to set the DMA transfer length register, plus one small style fix. Submitted by: Thomas Nystrom <thn@saeab.se>
2002-08-05 13:24:06 +00:00
VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH);
VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD);
Remember to actually program the MAC address into the unicast filter in vr_init(). The VIA Rhine chip happens to be able to automatically read its station address from the EEPROM automatically when reset, so you don't need to program the filter if you want to keep using the factory default address, but if you want to change it with "ifconfig vr0 ether xx:xx:xx:xx:xx:xx" then we need to manually set it in the init routine.
2001-03-07 18:52:22 +00:00
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
/*
Make sure to set the DMA transfer length register, plus one small style fix. Submitted by: Thomas Nystrom <thn@saeab.se>
2002-08-05 13:24:06 +00:00
* BCR0 and BCR1 can override the RXCFG and TXCFG registers,
Make sure to set both sets of registers which control the RX and TX buffer sizes. Previously, the end result was at the mercy of the card's default setting. This change will reduce the number of buffer underruns for some users. PR: kern/37929 Submitted by: Thomas Nystrom <thn@saeab.se> MFC after: 7 days
2002-07-31 19:58:36 +00:00
* so we must set both.
*/
VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH);
Fixes from Thomas Nystrom to fix hanging problems experienced by vr cards under load. This patch has been tested by Thomas and other for more than a month now, and all (known) hangs seem to be solved. Thomas's explanation of the patch: * Fix the problem with the printing of the RX-error. * Code from if_fet do better deal with the RX-recovery including a timeout of the RX-turnoff. * The call to vr_rxeof before vr_rxeoc have been moved to a point where the RX-part of the chip is turned off. Otherwise there is a window where new data could have been written to the buffer chain before the RX-part is turned off. If this happens the chip will see a busy rx-buffer. I have no evidence that this have occured but god knows what the chip will do in this case! * I have added a timeout of the TX-turnoff. I have checked and in my 900 MHz system the flags for turnoff (both RX & TX) is seen at the first check in the loop. * I could see that I got the VR_ISR_DROPPED interrupt sometimes and started to thinking about this. I then realized that no recovery is needed for this case and therefore I only count it as an rxerror (which was not done before). * Finally I have changed the FIFO RX threshhold to 128 bytes. When I did this the VR_ISR_DROPPED interrupt went away. Theory: The chip will receive a complete frame before it tries to write it out to memory then the RX threshold is set to store'n'forward. IF the frame is large AND the next rx frame also is large AND the bus is busy transfering a TX frame to the TX fifo THEN the second received frame wont fit in the FIFO and is then dropped. By having the RX threshold set to 128 the RX fifo is emptied faster. MFC after: 5 days
2003-01-31 07:37:06 +00:00
VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES);
Make sure to set both sets of registers which control the RX and TX buffer sizes. Previously, the end result was at the mercy of the card's default setting. This change will reduce the number of buffer underruns for some users. PR: kern/37929 Submitted by: Thomas Nystrom <thn@saeab.se> MFC after: 7 days
2002-07-31 19:58:36 +00:00
VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
VR_SETBIT(sc, VR_BCR1, vr_tx_threshold_tables[sc->vr_txthresh].bcr_cfg);
Make sure to set both sets of registers which control the RX and TX buffer sizes. Previously, the end result was at the mercy of the card's default setting. This change will reduce the number of buffer underruns for some users. PR: kern/37929 Submitted by: Thomas Nystrom <thn@saeab.se> MFC after: 7 days
2002-07-31 19:58:36 +00:00
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH);
Fixes from Thomas Nystrom to fix hanging problems experienced by vr cards under load. This patch has been tested by Thomas and other for more than a month now, and all (known) hangs seem to be solved. Thomas's explanation of the patch: * Fix the problem with the printing of the RX-error. * Code from if_fet do better deal with the RX-recovery including a timeout of the RX-turnoff. * The call to vr_rxeof before vr_rxeoc have been moved to a point where the RX-part of the chip is turned off. Otherwise there is a window where new data could have been written to the buffer chain before the RX-part is turned off. If this happens the chip will see a busy rx-buffer. I have no evidence that this have occured but god knows what the chip will do in this case! * I have added a timeout of the TX-turnoff. I have checked and in my 900 MHz system the flags for turnoff (both RX & TX) is seen at the first check in the loop. * I could see that I got the VR_ISR_DROPPED interrupt sometimes and started to thinking about this. I then realized that no recovery is needed for this case and therefore I only count it as an rxerror (which was not done before). * Finally I have changed the FIFO RX threshhold to 128 bytes. When I did this the VR_ISR_DROPPED interrupt went away. Theory: The chip will receive a complete frame before it tries to write it out to memory then the RX threshold is set to store'n'forward. IF the frame is large AND the next rx frame also is large AND the bus is busy transfering a TX frame to the TX fifo THEN the second received frame wont fit in the FIFO and is then dropped. By having the RX threshold set to 128 the RX fifo is emptied faster. MFC after: 5 days
2003-01-31 07:37:06 +00:00
VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
VR_SETBIT(sc, VR_TXCFG, vr_tx_threshold_tables[sc->vr_txthresh].tx_cfg);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
/* Init circular RX list. */
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (vr_rx_ring_init(sc) != 0) {
Consistently use if_printf() only in interface methods: if_start, if_ioctl, if_watchdog, etc, or in functions that are used by these methods only. In all other cases use device_printf(). This also fixes several panics, when if_printf() is called before softc->ifp was initialized. Submitted by: Alex Lyashkov <umka sevcity.net>
2006-09-15 10:40:54 +00:00
device_printf(sc->vr_dev,
- Use if_printf() and device_printf() and remove vr_unit from the softc. I had to initialize the ifnet a bit earlier in attach so that the if_printf()'s in vr_reset() didn't explode with a page fault. - Use M_ZERO with contigmalloc() rather than an explicit bzero.
2005-10-27 21:18:37 +00:00
"initialization failed: no memory for rx buffers\n");
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
vr_stop(sc);
return;
}
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
/* Init tx descriptors. */
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
vr_tx_ring_init(sc);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if ((sc->vr_quirks & VR_Q_CAM) != 0) {
Fix a multicast handling regression on VT6105M introduced in vr(4) overhauling(r177050). It seems that filtering multicast addresses with multicast CAM entries require accessing 'CAM enable bit' for each CAM entry. Subsequent accessing multicast CAM control register without toggling the 'CAM enable bit' seem to no effects. In order to fix that separate CAM setup from CAM mask configuration and CAM entry modification. While I'm here add VLAN CAM filtering feature which will be enabled in future(FreeBSD now can receive VLAN id insertion/removal event from vlan(4) on the fly). For VT6105M hardware, explicitly disable VLAN hardware tag insertion/stripping and enable VLAN CAM filtering for VLAN id 0. This shall make non-VLAN frames set VR_RXSTAT_VIDHIT bit in Rx status word. Added multicast/VLAN CAM address definition to header file. PR: kern/125010, kern/125024 MFC after: 1 week
2008-07-16 08:35:29 +00:00
uint8_t vcam[2] = { 0, 0 };
/* Disable VLAN hardware tag insertion/stripping. */
VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TXTAGEN | VR_TXCFG_RXTAGCTL);
/* Disable VLAN hardware filtering. */
VR_CLRBIT(sc, VR_BCR1, VR_BCR1_VLANFILT_ENB);
/* Disable all CAM entries. */
vr_cam_mask(sc, VR_MCAST_CAM, 0);
vr_cam_mask(sc, VR_VLAN_CAM, 0);
/* Enable the first VLAN CAM. */
vr_cam_data(sc, VR_VLAN_CAM, 0, vcam);
vr_cam_mask(sc, VR_VLAN_CAM, 1);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
}
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
/*
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
* Set up receive filter.
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
*/
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
vr_set_filter(sc);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
/*
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
* Load the address of the RX ring.
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
*/
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
addr = VR_RX_RING_ADDR(sc, 0);
CSR_WRITE_4(sc, VR_RXADDR, VR_ADDR_LO(addr));
/*
* Load the address of the TX ring.
*/
addr = VR_TX_RING_ADDR(sc, 0);
CSR_WRITE_4(sc, VR_TXADDR, VR_ADDR_LO(addr));
/* Default : full-duplex, no Tx poll. */
CSR_WRITE_1(sc, VR_CR1, VR_CR1_FULLDUPLEX | VR_CR1_TX_NOPOLL);
/* Set flow-control parameters for Rhine III. */
if (sc->vr_revid >= REV_ID_VT6105_A0) {
/*
Announce flow control capability to PHY drivers and enable flow control for all vr(4) controllers that support it. It's known that old vr(4) controllers(Rhine II) does not support TX pause but Rhine III supports both TX and RX pause. Make TX pause really work on Rhine III by letting controller know available RX buffers. While here, adjust XON/XOFF parameters to get better performance with flow control.
2011-11-28 19:03:59 +00:00
* Configure Rx buffer count available for incoming
* packet.
* Even though data sheet says almost nothing about
* this register, this register should be updated
* whenever driver adds new RX buffers to controller.
* Otherwise, XON frame is not sent to link partner
* even if controller has enough RX buffers and you
* would be isolated from network.
* The controller is not smart enough to know number
* of available RX buffers so driver have to let
* controller know how many RX buffers are posted.
* In other words, this register works like a residue
* counter for RX buffers and should be initialized
* to the number of total RX buffers - 1 before
* enabling RX MAC. Note, this register is 8bits so
* it effectively limits the maximum number of RX
* buffer to be configured by controller is 255.
*/
CSR_WRITE_1(sc, VR_FLOWCR0, VR_RX_RING_CNT - 1);
/*
* Tx pause low threshold : 8 free receive buffers
* Tx pause XON high threshold : 24 free receive buffers
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
*/
CSR_WRITE_1(sc, VR_FLOWCR1,
Announce flow control capability to PHY drivers and enable flow control for all vr(4) controllers that support it. It's known that old vr(4) controllers(Rhine II) does not support TX pause but Rhine III supports both TX and RX pause. Make TX pause really work on Rhine III by letting controller know available RX buffers. While here, adjust XON/XOFF parameters to get better performance with flow control.
2011-11-28 19:03:59 +00:00
VR_FLOWCR1_TXLO8 | VR_FLOWCR1_TXHI24 | VR_FLOWCR1_XONXOFF);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
/* Set Tx pause timer. */
CSR_WRITE_2(sc, VR_PAUSETIMER, 0xffff);
}
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
/* Enable receiver and transmitter. */
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
CSR_WRITE_1(sc, VR_CR0,
VR_CR0_START | VR_CR0_TX_ON | VR_CR0_RX_ON | VR_CR0_RX_GO);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
- Rewritten TX to use only two pointers to track producer/consumer. - Added polling(4) support! - Bugfix: don't forget to set IFF_OACTIVE when TX list is full. - Minor: tidy up vr_encap().
2004-04-05 17:39:57 +00:00
CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
#ifdef DEVICE_POLLING
/*
* Disable interrupts if we are polling.
*/
Big polling(4) cleanup. o Axe poll in trap. o Axe IFF_POLLING flag from if_flags. o Rework revision 1.21 (Giant removal), in such a way that poll_mtx is not dropped during call to polling handler. This fixes problem with idle polling. o Make registration and deregistration from polling in a functional way, insted of next tick/interrupt. o Obsolete kern.polling.enable. Polling is turned on/off with ifconfig. Detailed kern_poll.c changes: - Remove polling handler flags, introduced in 1.21. The are not needed now. - Forget and do not check if_flags, if_capenable and if_drv_flags. - Call all registered polling handlers unconditionally. - Do not drop poll_mtx, when entering polling handlers. - In ether_poll() NET_LOCK_GIANT prior to locking poll_mtx. - In netisr_poll() axe the block, where polling code asks drivers to unregister. - In netisr_poll() and ether_poll() do polling always, if any handlers are present. - In ether_poll_[de]register() remove a lot of error hiding code. Assert that arguments are correct, instead. - In ether_poll_[de]register() use standard return values in case of error or success. - Introduce poll_switch() that is a sysctl handler for kern.polling.enable. poll_switch() goes through interface list and enabled/disables polling. A message that kern.polling.enable is deprecated is printed. Detailed driver changes: - On attach driver announces IFCAP_POLLING in if_capabilities, but not in if_capenable. - On detach driver calls ether_poll_deregister() if polling is enabled. - In polling handler driver obtains its lock and checks IFF_DRV_RUNNING flag. If there is no, then unlocks and returns. - In ioctl handler driver checks for IFCAP_POLLING flag requested to be set or cleared. Driver first calls ether_poll_[de]register(), then obtains driver lock and [dis/en]ables interrupts. - In interrupt handler driver checks IFCAP_POLLING flag in if_capenable. If present, then returns.This is important to protect from spurious interrupts. Reviewed by: ru, sam, jhb
2005-10-01 18:56:19 +00:00
if (ifp->if_capenable & IFCAP_POLLING)
- Rewritten TX to use only two pointers to track producer/consumer. - Added polling(4) support! - Bugfix: don't forget to set IFF_OACTIVE when TX list is full. - Minor: tidy up vr_encap().
2004-04-05 17:39:57 +00:00
CSR_WRITE_2(sc, VR_IMR, 0);
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
else
Big polling(4) cleanup. o Axe poll in trap. o Axe IFF_POLLING flag from if_flags. o Rework revision 1.21 (Giant removal), in such a way that poll_mtx is not dropped during call to polling handler. This fixes problem with idle polling. o Make registration and deregistration from polling in a functional way, insted of next tick/interrupt. o Obsolete kern.polling.enable. Polling is turned on/off with ifconfig. Detailed kern_poll.c changes: - Remove polling handler flags, introduced in 1.21. The are not needed now. - Forget and do not check if_flags, if_capenable and if_drv_flags. - Call all registered polling handlers unconditionally. - Do not drop poll_mtx, when entering polling handlers. - In ether_poll() NET_LOCK_GIANT prior to locking poll_mtx. - In netisr_poll() axe the block, where polling code asks drivers to unregister. - In netisr_poll() and ether_poll() do polling always, if any handlers are present. - In ether_poll_[de]register() remove a lot of error hiding code. Assert that arguments are correct, instead. - In ether_poll_[de]register() use standard return values in case of error or success. - Introduce poll_switch() that is a sysctl handler for kern.polling.enable. poll_switch() goes through interface list and enabled/disables polling. A message that kern.polling.enable is deprecated is printed. Detailed driver changes: - On attach driver announces IFCAP_POLLING in if_capabilities, but not in if_capenable. - On detach driver calls ether_poll_deregister() if polling is enabled. - In polling handler driver obtains its lock and checks IFF_DRV_RUNNING flag. If there is no, then unlocks and returns. - In ioctl handler driver checks for IFCAP_POLLING flag requested to be set or cleared. Driver first calls ether_poll_[de]register(), then obtains driver lock and [dis/en]ables interrupts. - In interrupt handler driver checks IFCAP_POLLING flag in if_capenable. If present, then returns.This is important to protect from spurious interrupts. Reviewed by: ru, sam, jhb
2005-10-01 18:56:19 +00:00
#endif
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
/*
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
* Enable interrupts and disable MII intrs.
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
*/
CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (sc->vr_revid > REV_ID_VT6102_A)
CSR_WRITE_2(sc, VR_MII_IMR, 0);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Propagate rename of IFF_OACTIVE and IFF_RUNNING to IFF_DRV_OACTIVE and IFF_DRV_RUNNING, as well as the move from ifnet.if_flags to ifnet.if_drv_flags. Device drivers are now responsible for synchronizing access to these flags, as they are in if_drv_flags. This helps prevent races between the network stack and device driver in maintaining the interface flags field. Many __FreeBSD__ and __FreeBSD_version checks maintained and continued; some less so. Reviewed by: pjd, bz MFC after: 7 days
2005-08-09 10:20:02 +00:00
ifp->if_drv_flags |= IFF_DRV_RUNNING;
ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Announce flow control capability to PHY drivers and enable flow control for all vr(4) controllers that support it. It's known that old vr(4) controllers(Rhine II) does not support TX pause but Rhine III supports both TX and RX pause. Make TX pause really work on Rhine III by letting controller know available RX buffers. While here, adjust XON/XOFF parameters to get better performance with flow control.
2011-11-28 19:03:59 +00:00
sc->vr_flags &= ~(VR_F_LINK | VR_F_TXPAUSE);
Reuse flag variable to represent driver internal states rather than using member variables in softc. While I'm here change media after setting IFF_DRV_RUNNING. This will remove unnecessary link state handling in vr_tick() if controller established a link immediately.
2011-11-28 18:32:35 +00:00
mii_mediachg(mii);
- Use callout_*() to manage the callout and make it MPSAFE. - Fix locking in detach(), we only need to lock across vr_stop(). Tested by: Mike Tancsa mike at sentex dot net MFC after: 1 week
2005-10-31 21:37:27 +00:00
callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
/*
* Set media options.
*/
style: put return types on a line by themselves.
2002-08-24 00:02:03 +00:00
static int
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
vr_ifmedia_upd(struct ifnet *ifp)
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
{
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
struct vr_softc *sc;
struct mii_data *mii;
struct mii_softc *miisc;
int error;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc = ifp->if_softc;
VR_LOCK(sc);
mii = device_get_softc(sc->vr_miibus);
- Remove attempts to implement setting of BMCR_LOOP/MIIF_NOLOOP (reporting IFM_LOOP based on BMCR_LOOP is left in place though as it might provide useful for debugging). For most mii(4) drivers it was unclear whether the PHYs driven by them actually support loopback or not. Moreover, typically loopback mode also needs to be activated on the MAC, which none of the Ethernet drivers using mii(4) implements. Given that loopback media has no real use (and obviously hardly had a chance to actually work) besides for driver development (which just loopback mode should be sufficient for though, i.e one doesn't necessary need support for loopback media) support for it is just dropped as both NetBSD and OpenBSD already did quite some time ago. - Let mii_phy_add_media() also announce the support of IFM_NONE. - Restructure the PHY entry points to use a structure of entry points instead of discrete function pointers, and extend this to include a "reset" entry point. Make sure any PHY-specific reset routine is always used, and provide one for lxtphy(4) which disables MII interrupts (as is done for a few other PHYs we have drivers for). This includes changing NIC drivers which previously just called the generic mii_phy_reset() to now actually call the PHY-specific reset routine, which might be crucial in some cases. While at it, the redundant checks in these NIC drivers for mii->mii_instance not being zero before calling the reset routines were removed because as soon as one PHY driver attaches mii->mii_instance is incremented and we hardly can end up in their media change callbacks etc if no PHY driver has attached as mii_attach() would have failed in that case and not attach a miibus(4) instance. Consequently, NIC drivers now no longer should call mii_phy_reset() directly, so it was removed from EXPORT_SYMS. - Add a mii_phy_dev_attach() as a companion helper to mii_phy_dev_probe(). The purpose of that function is to perform the common steps to attach a PHY driver instance and to hook it up to the miibus(4) instance and to optionally also handle the probing, addition and initialization of the supported media. So all a PHY driver without any special requirements has to do in its bus attach method is to call mii_phy_dev_attach() along with PHY-specific MIIF_* flags, a pointer to its PHY functions and the add_media set to one. All PHY drivers were updated to take advantage of mii_phy_dev_attach() as appropriate. Along with these changes the capability mask was added to the mii_softc structure so PHY drivers taking advantage of mii_phy_dev_attach() but still handling media on their own do not need to fiddle with the MII attach arguments anyway. - Keep track of the PHY offset in the mii_softc structure. This is done for compatibility with NetBSD/OpenBSD. - Keep track of the PHY's OUI, model and revision in the mii_softc structure. Several PHY drivers require this information also after attaching and previously had to wrap their own softc around mii_softc. NetBSD/OpenBSD also keep track of the model and revision on their mii_softc structure. All PHY drivers were updated to take advantage as appropriate. - Convert the mebers of the MII data structure to unsigned where appropriate. This is partly inspired by NetBSD/OpenBSD. - According to IEEE 802.3-2002 the bits actually have to be reversed when mapping an OUI to the MII ID registers. All PHY drivers and miidevs where changed as necessary. Actually this now again allows to largely share miidevs with NetBSD, which fixed this problem already 9 years ago. Consequently miidevs was synced as far as possible. - Add MIIF_NOMANPAUSE and mii_phy_flowstatus() calls to drivers that weren't explicitly converted to support flow control before. It's unclear whether flow control actually works with these but typically it should and their net behavior should be more correct with these changes in place than without if the MAC driver sets MIIF_DOPAUSE. Obtained from: NetBSD (partially) Reviewed by: yongari (earlier version), silence on arch@ and net@
2011-05-03 19:51:29 +00:00
LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
PHY_RESET(miisc);
Announce flow control capability to PHY drivers and enable flow control for all vr(4) controllers that support it. It's known that old vr(4) controllers(Rhine II) does not support TX pause but Rhine III supports both TX and RX pause. Make TX pause really work on Rhine III by letting controller know available RX buffers. While here, adjust XON/XOFF parameters to get better performance with flow control.
2011-11-28 19:03:59 +00:00
sc->vr_flags &= ~(VR_F_LINK | VR_F_TXPAUSE);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
error = mii_mediachg(mii);
VR_UNLOCK(sc);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
return (error);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
/*
* Report current media status.
*/
style: put return types on a line by themselves.
2002-08-24 00:02:03 +00:00
static void
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
{
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
struct vr_softc *sc;
Convert the VIA Rhine driver to miibus.
1999-09-19 22:03:31 +00:00
struct mii_data *mii;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc = ifp->if_softc;
Convert the VIA Rhine driver to miibus.
1999-09-19 22:03:31 +00:00
mii = device_get_softc(sc->vr_miibus);
Revert rev 1.93 and replace it by grabbing the vr lock before calling mii_pollstat(). The previous was causing the vr lock to recurse. PR: kern/70189
2004-08-11 04:30:49 +00:00
VR_LOCK(sc);
Remove link state change callback handler. There is no need to register both status change and link state change callbacks. Implement checking valid link in state change callback and poll active link state in vr_tick(). This allows immediate detection of lost link as well as protecting driver from frequent link flips during link renegotiation. taskq implementation was removed because driver now needs to poll link state in vr_tick(). While I'm here do not report current link state if interface is not running. Tested by: n_hibma MFC after: 1 week
2011-06-22 02:18:45 +00:00
if ((ifp->if_flags & IFF_UP) == 0) {
VR_UNLOCK(sc);
return;
}
Convert the VIA Rhine driver to miibus.
1999-09-19 22:03:31 +00:00
mii_pollstat(mii);
ifmr->ifm_active = mii->mii_media_active;
ifmr->ifm_status = mii->mii_media_status;
Close a race where SIOCGIFMEDIA ioctl get inconsistent link status. Because driver is accessing a common MII structure in mii_pollstat(), updating user supplied structure should be done before dropping a driver lock. Reported by: Karim (fodillemlinkarimi <> gmail dot com)
2011-10-17 19:49:00 +00:00
VR_UNLOCK(sc);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
style: put return types on a line by themselves.
2002-08-24 00:02:03 +00:00
static int
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
{
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
struct vr_softc *sc;
struct ifreq *ifr;
Convert the VIA Rhine driver to miibus.
1999-09-19 22:03:31 +00:00
struct mii_data *mii;
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
int error, mask;
sc = ifp->if_softc;
ifr = (struct ifreq *)data;
error = 0;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
switch (command) {
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
case SIOCSIFFLAGS:
Further locking improvements for vr(4): - Add *_locked() entry points as needed to avoid unnecessary lock thrashing. - Use these entry points wisely. - Only acquire the lock once when servicing an interrupt. - Check 'suspended' on interrupt to avoid racing detach. - Correct a mis-spelled comment. - Don't take the lock in vr_reset() to avoid lock thrashing in attach. - Comment this. Reviewed by: -net (silence)
2004-07-09 00:17:14 +00:00
VR_LOCK(sc);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
if (ifp->if_flags & IFF_UP) {
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
if ((ifp->if_flags ^ sc->vr_if_flags) &
(IFF_PROMISC | IFF_ALLMULTI))
vr_set_filter(sc);
} else {
Reuse flag variable to represent driver internal states rather than using member variables in softc. While I'm here change media after setting IFF_DRV_RUNNING. This will remove unnecessary link state handling in vr_tick() if controller established a link immediately.
2011-11-28 18:32:35 +00:00
if ((sc->vr_flags & VR_F_DETACHED) == 0)
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
vr_init_locked(sc);
}
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
} else {
Propagate rename of IFF_OACTIVE and IFF_RUNNING to IFF_DRV_OACTIVE and IFF_DRV_RUNNING, as well as the move from ifnet.if_flags to ifnet.if_drv_flags. Device drivers are now responsible for synchronizing access to these flags, as they are in if_drv_flags. This helps prevent races between the network stack and device driver in maintaining the interface flags field. Many __FreeBSD__ and __FreeBSD_version checks maintained and continued; some less so. Reviewed by: pjd, bz MFC after: 7 days
2005-08-09 10:20:02 +00:00
if (ifp->if_drv_flags & IFF_DRV_RUNNING)
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
vr_stop(sc);
}
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc->vr_if_flags = ifp->if_flags;
Further locking improvements for vr(4): - Add *_locked() entry points as needed to avoid unnecessary lock thrashing. - Use these entry points wisely. - Only acquire the lock once when servicing an interrupt. - Check 'suspended' on interrupt to avoid racing detach. - Correct a mis-spelled comment. - Don't take the lock in vr_reset() to avoid lock thrashing in attach. - Comment this. Reviewed by: -net (silence)
2004-07-09 00:17:14 +00:00
VR_UNLOCK(sc);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
break;
case SIOCADDMULTI:
case SIOCDELMULTI:
SMPng locking cleanup for vr(4). - Remove recursive locking situations. Remove the MTX_RECURSE bit. - Take the lock for any routine which is not called from within if_vr.c itself; this includes entry points called by newbus, ifnet, callout, ifmedia, and polling subsystems. - Remove spl references from the code added to miibus callbacks in rev 1.60. - Add the INTR_MPSAFE bit. - Tidy up some assignments; locks are not needed for taking the address of something at a known offset, for example. - Tested on the machine this was committed from. Tested on: UP only, !debug.mpsafenet && debug.mpsafenet Reviewed by: rwatson
2004-07-03 02:59:02 +00:00
VR_LOCK(sc);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
vr_set_filter(sc);
SMPng locking cleanup for vr(4). - Remove recursive locking situations. Remove the MTX_RECURSE bit. - Take the lock for any routine which is not called from within if_vr.c itself; this includes entry points called by newbus, ifnet, callout, ifmedia, and polling subsystems. - Remove spl references from the code added to miibus callbacks in rev 1.60. - Add the INTR_MPSAFE bit. - Tidy up some assignments; locks are not needed for taking the address of something at a known offset, for example. - Tested on the machine this was committed from. Tested on: UP only, !debug.mpsafenet && debug.mpsafenet Reviewed by: rwatson
2004-07-03 02:59:02 +00:00
VR_UNLOCK(sc);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
break;
case SIOCGIFMEDIA:
case SIOCSIFMEDIA:
Convert the VIA Rhine driver to miibus.
1999-09-19 22:03:31 +00:00
mii = device_get_softc(sc->vr_miibus);
error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
break;
Implemented per-interface polling(4) control.
2004-04-11 15:18:09 +00:00
case SIOCSIFCAP:
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
mask = ifr->ifr_reqcap ^ ifp->if_capenable;
Big polling(4) cleanup. o Axe poll in trap. o Axe IFF_POLLING flag from if_flags. o Rework revision 1.21 (Giant removal), in such a way that poll_mtx is not dropped during call to polling handler. This fixes problem with idle polling. o Make registration and deregistration from polling in a functional way, insted of next tick/interrupt. o Obsolete kern.polling.enable. Polling is turned on/off with ifconfig. Detailed kern_poll.c changes: - Remove polling handler flags, introduced in 1.21. The are not needed now. - Forget and do not check if_flags, if_capenable and if_drv_flags. - Call all registered polling handlers unconditionally. - Do not drop poll_mtx, when entering polling handlers. - In ether_poll() NET_LOCK_GIANT prior to locking poll_mtx. - In netisr_poll() axe the block, where polling code asks drivers to unregister. - In netisr_poll() and ether_poll() do polling always, if any handlers are present. - In ether_poll_[de]register() remove a lot of error hiding code. Assert that arguments are correct, instead. - In ether_poll_[de]register() use standard return values in case of error or success. - Introduce poll_switch() that is a sysctl handler for kern.polling.enable. poll_switch() goes through interface list and enabled/disables polling. A message that kern.polling.enable is deprecated is printed. Detailed driver changes: - On attach driver announces IFCAP_POLLING in if_capabilities, but not in if_capenable. - On detach driver calls ether_poll_deregister() if polling is enabled. - In polling handler driver obtains its lock and checks IFF_DRV_RUNNING flag. If there is no, then unlocks and returns. - In ioctl handler driver checks for IFCAP_POLLING flag requested to be set or cleared. Driver first calls ether_poll_[de]register(), then obtains driver lock and [dis/en]ables interrupts. - In interrupt handler driver checks IFCAP_POLLING flag in if_capenable. If present, then returns.This is important to protect from spurious interrupts. Reviewed by: ru, sam, jhb
2005-10-01 18:56:19 +00:00
#ifdef DEVICE_POLLING
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (mask & IFCAP_POLLING) {
if (ifr->ifr_reqcap & IFCAP_POLLING) {
error = ether_poll_register(vr_poll, ifp);
if (error != 0)
break;
VR_LOCK(sc);
/* Disable interrupts. */
CSR_WRITE_2(sc, VR_IMR, 0x0000);
ifp->if_capenable |= IFCAP_POLLING;
VR_UNLOCK(sc);
} else {
error = ether_poll_deregister(ifp);
/* Enable interrupts. */
VR_LOCK(sc);
CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
ifp->if_capenable &= ~IFCAP_POLLING;
VR_UNLOCK(sc);
}
Big polling(4) cleanup. o Axe poll in trap. o Axe IFF_POLLING flag from if_flags. o Rework revision 1.21 (Giant removal), in such a way that poll_mtx is not dropped during call to polling handler. This fixes problem with idle polling. o Make registration and deregistration from polling in a functional way, insted of next tick/interrupt. o Obsolete kern.polling.enable. Polling is turned on/off with ifconfig. Detailed kern_poll.c changes: - Remove polling handler flags, introduced in 1.21. The are not needed now. - Forget and do not check if_flags, if_capenable and if_drv_flags. - Call all registered polling handlers unconditionally. - Do not drop poll_mtx, when entering polling handlers. - In ether_poll() NET_LOCK_GIANT prior to locking poll_mtx. - In netisr_poll() axe the block, where polling code asks drivers to unregister. - In netisr_poll() and ether_poll() do polling always, if any handlers are present. - In ether_poll_[de]register() remove a lot of error hiding code. Assert that arguments are correct, instead. - In ether_poll_[de]register() use standard return values in case of error or success. - Introduce poll_switch() that is a sysctl handler for kern.polling.enable. poll_switch() goes through interface list and enabled/disables polling. A message that kern.polling.enable is deprecated is printed. Detailed driver changes: - On attach driver announces IFCAP_POLLING in if_capabilities, but not in if_capenable. - On detach driver calls ether_poll_deregister() if polling is enabled. - In polling handler driver obtains its lock and checks IFF_DRV_RUNNING flag. If there is no, then unlocks and returns. - In ioctl handler driver checks for IFCAP_POLLING flag requested to be set or cleared. Driver first calls ether_poll_[de]register(), then obtains driver lock and [dis/en]ables interrupts. - In interrupt handler driver checks IFCAP_POLLING flag in if_capenable. If present, then returns.This is important to protect from spurious interrupts. Reviewed by: ru, sam, jhb
2005-10-01 18:56:19 +00:00
}
#endif /* DEVICE_POLLING */
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if ((mask & IFCAP_TXCSUM) != 0 &&
(IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
ifp->if_capenable ^= IFCAP_TXCSUM;
if ((IFCAP_TXCSUM & ifp->if_capenable) != 0)
ifp->if_hwassist |= VR_CSUM_FEATURES;
else
ifp->if_hwassist &= ~VR_CSUM_FEATURES;
}
if ((mask & IFCAP_RXCSUM) != 0 &&
(IFCAP_RXCSUM & ifp->if_capabilities) != 0)
ifp->if_capenable ^= IFCAP_RXCSUM;
if ((mask & IFCAP_WOL_UCAST) != 0 &&
(ifp->if_capabilities & IFCAP_WOL_UCAST) != 0)
ifp->if_capenable ^= IFCAP_WOL_UCAST;
if ((mask & IFCAP_WOL_MAGIC) != 0 &&
(ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
ifp->if_capenable ^= IFCAP_WOL_MAGIC;
Implemented per-interface polling(4) control.
2004-04-11 15:18:09 +00:00
break;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
default:
o track either_ifattach/ether_ifdetach API changes o use if_input for input packet processing o don't strip the Ethernet header for input packets o use BPF_* macros bpf tapping o call ether_ioctl to handle default ioctl case o track vlan changes Reviewed by: many Approved by: re
2002-11-14 23:49:09 +00:00
error = ether_ioctl(ifp, command, data);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
break;
}
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
return (error);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
style: put return types on a line by themselves.
2002-08-24 00:02:03 +00:00
static void
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
vr_watchdog(struct vr_softc *sc)
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
{
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
struct ifnet *ifp;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
VR_LOCK_ASSERT(sc);
if (sc->vr_watchdog_timer == 0 || --sc->vr_watchdog_timer)
return;
ifp = sc->vr_ifp;
/*
* Reclaim first as we don't request interrupt for every packets.
*/
vr_txeof(sc);
if (sc->vr_cdata.vr_tx_cnt == 0)
return;
Reuse flag variable to represent driver internal states rather than using member variables in softc. While I'm here change media after setting IFF_DRV_RUNNING. This will remove unnecessary link state handling in vr_tick() if controller established a link immediately.
2011-11-28 18:32:35 +00:00
if ((sc->vr_flags & VR_F_LINK) == 0) {
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
if (bootverbose)
if_printf(sc->vr_ifp, "watchdog timeout "
"(missed link)\n");
Mechanically convert to if_inc_counter().
2014-09-18 20:17:27 +00:00
if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
Remove unnecessary controller reinitialization. CAM filter handling was rewritten long time ago so it should not require controller reinitialization. PR: kern/87506
2010-08-24 18:40:11 +00:00
ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
vr_init_locked(sc);
return;
}
Further locking improvements for vr(4): - Add *_locked() entry points as needed to avoid unnecessary lock thrashing. - Use these entry points wisely. - Only acquire the lock once when servicing an interrupt. - Check 'suspended' on interrupt to avoid racing detach. - Correct a mis-spelled comment. - Don't take the lock in vr_reset() to avoid lock thrashing in attach. - Comment this. Reviewed by: -net (silence)
2004-07-09 00:17:14 +00:00
Mechanically convert to if_inc_counter().
2014-09-18 20:17:27 +00:00
if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
- Use if_printf() and device_printf() and remove vr_unit from the softc. I had to initialize the ifnet a bit earlier in attach so that the if_printf()'s in vr_reset() didn't explode with a page fault. - Use M_ZERO with contigmalloc() rather than an explicit bzero.
2005-10-27 21:18:37 +00:00
if_printf(ifp, "watchdog timeout\n");
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Remove unnecessary controller reinitialization. CAM filter handling was rewritten long time ago so it should not require controller reinitialization. PR: kern/87506
2010-08-24 18:40:11 +00:00
ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
Further locking improvements for vr(4): - Add *_locked() entry points as needed to avoid unnecessary lock thrashing. - Use these entry points wisely. - Only acquire the lock once when servicing an interrupt. - Check 'suspended' on interrupt to avoid racing detach. - Correct a mis-spelled comment. - Don't take the lock in vr_reset() to avoid lock thrashing in attach. - Comment this. Reviewed by: -net (silence)
2004-07-09 00:17:14 +00:00
vr_init_locked(sc);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
Second part of ALTQ driver modifications, covering: an(4), ath(4), hme(4), ndis(4), vr(4) and wi(4) Please help testing: http://people.freebsd.org/~mlaier/ALTQ_driver/ Tested by: Vaidas Damosevicius (an, ath, wi) Roman Divacky (vr) Submitted by: yongari (hme)
2004-08-01 23:58:04 +00:00
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
Further locking improvements for vr(4): - Add *_locked() entry points as needed to avoid unnecessary lock thrashing. - Use these entry points wisely. - Only acquire the lock once when servicing an interrupt. - Check 'suspended' on interrupt to avoid racing detach. - Correct a mis-spelled comment. - Don't take the lock in vr_reset() to avoid lock thrashing in attach. - Comment this. Reviewed by: -net (silence)
2004-07-09 00:17:14 +00:00
vr_start_locked(ifp);
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
}
Further locking improvements for vr(4): - Add *_locked() entry points as needed to avoid unnecessary lock thrashing. - Use these entry points wisely. - Only acquire the lock once when servicing an interrupt. - Check 'suspended' on interrupt to avoid racing detach. - Correct a mis-spelled comment. - Don't take the lock in vr_reset() to avoid lock thrashing in attach. - Comment this. Reviewed by: -net (silence)
2004-07-09 00:17:14 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
static void
vr_tx_start(struct vr_softc *sc)
{
bus_addr_t addr;
uint8_t cmd;
cmd = CSR_READ_1(sc, VR_CR0);
if ((cmd & VR_CR0_TX_ON) == 0) {
addr = VR_TX_RING_ADDR(sc, sc->vr_cdata.vr_tx_cons);
CSR_WRITE_4(sc, VR_TXADDR, VR_ADDR_LO(addr));
cmd |= VR_CR0_TX_ON;
CSR_WRITE_1(sc, VR_CR0, cmd);
}
if (sc->vr_cdata.vr_tx_cnt != 0) {
sc->vr_watchdog_timer = 5;
VR_SETBIT(sc, VR_CR0, VR_CR0_TX_GO);
}
}
static void
vr_rx_start(struct vr_softc *sc)
{
bus_addr_t addr;
uint8_t cmd;
cmd = CSR_READ_1(sc, VR_CR0);
if ((cmd & VR_CR0_RX_ON) == 0) {
addr = VR_RX_RING_ADDR(sc, sc->vr_cdata.vr_rx_cons);
CSR_WRITE_4(sc, VR_RXADDR, VR_ADDR_LO(addr));
cmd |= VR_CR0_RX_ON;
CSR_WRITE_1(sc, VR_CR0, cmd);
}
CSR_WRITE_1(sc, VR_CR0, cmd | VR_CR0_RX_GO);
}
static int
vr_tx_stop(struct vr_softc *sc)
{
int i;
uint8_t cmd;
cmd = CSR_READ_1(sc, VR_CR0);
if ((cmd & VR_CR0_TX_ON) != 0) {
cmd &= ~VR_CR0_TX_ON;
CSR_WRITE_1(sc, VR_CR0, cmd);
for (i = VR_TIMEOUT; i > 0; i--) {
DELAY(5);
cmd = CSR_READ_1(sc, VR_CR0);
if ((cmd & VR_CR0_TX_ON) == 0)
break;
}
if (i == 0)
return (ETIMEDOUT);
}
return (0);
}
static int
vr_rx_stop(struct vr_softc *sc)
{
int i;
uint8_t cmd;
cmd = CSR_READ_1(sc, VR_CR0);
if ((cmd & VR_CR0_RX_ON) != 0) {
cmd &= ~VR_CR0_RX_ON;
CSR_WRITE_1(sc, VR_CR0, cmd);
for (i = VR_TIMEOUT; i > 0; i--) {
DELAY(5);
cmd = CSR_READ_1(sc, VR_CR0);
if ((cmd & VR_CR0_RX_ON) == 0)
break;
}
if (i == 0)
return (ETIMEDOUT);
}
return (0);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
/*
* Stop the adapter and free any mbufs allocated to the
* RX and TX lists.
*/
style: put return types on a line by themselves.
2002-08-24 00:02:03 +00:00
static void
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
vr_stop(struct vr_softc *sc)
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
{
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
struct vr_txdesc *txd;
struct vr_rxdesc *rxd;
struct ifnet *ifp;
int i;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
SMPng locking cleanup for vr(4). - Remove recursive locking situations. Remove the MTX_RECURSE bit. - Take the lock for any routine which is not called from within if_vr.c itself; this includes entry points called by newbus, ifnet, callout, ifmedia, and polling subsystems. - Remove spl references from the code added to miibus callbacks in rev 1.60. - Add the INTR_MPSAFE bit. - Tidy up some assignments; locks are not needed for taking the address of something at a known offset, for example. - Tested on the machine this was committed from. Tested on: UP only, !debug.mpsafenet && debug.mpsafenet Reviewed by: rwatson
2004-07-03 02:59:02 +00:00
VR_LOCK_ASSERT(sc);
First round of converting network drivers from spls to mutexes. This takes care of all the 10/100 and gigE PCI drivers that I've done. Next will be the wireless drivers, then the USB ones. I may pick up some stragglers along the way. I'm sort of playing this by ear: if anyone spots any places where I've screwed up horribly, please let me know.
2000-10-13 17:54:19 +00:00
Stop embedding struct ifnet at the top of driver softcs. Instead the struct ifnet or the layer 2 common structure it was embedded in have been replaced with a struct ifnet pointer to be filled by a call to the new function, if_alloc(). The layer 2 common structure is also allocated via if_alloc() based on the interface type. It is hung off the new struct ifnet member, if_l2com. This change removes the size of these structures from the kernel ABI and will allow us to better manage them as interfaces come and go. Other changes of note: - Struct arpcom is no longer referenced in normal interface code. Instead the Ethernet address is accessed via the IFP2ENADDR() macro. To enforce this ac_enaddr has been renamed to _ac_enaddr. - The second argument to ether_ifattach is now always the mac address from driver private storage rather than sometimes being ac_enaddr. Reviewed by: sobomax, sam
2005-06-10 16:49:24 +00:00
ifp = sc->vr_ifp;
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
sc->vr_watchdog_timer = 0;
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
- Use callout_*() to manage the callout and make it MPSAFE. - Fix locking in detach(), we only need to lock across vr_stop(). Tested by: Mike Tancsa mike at sentex dot net MFC after: 1 week
2005-10-31 21:37:27 +00:00
callout_stop(&sc->vr_stat_callout);
Propagate rename of IFF_OACTIVE and IFF_RUNNING to IFF_DRV_OACTIVE and IFF_DRV_RUNNING, as well as the move from ifnet.if_flags to ifnet.if_drv_flags. Device drivers are now responsible for synchronizing access to these flags, as they are in if_drv_flags. This helps prevent races between the network stack and device driver in maintaining the interface flags field. Many __FreeBSD__ and __FreeBSD_version checks maintained and continued; some less so. Reviewed by: pjd, bz MFC after: 7 days
2005-08-09 10:20:02 +00:00
ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
Convert the VIA Rhine driver to miibus.
1999-09-19 22:03:31 +00:00
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
CSR_WRITE_1(sc, VR_CR0, VR_CR0_STOP);
if (vr_rx_stop(sc) != 0)
device_printf(sc->vr_dev, "%s: Rx shutdown error\n", __func__);
if (vr_tx_stop(sc) != 0)
device_printf(sc->vr_dev, "%s: Tx shutdown error\n", __func__);
/* Clear pending interrupts. */
CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
CSR_WRITE_2(sc, VR_IMR, 0x0000);
CSR_WRITE_4(sc, VR_TXADDR, 0x00000000);
CSR_WRITE_4(sc, VR_RXADDR, 0x00000000);
/*
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
* Free RX and TX mbufs still in the queues.
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
*/
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
for (i = 0; i < VR_RX_RING_CNT; i++) {
rxd = &sc->vr_cdata.vr_rxdesc[i];
if (rxd->rx_m != NULL) {
bus_dmamap_sync(sc->vr_cdata.vr_rx_tag,
rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
bus_dmamap_unload(sc->vr_cdata.vr_rx_tag,
rxd->rx_dmamap);
m_freem(rxd->rx_m);
rxd->rx_m = NULL;
}
}
for (i = 0; i < VR_TX_RING_CNT; i++) {
txd = &sc->vr_cdata.vr_txdesc[i];
if (txd->tx_m != NULL) {
bus_dmamap_sync(sc->vr_cdata.vr_tx_tag,
txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->vr_cdata.vr_tx_tag,
txd->tx_dmamap);
m_freem(txd->tx_m);
txd->tx_m = NULL;
}
}
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
/*
* Stop all chip I/O so that the kernel's probe routines don't
* get confused by errant DMAs when rebooting.
*/
Fix function prototype for device_shutdown method.
2007-11-22 02:45:00 +00:00
static int
style(9) compliance. Put some braces around the busy-wait loop in vr_rxeoc() to make the no-op semicolon more obvious. No functional changes. Running on the machine I am committing from without problems. Reviewed by: jmallett
2004-07-02 23:51:44 +00:00
vr_shutdown(device_t dev)
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
{
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
return (vr_suspend(dev));
}
static int
vr_suspend(device_t dev)
{
struct vr_softc *sc;
sc = device_get_softc(dev);
VR_LOCK(sc);
vr_stop(sc);
vr_setwol(sc);
Reuse flag variable to represent driver internal states rather than using member variables in softc. While I'm here change media after setting IFF_DRV_RUNNING. This will remove unnecessary link state handling in vr_tick() if controller established a link immediately.
2011-11-28 18:32:35 +00:00
sc->vr_flags |= VR_F_SUSPENDED;
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
VR_UNLOCK(sc);
return (0);
}
static int
vr_resume(device_t dev)
{
struct vr_softc *sc;
struct ifnet *ifp;
sc = device_get_softc(dev);
VR_LOCK(sc);
ifp = sc->vr_ifp;
vr_clrwol(sc);
vr_reset(sc);
if (ifp->if_flags & IFF_UP)
vr_init_locked(sc);
Reuse flag variable to represent driver internal states rather than using member variables in softc. While I'm here change media after setting IFF_DRV_RUNNING. This will remove unnecessary link state handling in vr_tick() if controller established a link immediately.
2011-11-28 18:32:35 +00:00
sc->vr_flags &= ~VR_F_SUSPENDED;
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
VR_UNLOCK(sc);
Fix function prototype for device_shutdown method.
2007-11-22 02:45:00 +00:00
return (0);
An early Christmas present: add driver support for a whole bunch of PCI fast ethernet adapters, plus man pages. if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100, various other PNIC devices if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various other boards based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and Rhine II chips (note: the D-Link and certain other cards that actually use a Rhine II chip still return the PCI device ID of the Rhine I. I don't know why, and it doesn't really matter since the driver treats both chips the same anyway.) if_wb.c: Trendware TE100-PCIE and various other cards based on the Winbond W89C840F chip (the Trendware card is identical to the sample boards Winbond sent me, so who knows how many clones there are running around) All drivers include support for ifmedia, BPF and hardware multicast filtering. Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and sysinstall device list. I also have a driver for the ASIX AX88140A in the works.
1998-12-04 18:01:24 +00:00
}
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
static void
vr_setwol(struct vr_softc *sc)
{
struct ifnet *ifp;
int pmc;
uint16_t pmstat;
uint8_t v;
VR_LOCK_ASSERT(sc);
if (sc->vr_revid < REV_ID_VT6102_A ||
Do a sweep of the tree replacing calls to pci_find_extcap() with calls to pci_find_cap() instead.
2011-03-23 13:10:15 +00:00
pci_find_cap(sc->vr_dev, PCIY_PMG, &pmc) != 0)
Teach vr(4) to use bus_dma(9) and major overhauling to handle link state change and reliable error recovery. o Moved vr_softc structure and relevant macros to header file. o Use PCIR_BAR macro to get BARs. o Implemented suspend/resume methods. o Implemented automatic Tx threshold configuration which will be activated when it suffers from Tx underrun. Also Tx underrun will try to restart only Tx path and resort to previous full-reset(both Rx/Tx) operation if restarting Tx path have failed. o Removed old bit-banging MII interface. Rhine provides simple and efficient MII interface. While I'm here show PHY address and PHY register number when its read/write operation was failed. o Define VR_MII_TIMEOUT constant and use it in MII access routines. o Always honor link up/down state reported by mii layers. The link state information is used in vr_start() to determine whether we got a valid link. o Removed vr_setcfg() which is now handled in vr_link_task(), link state taskqueue handler. When mii layer reports link state changes the taskqueue handler reprograms MAC to reflect negotiated duplex settings. Flow-control changes are not handled yet and it should be revisited when mii layer knows the notion of flow-control. o Added a new sysctl interface to get statistics of an instance of the driver.(sysctl dev.vr.0.stats=1) o Chip name was renamed to reflect the official name of the chips described in VIA Rhine I/II/III datasheet. REV_ID_3065_A -> REV_ID_VT6102_A REV_ID_3065_B -> REV_ID_VT6102_B REV_ID_3065_C -> REV_ID_VT6102_C REV_ID_3106_J -> REV_ID_VT6105_A0 REV_ID_3106_S -> REV_ID_VT6105M_A0 The following chip revisions were added. #define REV_ID_VT6105_B0 0x83 #define REV_ID_VT6105_LOM 0x8A #define REV_ID_VT6107_A0 0x8C #define REV_ID_VT6107_A1 0x8D #define REV_ID_VT6105M_B1 0x94 o Always show chip revision number in device attach. This shall help identifying revision specific issues. o Check whether EEPROM reloading is complete by inspecting the state of VR_EECSR_LOAD bit. This bit is self-cleared after the EEPROM reloading. Previously vr(4) blindly spins for 200us which may/may not enough to complete the EEPROM reload. o Removed if_mtu setup. It's done in ether_ifattach(). o Use our own callout to drive watchdog timer. o In vr_attach disable further interrupts after reset. For VT6102 or newer hardwares, diable MII state change interrupt as well because mii state handling is done by mii layer. o Add more sane register initialization for VT6102 or newer chips. - Have NIC report error instead of retrying forever. - Let hardware detect MII coding error. - Enable MODE10T mode. - Enable memory-read-multiple for VT6107. o PHY address for VT6105 or newer chips is located at fixed address 1. For older chips the PHY address is stored in VR_PHYADDR register. Armed with these information, there is no need to re-read VR_PHYADDR register in miibus handler to get PHY address. This saves one register access cycle for each MII access. o Don't reprogram VR_PHYADDR register whenever access to a register located at a PHY address is made. Rhine fmaily allows reprogramming PHY address location via VR_PHYADDR register depending on VR_MIISTAT_PHYOPT bit of VR_MIISTAT register. This used to lead numerous phantom PHYs attached to miibus during phy probe phase and driver used to limit allowable PHY address in mii register accessors for certain chip revisions. This removes one more register access cycle for each MII access. o Correctly set VLAN header length. o bus_dma(9) conversion. - Limit DMA access to be in range of 32bit address space. Hardware doesn't support DAC. - Apply descriptor ring alignment requirements(16 bytes alignment) - Apply Rx buffer address alignment requirements(4 bytes alignment) - Apply Tx buffer address alignment requirements(4 bytes alignment) for Rhine I chip. Rhine II or III has no Tx buffer address alignment restrictions, though. - Reduce number of allowable number of DMA segments to 8. - Removed the atomic(9) used in descriptor ownership managements as it's job of bus_dmamap_sync(9). With these change vr(4) should work on all platforms. o Rhine uses two separated 8bits command registers to control Tx/Rx MAC. So don't access it as a single 16bit register. o For non-strict alignment architectures vr(4) no longer require time-consuming copy operation for received frames to align IP header. This greatly improves Rx performance on i386/amd64 platforms. However the alignment is still necessary for strict-alignment platforms(e.g. sparc64). The alignment is handled in new fuction vr_fixup_rx(). o vr_rxeof() now rejects multiple-segmented(fragmented) frames as vr(4) is not ready to handle this situation. Datasheet said nothing about the reason when/why it happens. o In vr_newbuf() don't set VR_RXSTAT_FIRSTFRAG/VR_RXSTAT_LASTFRAG bits as it's set by hardware. o Don't pass checksum offload information to upper layer for fragmented frames. The hardware assisted checksum is valid only when the frame is non-fragmented IP frames. Also mark the checksum is valid for corrupted frames such that upper layers doesn't need to recompute the checksum with software routine. o Removed vr_rxeoc(). RxDMA doesn't seem to need to be idle before sending VR_CMD_RX_GO command. Previously it used to stop RxDMA first which in turn resulted in long delays in Rx error recovery. o Rewrote Tx completion handler. - Always check VR_TXSTAT_OWN bit in status word prior to inspecting other status bits in the status word. - Collision counter updates were corrected as VT3071 or newer ones use different bits to notify collisions. - Unlike other chip revisions, VT86C100A uses different bit to indicate Tx underrun. For VT3071 or newer ones, check both VR_TXSTAT_TBUFF and VR_TXSTAT_UDF bits to see whether Tx underrun was happend. In case of Tx underrun requeue the failed frame and restart stalled Tx SM. Also double Tx DMA threshold size on each failure to mitigate future Tx underruns. - Disarm watchdog timer only if we have no queued packets, otherwise don't touch watchdog timer. o Rewrote interrupt handler. - status word in Tx/Rx descriptors indicates more detailed error state required to recover from the specific error. There is no need to rely on interrupt status word to recover from Tx/Rx error except PCI bus error. Other event notifications like statistics counter overflows or link state events will be handled in main interrupt handler. - Don't touch VR_IMR register if we are in suspend mode. Touching the register may hang the hardware if we are in suspended state. Previously it seems that touching VR_IMR register in interrupt handler was to work-around panic occurred in system shutdown stage on SMP systems. I think that work-around would hide root-cause of the panic and I couldn't reproduce the panic with multiple attempts on my box. o While padding space to meet minimum frame size, zero the pad data in order to avoid possibly leaking sensitive data. o Rewrote vr_start_locked(). - Don't try to queue packets if number of available Tx descriptors are short than that of required one. o Don't reinitialize hardware whenever media configuration is changed. Media/link state changes are reported from mii layer if this happens and vr_link_task() will perform necessary changes. o Don't reinitialize hardware if only PROMISC bit was changed. Just toggle the PROMISC bit in hardware is sufficient to reflect the request. o Rearrganed the IFCAP_POLLING/IFCAP_HWCSUM handling in vr_ioctl(). o Generate Tx completion interrupts for every VR_TX_INTR_THRESH-th frames. This reduces Tx completion interrupts under heavy network loads. o Since vr(4) doesn't request Tx interrupts for every queued frames, reclaim any pending descriptors not handled in Tx completion handler before actually firing up watchdog timeouts. o Added vr_tx_stop()/vr_rx_stop() to wait for the end of active TxDMA/RxDMA cycles(draining). These routines are used in vr_stop() to ensure sane state of MAC before releasing allocated Tx/Rx buffers. vr_link_task() also takes advantage of these functions to get to idle state prior to restarting Tx/Rx. o Added vr_tx_start()/vr_rx_start() to restart Rx/Tx. By separating Rx operation from Tx operation vr(4) no longer need to full-reset the hardware in case of Tx/Rx error recovery. o Implemented WOL. o Added VT6105M specific register definitions. VT6105M has the following hardware capabilities. - Tx/Rx IP/TCP/UDP checksum offload. - VLAN hardware tag insertion/extraction. Due to lack of information for getting extracted VLAN tag in Rx path, VLAN hardware support was not implemented yet. - CAM(Content Addressable Memory) based 32 entry perfect multicast/ VLAN filtering. - 8 priority queues. o Implemented CAM based 32 entry perfect multicast filtering for VT6105M. If number of multicast entry is greater than 32, vr(4) uses traditional hash based filtering. o Reflect real Tx/Rx descriptor structure. Previously vr(4) used to embed other driver (private) data into these structure. This type of embedding make it hard to work on LP64 systems. o Removed unused vr_mii_frame structure and MII bit-baning definitions. o Added new PCI configuration registers that controls mii operation and mode selection. o Reduced number of Tx/Rx descriptors to 128 from 256. From my testing, increasing number of descriptors above than 64 didn't help increasing performance at all. Experimentations show 128 Rx descriptors seems to help a lot reducing Rx FIFO overruns under high system loads. It seems the poor Tx performance of Rhine hardwares comes from the limitation of hardware. You wouldn't satuarte the link with vr(4) no matter how fast CPU/large number of descriptors are used. o Added vr_statistics structure to hold various counter values. No regression was reported but one variant of Rhine III(VT6105M) found on RouterBOARD 44 does not work yet(Reported by Milan Obuch). I hope this would be resolved in near future. I'd like to say big thanks to Mike Tancsa who kindly donated a Rhine hardware to me. Without his enthusiastic testing and feedbacks overhauling vr(4) never have been possible. Also thanks to Masayuki Murayama who provided some good comments on the hardware's internals. This driver is result of combined effort of many users who provided many feedbacks so I'd like to say special thanks to them. Hardware donated by: Mike Tancsa (mike AT sentex dot net) Reviewed by: remko (initial version) Tested by: Mike Tancsa(x86), JoaoBR ( joao AT matik DOT com DOT br ) Marcin Wisnicki ( mwisnicki+freebsd AT gmail DOT com ) Stefan Ehmann ( shoesoft AT gmx DOT net ) Florian Smeets ( flo AT kasimir DOT com ) Phil Oleson ( oz AT nixil DOT net ) Larry Baird ( lab AT gta DOT com ) Milan Obuch ( freebsd-current AT dino DOT sk ) remko (initial version)
2008-03-11 04:51:22 +00:00
return;
ifp = sc->vr_ifp;
/* Clear WOL configuration. */
CSR_WRITE_1(sc, VR_WOLCR_CLR, 0xFF);
CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_SAB | VR_WOLCFG_SAM);
CSR_WRITE_1(sc, VR_PWRCSR_CLR, 0xFF);
CSR_WRITE_1(sc, VR_PWRCFG_CLR, VR_PWRCFG_WOLEN);
if (sc->vr_revid > REV_ID_VT6105_B0) {
/* Newer Rhine III supports two additional patterns. */
CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_PATTERN_PAGE);
CSR_WRITE_1(sc, VR_TESTREG_CLR, 3);
CSR_WRITE_1(sc, VR_PWRCSR1_CLR, 3);
}
if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
CSR_WRITE_1(sc, VR_WOLCR_SET, VR_WOLCR_UCAST);
if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
CSR_WRITE_1(sc, VR_WOLCR_SET, VR_WOLCR_MAGIC);
/*
* It seems that multicast wakeup frames require programming pattern
* registers and valid CRC as well as pattern mask for each pattern.
* While it's possible to setup such a pattern it would complicate
* WOL configuration so ignore multicast wakeup frames.
*/
if ((ifp->if_capenable & IFCAP_WOL) != 0) {
CSR_WRITE_1(sc, VR_WOLCFG_SET, VR_WOLCFG_SAB | VR_WOLCFG_SAM);
v = CSR_READ_1(sc, VR_STICKHW);
CSR_WRITE_1(sc, VR_STICKHW, v | VR_STICKHW_WOL_ENB);
CSR_WRITE_1(sc, VR_PWRCFG_SET, VR_PWRCFG_WOLEN);
}
/* Put hardware into sleep. */
v = CSR_READ_1(sc, VR_STICKHW);
v |= VR_STICKHW_DS0 | VR_STICKHW_DS1;
CSR_WRITE_1(sc, VR_STICKHW, v);
/* Request PME if WOL is requested. */
pmstat = pci_read_config(sc->vr_dev, pmc + PCIR_POWER_STATUS, 2);
pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
if ((ifp->if_capenable & IFCAP_WOL) != 0)
pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
pci_write_config(sc->vr_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
}
static void
vr_clrwol(struct vr_softc *sc)
{
uint8_t v;
VR_LOCK_ASSERT(sc);
if (sc->vr_revid < REV_ID_VT6102_A)
return;
/* Take hardware out of sleep. */
v = CSR_READ_1(sc, VR_STICKHW);
v &= ~(VR_STICKHW_DS0 | VR_STICKHW_DS1 | VR_STICKHW_WOL_ENB);
CSR_WRITE_1(sc, VR_STICKHW, v);
/* Clear WOL configuration as WOL may interfere normal operation. */
CSR_WRITE_1(sc, VR_WOLCR_CLR, 0xFF);
CSR_WRITE_1(sc, VR_WOLCFG_CLR,
VR_WOLCFG_SAB | VR_WOLCFG_SAM | VR_WOLCFG_PMEOVR);
CSR_WRITE_1(sc, VR_PWRCSR_CLR, 0xFF);
CSR_WRITE_1(sc, VR_PWRCFG_CLR, VR_PWRCFG_WOLEN);
if (sc->vr_revid > REV_ID_VT6105_B0) {
/* Newer Rhine III supports two additional patterns. */
CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_PATTERN_PAGE);
CSR_WRITE_1(sc, VR_TESTREG_CLR, 3);
CSR_WRITE_1(sc, VR_PWRCSR1_CLR, 3);
}
}
static int
vr_sysctl_stats(SYSCTL_HANDLER_ARGS)
{
struct vr_softc *sc;
struct vr_statistics *stat;
int error;
int result;
result = -1;
error = sysctl_handle_int(oidp, &result, 0, req);
if (error != 0 || req->newptr == NULL)
return (error);
if (result == 1) {
sc = (struct vr_softc *)arg1;
stat = &sc->vr_stat;
printf("%s statistics:\n", device_get_nameunit(sc->vr_dev));
printf("Outbound good frames : %ju\n",
(uintmax_t)stat->tx_ok);
printf("Inbound good frames : %ju\n",
(uintmax_t)stat->rx_ok);
printf("Outbound errors : %u\n", stat->tx_errors);
printf("Inbound errors : %u\n", stat->rx_errors);
printf("Inbound no buffers : %u\n", stat->rx_no_buffers);
printf("Inbound no mbuf clusters: %d\n", stat->rx_no_mbufs);
printf("Inbound FIFO overflows : %d\n",
stat->rx_fifo_overflows);
printf("Inbound CRC errors : %u\n", stat->rx_crc_errors);
printf("Inbound frame alignment errors : %u\n",
stat->rx_alignment);
printf("Inbound giant frames : %u\n", stat->rx_giants);
printf("Inbound runt frames : %u\n", stat->rx_runts);
printf("Outbound aborted with excessive collisions : %u\n",
stat->tx_abort);
printf("Outbound collisions : %u\n", stat->tx_collisions);
printf("Outbound late collisions : %u\n",
stat->tx_late_collisions);
printf("Outbound underrun : %u\n", stat->tx_underrun);
printf("PCI bus errors : %u\n", stat->bus_errors);
printf("driver restarted due to Rx/Tx shutdown failure : %u\n",
stat->num_restart);
}
return (error);
}
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