freebsd-nq/sys/dev/sdhci/sdhci_if.m

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#-
# Copyright (c) 2006 M. Warner Losh
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
# SUCH DAMAGE.
#
# Portions of this software may have been developed with reference to
# the SD Simplified Specification. The following disclaimer may apply:
#
# The following conditions apply to the release of the simplified
# specification ("Simplified Specification") by the SD Card Association and
# the SD Group. The Simplified Specification is a subset of the complete SD
# Specification which is owned by the SD Card Association and the SD
# Group. This Simplified Specification is provided on a non-confidential
# basis subject to the disclaimers below. Any implementation of the
# Simplified Specification may require a license from the SD Card
# Association, SD Group, SD-3C LLC or other third parties.
#
# Disclaimers:
#
# The information contained in the Simplified Specification is presented only
# as a standard specification for SD Cards and SD Host/Ancillary products and
# is provided "AS-IS" without any representations or warranties of any
# kind. No responsibility is assumed by the SD Group, SD-3C LLC or the SD
# Card Association for any damages, any infringements of patents or other
# right of the SD Group, SD-3C LLC, the SD Card Association or any third
# parties, which may result from its use. No license is granted by
# implication, estoppel or otherwise under any patent or other rights of the
# SD Group, SD-3C LLC, the SD Card Association or any third party. Nothing
# herein shall be construed as an obligation by the SD Group, the SD-3C LLC
# or the SD Card Association to disclose or distribute any technical
# information, know-how or other confidential information to any third party.
#
# $FreeBSD$
#
#
# This is the set of callbacks that mmc bridges call into the bus, or
# that mmc/sd card drivers call to make requests.
#
o Add support for eMMC HS200 and HS400 bus speed modes at 200 MHz to sdhci(4), mmc(4) and mmcsd(4). For the most part, this consists of: - Correcting and extending the infrastructure for negotiating and enabling post-DDR52 modes already added as part of r315598. In fact, HS400ES now should work as well but hasn't been activated due to lack of corresponding hardware. - Adding support executing standard SDHCI initial tuning as well as re-tuning as required for eMMC HS200/HS400 and the fast UHS-I SD card modes. Currently, corresponding methods are only hooked up to the ACPI and PCI front-ends of sdhci(4), though. Moreover, sdhci(4) won't offer any modes requiring (re-)tuning to the MMC/SD layer in order to not break operations with other sdhci(4) front- ends. Likewise, sdhci(4) now no longer offers modes requiring the set_uhs_timing method introduced in r315598 to be implemented/ hooked up (previously, this method was used with DDR52 only, which in turn is only available with Intel controllers so far, i. e. no such limitation was necessary before). Similarly for 1.2/1.8 V VCCQ support and the switch_vccq method. - Addition of locking to the IOCTL half of mmcsd(4) to prevent races with detachment and suspension, especially since it's required to immediately switch away from RPMB partitions again after an access to these (so re-tuning can take place anew, given that the current eMMC specification v5.1 doesn't allow tuning commands to be issued with a RPMB partition selected). Therefore, the existing part_mtx lock in the mmcsd(4) softc is additionally renamed to disk_mtx in order to denote that it only refers to the disk(9) half, likewise for corresponding macros. On the system where the addition of DDR52 support increased the read throughput to ~80 MB/s (from ~45 MB/s at high speed), HS200 yields ~154 MB/s and HS400 ~187 MB/s, i. e. performance now has more than quadrupled compared to pre-r315598. Also, with the advent of (re-)tuning support, most infrastructure necessary for SD card UHS-I modes up to SDR104 now is also in place. Note, though, that the standard SDHCI way of (re-)tuning is special in several ways, which also is why sending the actual tuning requests to the device is part of sdhci(4). SDHCI implementations not following the specification, MMC and non-SDHCI SD card controllers likely will use a generic implementation in the MMC/SD layer for executing tuning, which hasn't been written so far, though. However, in fact this isn't a feature-only change; there are boards based on Intel Bay Trail where DDR52 is problematic and the suggested workaround is to use HS200 mode instead. So far exact details are unknown, however, i. e. whether that's due to a defect in these SoCs or on the boards. Moreover, due to the above changes requiring to be aware of possible MMC siblings in the fast path of mmc(4), corresponding information now is cached in mmc_softc. As a side-effect, mmc_calculate_clock(), mmc_delete_cards(), mmc_discover_cards() and mmc_rescan_cards() now all are guaranteed to operate on the same set of devices as there no longer is any use of device_get_children(9), which can fail in low memory situations. Likewise, mmc_calculate_clock() now longer will trigger a panic due to the latter. o Fix a bug in the failure reporting of mmcsd_delete(); in case of an error when the starting block of a previously stored erase request is used (in order to be able to erase a full erase sector worth of data), the starting block of the newly supplied bio_pblkno has to be returned for indicating no progress. Otherwise, upper layers might be told that a negative number of BIOs have been completed, leading to a panic. o Fix 2 bugs on resume: - Things done in fork1(9) like the acquisition of an SX lock or the sleepable memory allocation are incompatible with a MTX_DEF taken. Thus, mmcsd_resume() must not call kproc_create(9), which in turn uses fork1(9), with the disk_mtx (formerly part_mtx) held. - In mmc_suspend(), the bus is powered down, which in the typical case of a device being selected at the time of suspension, causes the device deselection as part of the bus acquisition by mmc(4) in mmc_scan() to fail as the bus isn't powered up again before later in mmc_go_discovery(). Thus, power down with the bus acquired in mmc_suspend(), which will trigger the deselection up-front. o Fix a memory leak in mmcsd_ioctl() in case copyin(9) fails. [1] o Fix missing variable initialization in mmc_switch_status(). [2] o Fix R1_SWITCH_ERROR detection in mmc_switch_status(). [3] o Handle the case of device_add_child(9) failing, for example due to a memory shortage, gracefully in mmc(4) and sdhci(4), including not leaking memory for the instance variables in case of mmc(4) (which might or might not fix [4] as the latter problem has been discovered independently). o Handle the case of an unknown SD CSD version in mmc_decode_csd_sd() gracefully instead of calling panic(9). o Again, check and handle the return values of some additional function calls in mmc(4) instead of assuming that everything went right or mark non-fatal errors by casting the return value to void. o Correct a typo in the Linux IOCTL compatibility; it should have been MMC_IOC_MULTI_CMD rather than MMC_IOC_CMD_MULTI. o Now that we are reaching ever faster speeds (more improvement in this regard is to be expected when adding ADMA support to sdhci(4)), apply a few micro-optimizations like predicting mmc(4) and sdhci(4) debugging to be off or caching erase sector and maximum data sizes as well support of block addressing in mmsd(4) (instead of doing 2 indirections on every read/write request for determining the maximum data size for example). Reported by: Coverity CID: 1372612 [1], 1372624 [2], 1372594 [3], 1007069 [4]
2017-07-23 16:11:47 +00:00
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/types.h>
#include <sys/sysctl.h>
#include <sys/taskqueue.h>
o Add support for eMMC HS200 and HS400 bus speed modes at 200 MHz to sdhci(4), mmc(4) and mmcsd(4). For the most part, this consists of: - Correcting and extending the infrastructure for negotiating and enabling post-DDR52 modes already added as part of r315598. In fact, HS400ES now should work as well but hasn't been activated due to lack of corresponding hardware. - Adding support executing standard SDHCI initial tuning as well as re-tuning as required for eMMC HS200/HS400 and the fast UHS-I SD card modes. Currently, corresponding methods are only hooked up to the ACPI and PCI front-ends of sdhci(4), though. Moreover, sdhci(4) won't offer any modes requiring (re-)tuning to the MMC/SD layer in order to not break operations with other sdhci(4) front- ends. Likewise, sdhci(4) now no longer offers modes requiring the set_uhs_timing method introduced in r315598 to be implemented/ hooked up (previously, this method was used with DDR52 only, which in turn is only available with Intel controllers so far, i. e. no such limitation was necessary before). Similarly for 1.2/1.8 V VCCQ support and the switch_vccq method. - Addition of locking to the IOCTL half of mmcsd(4) to prevent races with detachment and suspension, especially since it's required to immediately switch away from RPMB partitions again after an access to these (so re-tuning can take place anew, given that the current eMMC specification v5.1 doesn't allow tuning commands to be issued with a RPMB partition selected). Therefore, the existing part_mtx lock in the mmcsd(4) softc is additionally renamed to disk_mtx in order to denote that it only refers to the disk(9) half, likewise for corresponding macros. On the system where the addition of DDR52 support increased the read throughput to ~80 MB/s (from ~45 MB/s at high speed), HS200 yields ~154 MB/s and HS400 ~187 MB/s, i. e. performance now has more than quadrupled compared to pre-r315598. Also, with the advent of (re-)tuning support, most infrastructure necessary for SD card UHS-I modes up to SDR104 now is also in place. Note, though, that the standard SDHCI way of (re-)tuning is special in several ways, which also is why sending the actual tuning requests to the device is part of sdhci(4). SDHCI implementations not following the specification, MMC and non-SDHCI SD card controllers likely will use a generic implementation in the MMC/SD layer for executing tuning, which hasn't been written so far, though. However, in fact this isn't a feature-only change; there are boards based on Intel Bay Trail where DDR52 is problematic and the suggested workaround is to use HS200 mode instead. So far exact details are unknown, however, i. e. whether that's due to a defect in these SoCs or on the boards. Moreover, due to the above changes requiring to be aware of possible MMC siblings in the fast path of mmc(4), corresponding information now is cached in mmc_softc. As a side-effect, mmc_calculate_clock(), mmc_delete_cards(), mmc_discover_cards() and mmc_rescan_cards() now all are guaranteed to operate on the same set of devices as there no longer is any use of device_get_children(9), which can fail in low memory situations. Likewise, mmc_calculate_clock() now longer will trigger a panic due to the latter. o Fix a bug in the failure reporting of mmcsd_delete(); in case of an error when the starting block of a previously stored erase request is used (in order to be able to erase a full erase sector worth of data), the starting block of the newly supplied bio_pblkno has to be returned for indicating no progress. Otherwise, upper layers might be told that a negative number of BIOs have been completed, leading to a panic. o Fix 2 bugs on resume: - Things done in fork1(9) like the acquisition of an SX lock or the sleepable memory allocation are incompatible with a MTX_DEF taken. Thus, mmcsd_resume() must not call kproc_create(9), which in turn uses fork1(9), with the disk_mtx (formerly part_mtx) held. - In mmc_suspend(), the bus is powered down, which in the typical case of a device being selected at the time of suspension, causes the device deselection as part of the bus acquisition by mmc(4) in mmc_scan() to fail as the bus isn't powered up again before later in mmc_go_discovery(). Thus, power down with the bus acquired in mmc_suspend(), which will trigger the deselection up-front. o Fix a memory leak in mmcsd_ioctl() in case copyin(9) fails. [1] o Fix missing variable initialization in mmc_switch_status(). [2] o Fix R1_SWITCH_ERROR detection in mmc_switch_status(). [3] o Handle the case of device_add_child(9) failing, for example due to a memory shortage, gracefully in mmc(4) and sdhci(4), including not leaking memory for the instance variables in case of mmc(4) (which might or might not fix [4] as the latter problem has been discovered independently). o Handle the case of an unknown SD CSD version in mmc_decode_csd_sd() gracefully instead of calling panic(9). o Again, check and handle the return values of some additional function calls in mmc(4) instead of assuming that everything went right or mark non-fatal errors by casting the return value to void. o Correct a typo in the Linux IOCTL compatibility; it should have been MMC_IOC_MULTI_CMD rather than MMC_IOC_CMD_MULTI. o Now that we are reaching ever faster speeds (more improvement in this regard is to be expected when adding ADMA support to sdhci(4)), apply a few micro-optimizations like predicting mmc(4) and sdhci(4) debugging to be off or caching erase sector and maximum data sizes as well support of block addressing in mmsd(4) (instead of doing 2 indirections on every read/write request for determining the maximum data size for example). Reported by: Coverity CID: 1372612 [1], 1372624 [2], 1372594 [3], 1007069 [4]
2017-07-23 16:11:47 +00:00
#include <machine/bus.h>
#include <dev/mmc/bridge.h>
#include <dev/sdhci/sdhci.h>
o Add support for eMMC DDR bus speed mode at 52 MHz to sdhci(4) and mmc(4). For the most part, this consists of support for: - Switching the signal voltage (VCCQ) to 1.8 V or (if supported by the host controller) to 1.2 V, - setting the UHS mode as appropriate in the SDHCI_HOST_CONTROL2 register, - setting the power class in the eMMC device according to the core supply voltage (VCC), - using different bits for enabling a bus width of 4 and 8 bits in the the eMMC device at DDR or higher timings respectively, - arbitrating timings faster than high speed if there actually are additional devices on the same MMC bus. Given that support for DDR52 is not denoted by SDHCI capability registers, availability of that timing is indicated by a new quirk SDHCI_QUIRK_MMC_DDR52 and only enabled for Intel SDHCI controllers so far. Generally, what it takes for a sdhci(4) front-end to enable support for DDR52 is to hook up the bridge method mmcbr_switch_vccq (which especially for 1.2 V signaling support is chip/board specific) and the sdhci_set_uhs_timing sdhci(4) method. As a side-effect, this change also fixes communication with some eMMC devices at SDR high speed mode with 52 MHz due to the signaling voltage and UHS bits in the SDHCI controller no longer being left in an inappropriate state. Compared to 52 MHz at SDR high speed which typically yields ~45 MB/s with the eMMC chips tested, throughput goes up to ~80 MB/s at DDR52. Additionally, this change already adds infrastructure and quite some code for modes up to HS400ES and SDR104 respectively (I did not want to add to much stuff at a time, though). Essentially, what is still missing in order to be able to activate support for these latter is is support for and handling of (re-)tuning. o In sdhci(4), add two tunables hw.sdhci.quirk_clear as well as hw.sdhci.quirk_set, which (when hooked up in the front-end) allow to set/clear sdhci(4) quirks for debugging and testing purposes. However, especially for SDHCI controllers on the PCI bus which have no specific support code so far and, thus, are picked up as generic SDHCI controllers, hw.sdhci.quirk_set allows for setting the necessary quirks (if required). o In mmc(4), check and handle the return values of some more function calls instead of assuming that everything went right. In case failures actually are not problematic, indicate that by casting the return value to void. Reviewed by: jmcneill
2017-03-19 23:27:17 +00:00
CODE {
static void
null_set_uhs_timing(device_t brdev __unused,
struct sdhci_slot *slot __unused)
{
}
}
INTERFACE sdhci;
METHOD uint8_t read_1 {
device_t brdev;
struct sdhci_slot *slot;
bus_size_t off;
}
METHOD uint16_t read_2 {
device_t brdev;
struct sdhci_slot *slot;
bus_size_t off;
}
METHOD uint32_t read_4 {
device_t brdev;
struct sdhci_slot *slot;
bus_size_t off;
}
METHOD void read_multi_4 {
device_t brdev;
struct sdhci_slot *slot;
bus_size_t off;
uint32_t *data;
bus_size_t count;
}
METHOD void write_1 {
device_t brdev;
struct sdhci_slot *slot;
bus_size_t off;
uint8_t val;
}
METHOD void write_2 {
device_t brdev;
struct sdhci_slot *slot;
bus_size_t off;
uint16_t val;
}
METHOD void write_4 {
device_t brdev;
struct sdhci_slot *slot;
bus_size_t off;
uint32_t val;
}
METHOD void write_multi_4 {
device_t brdev;
struct sdhci_slot *slot;
bus_size_t off;
uint32_t *data;
bus_size_t count;
}
METHOD int platform_will_handle {
device_t brdev;
struct sdhci_slot *slot;
}
METHOD void platform_start_transfer {
device_t brdev;
struct sdhci_slot *slot;
uint32_t *intmask;
}
METHOD void platform_finish_transfer {
device_t brdev;
struct sdhci_slot *slot;
}
METHOD uint32_t min_freq {
device_t brdev;
struct sdhci_slot *slot;
} DEFAULT sdhci_generic_min_freq;
METHOD bool get_card_present {
device_t brdev;
struct sdhci_slot *slot;
} DEFAULT sdhci_generic_get_card_present;
o Add support for eMMC DDR bus speed mode at 52 MHz to sdhci(4) and mmc(4). For the most part, this consists of support for: - Switching the signal voltage (VCCQ) to 1.8 V or (if supported by the host controller) to 1.2 V, - setting the UHS mode as appropriate in the SDHCI_HOST_CONTROL2 register, - setting the power class in the eMMC device according to the core supply voltage (VCC), - using different bits for enabling a bus width of 4 and 8 bits in the the eMMC device at DDR or higher timings respectively, - arbitrating timings faster than high speed if there actually are additional devices on the same MMC bus. Given that support for DDR52 is not denoted by SDHCI capability registers, availability of that timing is indicated by a new quirk SDHCI_QUIRK_MMC_DDR52 and only enabled for Intel SDHCI controllers so far. Generally, what it takes for a sdhci(4) front-end to enable support for DDR52 is to hook up the bridge method mmcbr_switch_vccq (which especially for 1.2 V signaling support is chip/board specific) and the sdhci_set_uhs_timing sdhci(4) method. As a side-effect, this change also fixes communication with some eMMC devices at SDR high speed mode with 52 MHz due to the signaling voltage and UHS bits in the SDHCI controller no longer being left in an inappropriate state. Compared to 52 MHz at SDR high speed which typically yields ~45 MB/s with the eMMC chips tested, throughput goes up to ~80 MB/s at DDR52. Additionally, this change already adds infrastructure and quite some code for modes up to HS400ES and SDR104 respectively (I did not want to add to much stuff at a time, though). Essentially, what is still missing in order to be able to activate support for these latter is is support for and handling of (re-)tuning. o In sdhci(4), add two tunables hw.sdhci.quirk_clear as well as hw.sdhci.quirk_set, which (when hooked up in the front-end) allow to set/clear sdhci(4) quirks for debugging and testing purposes. However, especially for SDHCI controllers on the PCI bus which have no specific support code so far and, thus, are picked up as generic SDHCI controllers, hw.sdhci.quirk_set allows for setting the necessary quirks (if required). o In mmc(4), check and handle the return values of some more function calls instead of assuming that everything went right. In case failures actually are not problematic, indicate that by casting the return value to void. Reviewed by: jmcneill
2017-03-19 23:27:17 +00:00
METHOD void set_uhs_timing {
device_t brdev;
struct sdhci_slot *slot;
} DEFAULT null_set_uhs_timing;