1305 lines
26 KiB
Plaintext
1305 lines
26 KiB
Plaintext
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%{
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/*
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* Parser for the Aic7xxx SCSI Host adapter sequencer assembler.
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*
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* Copyright (c) 1997 Justin T. Gibbs.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice immediately at the beginning of the file, without modification,
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* this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id$
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <sysexits.h>
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#include <sys/types.h>
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#include <sys/queue.h>
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#include "aic7xxx_asm.h"
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#include "symbol.h"
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#include "sequencer.h"
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int yylineno;
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char *yyfilename;
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static symbol_t *cur_symbol;
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static symtype cur_symtype;
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static symbol_t *accumulator;
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static symbol_ref_t allones;
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static symbol_ref_t allzeros;
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static symbol_ref_t none;
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static symbol_ref_t sindex;
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static int instruction_ptr;
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static int sram_or_scb_offset;
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static patch_t *cur_patch;
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static void process_bitmask __P((int mask_type, symbol_t *sym, int mask));
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static void initialize_symbol __P((symbol_t *symbol));
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static void process_register __P((symbol_t **p_symbol));
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static void format_1_instr __P((int opcode, symbol_ref_t *dest,
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expression_t *immed, symbol_ref_t *src,
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int ret));
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static void format_2_instr __P((int opcode, symbol_ref_t *dest,
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expression_t *places, symbol_ref_t *src,
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int ret));
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static void format_3_instr __P((int opcode, symbol_ref_t *src,
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expression_t *immed, symbol_ref_t *address));
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static void test_readable_symbol __P((symbol_t *symbol));
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static void test_writable_symbol __P((symbol_t *symbol));
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static void type_check __P((symbol_t *symbol, expression_t *expression,
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int and_op));
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static void make_expression __P((expression_t *immed, int value));
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static void add_conditional __P((symbol_t *symbol));
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#define YYDEBUG 1
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#define SRAM_SYMNAME "SRAM_BASE"
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#define SCB_SYMNAME "SCB_BASE"
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%}
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%union {
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int value;
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char *str;
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symbol_t *sym;
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symbol_ref_t sym_ref;
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expression_t expression;
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}
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%token T_REGISTER
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%token <value> T_CONST
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%token T_SCB
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%token T_SRAM
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%token T_ALIAS
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%token T_SIZE
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%token <value> T_ADDRESS
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%token T_ACCESS_MODE
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%token <value> T_MODE
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%token T_BIT
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%token T_MASK
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%token <value> T_NUMBER
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%token <str> T_PATH
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%token T_EOF T_INCLUDE
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%token <value> T_SHR T_SHL T_ROR T_ROL
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%token <value> T_MVI T_MOV T_CLR
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%token <value> T_JMP T_JC T_JNC T_JE T_JNE T_JNZ T_JZ T_CALL
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%token <value> T_ADD T_ADC
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%token <value> T_INC T_DEC
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%token <value> T_STC T_CLC
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%token <value> T_CMP T_XOR
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%token <value> T_TEST T_AND
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%token <value> T_OR
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%token T_RET
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%token T_NOP
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%token T_ACCUM T_ALLONES T_ALLZEROS T_NONE T_SINDEX
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%token T_A
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%token <sym> T_SYMBOL
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%token T_NL
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%token T_IF T_ELSE T_ENDIF
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%type <sym_ref> reg_symbol address destination source opt_source
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%type <expression> expression immediate immediate_or_a
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%type <value> ret f1_opcode f2_opcode jmp_jc_jnc_call jz_jnz je_jne
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%left '|'
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%left '&'
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%left '+' '-'
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%right '~'
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%nonassoc UMINUS
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%%
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program:
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include
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| program include
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| register
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| program register
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| constant
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| program constant
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| scratch_ram
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| program scratch_ram
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| scb
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| program scb
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| label
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| program label
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| conditional
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| program conditional
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| code
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| program code
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;
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include:
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T_INCLUDE '<' T_PATH '>'
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{ include_file($3, BRACKETED_INCLUDE); }
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| T_INCLUDE '"' T_PATH '"'
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{ include_file($3, QUOTED_INCLUDE); }
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;
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register:
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T_REGISTER { cur_symtype = REGISTER; } reg_definition
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;
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reg_definition:
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T_SYMBOL '{'
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{
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if ($1->type != UNINITIALIZED) {
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stop("Register multiply defined", EX_DATAERR);
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/* NOTREACHED */
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}
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cur_symbol = $1;
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cur_symbol->type = cur_symtype;
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initialize_symbol(cur_symbol);
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}
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reg_attribute_list
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'}'
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{
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/*
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* Default to allowing everything in for registers
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* with no bit or mask definitions.
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*/
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if (cur_symbol->info.rinfo->valid_bitmask == 0)
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cur_symbol->info.rinfo->valid_bitmask = 0xFF;
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if (cur_symbol->info.rinfo->size == 0)
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cur_symbol->info.rinfo->size = 1;
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/*
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* This might be useful for registers too.
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*/
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if (cur_symbol->type != REGISTER) {
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if (cur_symbol->info.rinfo->address == 0)
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cur_symbol->info.rinfo->address =
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sram_or_scb_offset;
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sram_or_scb_offset +=
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cur_symbol->info.rinfo->size;
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}
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cur_symbol = NULL;
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}
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;
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reg_attribute_list:
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reg_attribute
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| reg_attribute_list reg_attribute
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;
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reg_attribute:
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reg_address
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| size
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| access_mode
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| bit_defn
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| mask_defn
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| alias
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| accumulator
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| allones
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| allzeros
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| none
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| sindex
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;
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reg_address:
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T_ADDRESS T_NUMBER
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{
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cur_symbol->info.rinfo->address = $2;
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}
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;
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size:
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T_SIZE T_NUMBER
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{
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cur_symbol->info.rinfo->size = $2;
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}
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;
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access_mode:
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T_ACCESS_MODE T_MODE
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{
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cur_symbol->info.rinfo->mode = $2;
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}
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;
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bit_defn:
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T_BIT T_SYMBOL T_NUMBER
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{
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process_bitmask(BIT, $2, $3);
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}
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;
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mask_defn:
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T_MASK T_SYMBOL expression
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{
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process_bitmask(MASK, $2, $3.value);
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}
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;
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alias:
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T_ALIAS T_SYMBOL
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{
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if ($2->type != UNINITIALIZED) {
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stop("Re-definition of register alias",
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EX_DATAERR);
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/* NOTREACHED */
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}
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$2->type = ALIAS;
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initialize_symbol($2);
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$2->info.ainfo->parent = cur_symbol;
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}
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;
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accumulator:
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T_ACCUM
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{
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if (accumulator != NULL) {
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stop("Only one accumulator definition allowed",
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EX_DATAERR);
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/* NOTREACHED */
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}
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accumulator = cur_symbol;
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}
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;
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allones:
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T_ALLONES
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{
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if (allones.symbol != NULL) {
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stop("Only one definition of allones allowed",
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EX_DATAERR);
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/* NOTREACHED */
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}
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allones.symbol = cur_symbol;
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}
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;
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allzeros:
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T_ALLZEROS
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{
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if (allzeros.symbol != NULL) {
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stop("Only one definition of allzeros allowed",
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EX_DATAERR);
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/* NOTREACHED */
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}
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allzeros.symbol = cur_symbol;
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}
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;
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none:
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T_NONE
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{
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if (none.symbol != NULL) {
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stop("Only one definition of none allowed",
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EX_DATAERR);
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/* NOTREACHED */
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}
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none.symbol = cur_symbol;
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}
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;
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sindex:
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T_SINDEX
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{
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if (sindex.symbol != NULL) {
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stop("Only one definition of sindex allowed",
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EX_DATAERR);
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/* NOTREACHED */
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}
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sindex.symbol = cur_symbol;
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}
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;
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expression:
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expression '|' expression
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{
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$$.value = $1.value | $3.value;
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symlist_merge(&$$.referenced_syms,
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&$1.referenced_syms,
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&$3.referenced_syms);
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}
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| expression '&' expression
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{
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$$.value = $1.value & $3.value;
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symlist_merge(&$$.referenced_syms,
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&$1.referenced_syms,
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&$3.referenced_syms);
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}
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| expression '+' expression
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{
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$$.value = $1.value + $3.value;
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symlist_merge(&$$.referenced_syms,
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&$1.referenced_syms,
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&$3.referenced_syms);
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}
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| expression '-' expression
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{
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$$.value = $1.value - $3.value;
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symlist_merge(&($$.referenced_syms),
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&($1.referenced_syms),
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&($3.referenced_syms));
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}
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| '(' expression ')'
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{
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$$ = $2;
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}
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| '~' expression
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{
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$$ = $2;
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$$.value = (~$$.value) & 0xFF;
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}
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| '-' expression %prec UMINUS
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{
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$$ = $2;
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$$.value = -$$.value;
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}
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| T_NUMBER
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{
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$$.value = $1;
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SLIST_INIT(&$$.referenced_syms);
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}
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| T_SYMBOL
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{
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symbol_t *symbol;
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|
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|
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symbol = $1;
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switch (symbol->type) {
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case ALIAS:
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symbol = $1->info.ainfo->parent;
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||
|
|
case REGISTER:
|
||
|
|
case SCBLOC:
|
||
|
|
case SRAMLOC:
|
||
|
|
$$.value = symbol->info.rinfo->address;
|
||
|
|
break;
|
||
|
|
case MASK:
|
||
|
|
case BIT:
|
||
|
|
$$.value = symbol->info.minfo->mask;
|
||
|
|
break;
|
||
|
|
case CONST:
|
||
|
|
$$.value = symbol->info.cinfo->value;
|
||
|
|
break;
|
||
|
|
case UNINITIALIZED:
|
||
|
|
default:
|
||
|
|
{
|
||
|
|
char buf[255];
|
||
|
|
|
||
|
|
snprintf(buf, sizeof(buf),
|
||
|
|
"Undefined symbol %s referenced",
|
||
|
|
symbol->name);
|
||
|
|
stop(buf, EX_DATAERR);
|
||
|
|
/* NOTREACHED */
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
SLIST_INIT(&$$.referenced_syms);
|
||
|
|
symlist_add(&$$.referenced_syms, symbol, SYMLIST_INSERT_HEAD);
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
constant:
|
||
|
|
T_CONST T_SYMBOL T_NUMBER
|
||
|
|
{
|
||
|
|
if ($2->type != UNINITIALIZED) {
|
||
|
|
stop("Re-definition of constant variable",
|
||
|
|
EX_DATAERR);
|
||
|
|
/* NOTREACHED */
|
||
|
|
}
|
||
|
|
$2->type = CONST;
|
||
|
|
initialize_symbol($2);
|
||
|
|
$2->info.cinfo->value = $3;
|
||
|
|
$2->info.cinfo->define = $1;
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
scratch_ram:
|
||
|
|
T_SRAM '{'
|
||
|
|
{
|
||
|
|
cur_symbol = symtable_get(SRAM_SYMNAME);
|
||
|
|
cur_symtype = SRAMLOC;
|
||
|
|
if (cur_symbol->type != UNINITIALIZED) {
|
||
|
|
stop("Only one SRAM definition allowed",
|
||
|
|
EX_DATAERR);
|
||
|
|
/* NOTREACHED */
|
||
|
|
}
|
||
|
|
cur_symbol->type = SRAMLOC;
|
||
|
|
initialize_symbol(cur_symbol);
|
||
|
|
}
|
||
|
|
reg_address
|
||
|
|
{
|
||
|
|
sram_or_scb_offset = cur_symbol->info.rinfo->address;
|
||
|
|
}
|
||
|
|
scb_or_sram_reg_list
|
||
|
|
'}'
|
||
|
|
{
|
||
|
|
cur_symbol = NULL;
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
scb:
|
||
|
|
T_SCB '{'
|
||
|
|
{
|
||
|
|
cur_symbol = symtable_get(SCB_SYMNAME);
|
||
|
|
cur_symtype = SCBLOC;
|
||
|
|
if (cur_symbol->type != UNINITIALIZED) {
|
||
|
|
stop("Only one SRAM definition allowed",
|
||
|
|
EX_SOFTWARE);
|
||
|
|
/* NOTREACHED */
|
||
|
|
}
|
||
|
|
cur_symbol->type = SCBLOC;
|
||
|
|
initialize_symbol(cur_symbol);
|
||
|
|
}
|
||
|
|
reg_address
|
||
|
|
{
|
||
|
|
sram_or_scb_offset = cur_symbol->info.rinfo->address;
|
||
|
|
}
|
||
|
|
scb_or_sram_reg_list
|
||
|
|
'}'
|
||
|
|
{
|
||
|
|
cur_symbol = NULL;
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
scb_or_sram_reg_list:
|
||
|
|
reg_definition
|
||
|
|
| scb_or_sram_reg_list reg_definition
|
||
|
|
;
|
||
|
|
|
||
|
|
reg_symbol:
|
||
|
|
T_SYMBOL
|
||
|
|
{
|
||
|
|
process_register(&$1);
|
||
|
|
$$.symbol = $1;
|
||
|
|
$$.offset = 0;
|
||
|
|
}
|
||
|
|
| T_SYMBOL '[' T_NUMBER ']'
|
||
|
|
{
|
||
|
|
process_register(&$1);
|
||
|
|
if (($3 + 1) > $1->info.rinfo->size) {
|
||
|
|
stop("Accessing offset beyond range of register",
|
||
|
|
EX_DATAERR);
|
||
|
|
/* NOTREACHED */
|
||
|
|
}
|
||
|
|
$$.symbol = $1;
|
||
|
|
$$.offset = $3;
|
||
|
|
}
|
||
|
|
| T_A
|
||
|
|
{
|
||
|
|
if (accumulator == NULL) {
|
||
|
|
stop("No accumulator has been defined", EX_DATAERR);
|
||
|
|
/* NOTREACHED */
|
||
|
|
}
|
||
|
|
$$.symbol = accumulator;
|
||
|
|
$$.offset = 0;
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
destination:
|
||
|
|
reg_symbol
|
||
|
|
{
|
||
|
|
test_writable_symbol($1.symbol);
|
||
|
|
$$ = $1;
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
immediate:
|
||
|
|
expression
|
||
|
|
{ $$ = $1; }
|
||
|
|
;
|
||
|
|
|
||
|
|
immediate_or_a:
|
||
|
|
expression
|
||
|
|
{
|
||
|
|
$$ = $1;
|
||
|
|
}
|
||
|
|
| T_A
|
||
|
|
{
|
||
|
|
SLIST_INIT(&$$.referenced_syms);
|
||
|
|
$$.value = 0;
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
source:
|
||
|
|
reg_symbol
|
||
|
|
{
|
||
|
|
test_readable_symbol($1.symbol);
|
||
|
|
$$ = $1;
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
opt_source:
|
||
|
|
{
|
||
|
|
$$.symbol = NULL;
|
||
|
|
$$.offset = 0;
|
||
|
|
}
|
||
|
|
| ',' source
|
||
|
|
{ $$ = $2; }
|
||
|
|
;
|
||
|
|
|
||
|
|
ret:
|
||
|
|
{ $$ = 0; }
|
||
|
|
| T_RET
|
||
|
|
{ $$ = 1; }
|
||
|
|
;
|
||
|
|
|
||
|
|
label:
|
||
|
|
T_SYMBOL ':'
|
||
|
|
{
|
||
|
|
if ($1->type != UNINITIALIZED) {
|
||
|
|
stop("Program label multiply defined", EX_DATAERR);
|
||
|
|
/* NOTREACHED */
|
||
|
|
}
|
||
|
|
$1->type = LABEL;
|
||
|
|
initialize_symbol($1);
|
||
|
|
$1->info.linfo->address = instruction_ptr;
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
address:
|
||
|
|
T_SYMBOL
|
||
|
|
{
|
||
|
|
$$.symbol = $1;
|
||
|
|
$$.offset = 0;
|
||
|
|
}
|
||
|
|
| T_SYMBOL '+' T_NUMBER
|
||
|
|
{
|
||
|
|
$$.symbol = $1;
|
||
|
|
$$.offset = $3;
|
||
|
|
}
|
||
|
|
| T_SYMBOL '-' T_NUMBER
|
||
|
|
{
|
||
|
|
$$.symbol = $1;
|
||
|
|
$$.offset = -$3;
|
||
|
|
}
|
||
|
|
| '.'
|
||
|
|
{
|
||
|
|
$$.symbol = NULL;
|
||
|
|
$$.offset = 0;
|
||
|
|
}
|
||
|
|
| '.' '+' T_NUMBER
|
||
|
|
{
|
||
|
|
$$.symbol = NULL;
|
||
|
|
$$.offset = $3;
|
||
|
|
}
|
||
|
|
| '.' '-' T_NUMBER
|
||
|
|
{
|
||
|
|
$$.symbol = NULL;
|
||
|
|
$$.offset = -$3;
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
conditional:
|
||
|
|
T_IF
|
||
|
|
{
|
||
|
|
if (cur_patch != NULL) {
|
||
|
|
stop("Nested .if directive", EX_DATAERR);
|
||
|
|
/* NOTREACHED */
|
||
|
|
}
|
||
|
|
cur_patch = patch_alloc();
|
||
|
|
cur_patch->begin = instruction_ptr;
|
||
|
|
}
|
||
|
|
option_list
|
||
|
|
;
|
||
|
|
|
||
|
|
conditional:
|
||
|
|
T_ELSE
|
||
|
|
{
|
||
|
|
patch_t *next_patch;
|
||
|
|
|
||
|
|
if (cur_patch == NULL) {
|
||
|
|
stop(".else outsize of .if", EX_DATAERR);
|
||
|
|
/* NOTREACHED */
|
||
|
|
}
|
||
|
|
cur_patch->end = instruction_ptr;
|
||
|
|
next_patch = patch_alloc();
|
||
|
|
next_patch->options = cur_patch->options;
|
||
|
|
next_patch->negative = cur_patch->negative ? FALSE : TRUE;
|
||
|
|
cur_patch = next_patch;
|
||
|
|
cur_patch->begin = instruction_ptr;
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
conditional:
|
||
|
|
T_ENDIF
|
||
|
|
{
|
||
|
|
if (cur_patch == NULL) {
|
||
|
|
stop(".endif outsize of .if", EX_DATAERR);
|
||
|
|
/* NOTREACHED */
|
||
|
|
}
|
||
|
|
cur_patch->end = instruction_ptr;
|
||
|
|
cur_patch = NULL;
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
option_list:
|
||
|
|
'(' option_symbol_list ')'
|
||
|
|
| '!' option_list
|
||
|
|
{
|
||
|
|
cur_patch->negative = cur_patch->negative ? FALSE : TRUE;
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
option_symbol_list:
|
||
|
|
T_SYMBOL
|
||
|
|
{
|
||
|
|
add_conditional($1);
|
||
|
|
}
|
||
|
|
| option_list '|' T_SYMBOL
|
||
|
|
{
|
||
|
|
add_conditional($3);
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
f1_opcode:
|
||
|
|
T_AND { $$ = AIC_OP_AND; }
|
||
|
|
| T_XOR { $$ = AIC_OP_XOR; }
|
||
|
|
| T_ADD { $$ = AIC_OP_ADD; }
|
||
|
|
| T_ADC { $$ = AIC_OP_ADC; }
|
||
|
|
;
|
||
|
|
|
||
|
|
code:
|
||
|
|
f1_opcode destination ',' immediate_or_a opt_source ret ';'
|
||
|
|
{
|
||
|
|
format_1_instr($1, &$2, &$4, &$5, $6);
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
code:
|
||
|
|
T_OR reg_symbol ',' immediate_or_a opt_source ret ';'
|
||
|
|
{
|
||
|
|
format_1_instr(AIC_OP_OR, &$2, &$4, &$5, $6);
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
code:
|
||
|
|
T_INC destination opt_source ret ';'
|
||
|
|
{
|
||
|
|
expression_t immed;
|
||
|
|
|
||
|
|
make_expression(&immed, 1);
|
||
|
|
format_1_instr(AIC_OP_ADD, &$2, &immed, &$3, $4);
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
code:
|
||
|
|
T_DEC destination opt_source ret ';'
|
||
|
|
{
|
||
|
|
expression_t immed;
|
||
|
|
|
||
|
|
make_expression(&immed, -1);
|
||
|
|
format_1_instr(AIC_OP_ADD, &$2, &immed, &$3, $4);
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
code:
|
||
|
|
T_CLC ret ';'
|
||
|
|
{
|
||
|
|
expression_t immed;
|
||
|
|
|
||
|
|
make_expression(&immed, -1);
|
||
|
|
format_1_instr(AIC_OP_ADD, &none, &immed, &allzeros, $2);
|
||
|
|
}
|
||
|
|
| T_CLC T_MVI destination ',' immediate_or_a ret ';'
|
||
|
|
{
|
||
|
|
format_1_instr(AIC_OP_ADD, &$3, &$5, &allzeros, $6);
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
code:
|
||
|
|
T_STC ret ';'
|
||
|
|
{
|
||
|
|
expression_t immed;
|
||
|
|
|
||
|
|
make_expression(&immed, 1);
|
||
|
|
format_1_instr(AIC_OP_ADD, &none, &immed, &allones, $2);
|
||
|
|
}
|
||
|
|
| T_STC destination ret ';'
|
||
|
|
{
|
||
|
|
expression_t immed;
|
||
|
|
|
||
|
|
make_expression(&immed, 1);
|
||
|
|
format_1_instr(AIC_OP_ADD, &$2, &immed, &allones, $3);
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
code:
|
||
|
|
T_MOV destination ',' source ret ';'
|
||
|
|
{
|
||
|
|
expression_t immed;
|
||
|
|
|
||
|
|
make_expression(&immed, 0xff);
|
||
|
|
format_1_instr(AIC_OP_AND, &$2, &immed, &$4, $5);
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
code:
|
||
|
|
T_MVI destination ',' immediate_or_a ret ';'
|
||
|
|
{
|
||
|
|
format_1_instr(AIC_OP_OR, &$2, &$4, &allzeros, $5);
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
code:
|
||
|
|
T_CLR destination ret ';'
|
||
|
|
{
|
||
|
|
expression_t immed;
|
||
|
|
|
||
|
|
make_expression(&immed, 0xff);
|
||
|
|
format_1_instr(AIC_OP_AND, &$2, &immed, &allzeros, $3);
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
code:
|
||
|
|
T_NOP ';'
|
||
|
|
{
|
||
|
|
expression_t immed;
|
||
|
|
|
||
|
|
make_expression(&immed, 0xff);
|
||
|
|
format_1_instr(AIC_OP_AND, &none, &immed, &allzeros, FALSE);
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
code:
|
||
|
|
T_RET ';'
|
||
|
|
{
|
||
|
|
expression_t immed;
|
||
|
|
|
||
|
|
make_expression(&immed, 0xff);
|
||
|
|
format_1_instr(AIC_OP_AND, &none, &immed, &allzeros, TRUE);
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* This grammer differs from the one in the aic7xxx
|
||
|
|
* reference manual since the grammer listed there is
|
||
|
|
* ambiguous and causes a shift/reduce conflict.
|
||
|
|
* It also seems more logical as the "immediate"
|
||
|
|
* argument is listed as the second arg like the
|
||
|
|
* other formats.
|
||
|
|
*/
|
||
|
|
|
||
|
|
f2_opcode:
|
||
|
|
T_SHL { $$ = AIC_OP_SHL; }
|
||
|
|
| T_SHR { $$ = AIC_OP_SHR; }
|
||
|
|
| T_ROL { $$ = AIC_OP_ROL; }
|
||
|
|
| T_ROR { $$ = AIC_OP_ROR; }
|
||
|
|
;
|
||
|
|
|
||
|
|
code:
|
||
|
|
f2_opcode destination ',' expression opt_source ret ';'
|
||
|
|
{
|
||
|
|
format_2_instr($1, &$2, &$4, &$5, $6);
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
jmp_jc_jnc_call:
|
||
|
|
T_JMP { $$ = AIC_OP_JMP; }
|
||
|
|
| T_JC { $$ = AIC_OP_JC; }
|
||
|
|
| T_JNC { $$ = AIC_OP_JNC; }
|
||
|
|
| T_CALL { $$ = AIC_OP_CALL; }
|
||
|
|
;
|
||
|
|
|
||
|
|
jz_jnz:
|
||
|
|
T_JZ { $$ = AIC_OP_JZ; }
|
||
|
|
| T_JNZ { $$ = AIC_OP_JNZ; }
|
||
|
|
;
|
||
|
|
|
||
|
|
je_jne:
|
||
|
|
T_JE { $$ = AIC_OP_JE; }
|
||
|
|
| T_JNE { $$ = AIC_OP_JNE; }
|
||
|
|
;
|
||
|
|
|
||
|
|
code:
|
||
|
|
jmp_jc_jnc_call address ';'
|
||
|
|
{
|
||
|
|
expression_t immed;
|
||
|
|
|
||
|
|
make_expression(&immed, 0);
|
||
|
|
format_3_instr($1, &sindex, &immed, &$2);
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
code:
|
||
|
|
T_OR reg_symbol ',' immediate jmp_jc_jnc_call address ';'
|
||
|
|
{
|
||
|
|
format_3_instr($5, &$2, &$4, &$6);
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
code:
|
||
|
|
T_TEST source ',' immediate_or_a jz_jnz address ';'
|
||
|
|
{
|
||
|
|
format_3_instr($5, &$2, &$4, &$6);
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
code:
|
||
|
|
T_CMP source ',' immediate_or_a je_jne address ';'
|
||
|
|
{
|
||
|
|
format_3_instr($5, &$2, &$4, &$6);
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
code:
|
||
|
|
T_MOV source jmp_jc_jnc_call address ';'
|
||
|
|
{
|
||
|
|
expression_t immed;
|
||
|
|
|
||
|
|
make_expression(&immed, 0);
|
||
|
|
format_3_instr($3, &$2, &immed, &$4);
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
code:
|
||
|
|
T_MVI immediate jmp_jc_jnc_call address ';'
|
||
|
|
{
|
||
|
|
format_3_instr($3, &allzeros, &$2, &$4);
|
||
|
|
}
|
||
|
|
;
|
||
|
|
|
||
|
|
%%
|
||
|
|
|
||
|
|
static void
|
||
|
|
process_bitmask(mask_type, sym, mask)
|
||
|
|
int mask_type;
|
||
|
|
symbol_t *sym;
|
||
|
|
int mask;
|
||
|
|
{
|
||
|
|
/*
|
||
|
|
* Add the current register to its
|
||
|
|
* symbol list, if it already exists,
|
||
|
|
* warn if we are setting it to a
|
||
|
|
* different value, or in the bit to
|
||
|
|
* the "allowed bits" of this register.
|
||
|
|
*/
|
||
|
|
if (sym->type == UNINITIALIZED) {
|
||
|
|
sym->type = mask_type;
|
||
|
|
initialize_symbol(sym);
|
||
|
|
if (mask_type == BIT) {
|
||
|
|
if (mask == 0) {
|
||
|
|
stop("Bitmask with no bits set", EX_DATAERR);
|
||
|
|
/* NOTREACHED */
|
||
|
|
}
|
||
|
|
if ((mask & ~(0x01 << (ffs(mask) - 1))) != 0) {
|
||
|
|
stop("Bitmask with more than one bit set",
|
||
|
|
EX_DATAERR);
|
||
|
|
/* NOTREACHED */
|
||
|
|
}
|
||
|
|
}
|
||
|
|
sym->info.minfo->mask = mask;
|
||
|
|
} else if (sym->type != mask_type) {
|
||
|
|
stop("Bit definition mirrors a definition of the same "
|
||
|
|
" name, but a different type", EX_DATAERR);
|
||
|
|
/* NOTREACHED */
|
||
|
|
} else if (mask != sym->info.minfo->mask) {
|
||
|
|
stop("Bitmask redefined with a conflicting value", EX_DATAERR);
|
||
|
|
/* NOTREACHED */
|
||
|
|
}
|
||
|
|
/* Fail if this symbol is already listed */
|
||
|
|
if (symlist_search(&(sym->info.minfo->symrefs),
|
||
|
|
cur_symbol->name) != NULL) {
|
||
|
|
stop("Bitmask defined multiple times for register", EX_DATAERR);
|
||
|
|
/* NOTREACHED */
|
||
|
|
}
|
||
|
|
symlist_add(&(sym->info.minfo->symrefs), cur_symbol,
|
||
|
|
SYMLIST_INSERT_HEAD);
|
||
|
|
cur_symbol->info.rinfo->valid_bitmask |= mask;
|
||
|
|
cur_symbol->info.rinfo->typecheck_masks = TRUE;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void
|
||
|
|
initialize_symbol(symbol)
|
||
|
|
symbol_t *symbol;
|
||
|
|
{
|
||
|
|
switch (symbol->type) {
|
||
|
|
case UNINITIALIZED:
|
||
|
|
stop("Call to initialize_symbol with type field unset",
|
||
|
|
EX_SOFTWARE);
|
||
|
|
/* NOTREACHED */
|
||
|
|
break;
|
||
|
|
case REGISTER:
|
||
|
|
case SRAMLOC:
|
||
|
|
case SCBLOC:
|
||
|
|
symbol->info.rinfo =
|
||
|
|
(struct reg_info *)malloc(sizeof(struct reg_info));
|
||
|
|
if (symbol->info.rinfo == NULL) {
|
||
|
|
stop("Can't create register info", EX_SOFTWARE);
|
||
|
|
/* NOTREACHED */
|
||
|
|
}
|
||
|
|
memset(symbol->info.rinfo, 0,
|
||
|
|
sizeof(struct reg_info));
|
||
|
|
break;
|
||
|
|
case ALIAS:
|
||
|
|
symbol->info.ainfo =
|
||
|
|
(struct alias_info *)malloc(sizeof(struct alias_info));
|
||
|
|
if (symbol->info.ainfo == NULL) {
|
||
|
|
stop("Can't create alias info", EX_SOFTWARE);
|
||
|
|
/* NOTREACHED */
|
||
|
|
}
|
||
|
|
memset(symbol->info.ainfo, 0,
|
||
|
|
sizeof(struct alias_info));
|
||
|
|
break;
|
||
|
|
case MASK:
|
||
|
|
case BIT:
|
||
|
|
symbol->info.minfo =
|
||
|
|
(struct mask_info *)malloc(sizeof(struct mask_info));
|
||
|
|
if (symbol->info.minfo == NULL) {
|
||
|
|
stop("Can't create bitmask info", EX_SOFTWARE);
|
||
|
|
/* NOTREACHED */
|
||
|
|
}
|
||
|
|
memset(symbol->info.minfo, 0, sizeof(struct mask_info));
|
||
|
|
SLIST_INIT(&(symbol->info.minfo->symrefs));
|
||
|
|
break;
|
||
|
|
case CONST:
|
||
|
|
symbol->info.cinfo =
|
||
|
|
(struct const_info *)malloc(sizeof(struct const_info));
|
||
|
|
if (symbol->info.cinfo == NULL) {
|
||
|
|
stop("Can't create alias info", EX_SOFTWARE);
|
||
|
|
/* NOTREACHED */
|
||
|
|
}
|
||
|
|
memset(symbol->info.cinfo, 0,
|
||
|
|
sizeof(struct const_info));
|
||
|
|
break;
|
||
|
|
case LABEL:
|
||
|
|
symbol->info.linfo =
|
||
|
|
(struct label_info *)malloc(sizeof(struct label_info));
|
||
|
|
if (symbol->info.linfo == NULL) {
|
||
|
|
stop("Can't create label info", EX_SOFTWARE);
|
||
|
|
/* NOTREACHED */
|
||
|
|
}
|
||
|
|
memset(symbol->info.linfo, 0,
|
||
|
|
sizeof(struct label_info));
|
||
|
|
break;
|
||
|
|
case CONDITIONAL:
|
||
|
|
symbol->info.condinfo =
|
||
|
|
(struct cond_info *)malloc(sizeof(struct cond_info));
|
||
|
|
if (symbol->info.condinfo == NULL) {
|
||
|
|
stop("Can't create conditional info", EX_SOFTWARE);
|
||
|
|
/* NOTREACHED */
|
||
|
|
}
|
||
|
|
memset(symbol->info.condinfo, 0,
|
||
|
|
sizeof(struct cond_info));
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
stop("Call to initialize_symbol with invalid symbol type",
|
||
|
|
EX_SOFTWARE);
|
||
|
|
/* NOTREACHED */
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void
|
||
|
|
process_register(p_symbol)
|
||
|
|
symbol_t **p_symbol;
|
||
|
|
{
|
||
|
|
char buf[255];
|
||
|
|
symbol_t *symbol = *p_symbol;
|
||
|
|
|
||
|
|
if (symbol->type == UNINITIALIZED) {
|
||
|
|
snprintf(buf, sizeof(buf), "Undefined register %s",
|
||
|
|
symbol->name);
|
||
|
|
stop(buf, EX_DATAERR);
|
||
|
|
/* NOTREACHED */
|
||
|
|
} else if (symbol->type == ALIAS) {
|
||
|
|
*p_symbol = symbol->info.ainfo->parent;
|
||
|
|
} else if ((symbol->type != REGISTER)
|
||
|
|
&& (symbol->type != SCBLOC)
|
||
|
|
&& (symbol->type != SRAMLOC)) {
|
||
|
|
snprintf(buf, sizeof(buf),
|
||
|
|
"Specified symbol %s is not a register",
|
||
|
|
symbol->name);
|
||
|
|
stop(buf, EX_DATAERR);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void
|
||
|
|
format_1_instr(opcode, dest, immed, src, ret)
|
||
|
|
int opcode;
|
||
|
|
symbol_ref_t *dest;
|
||
|
|
expression_t *immed;
|
||
|
|
symbol_ref_t *src;
|
||
|
|
int ret;
|
||
|
|
{
|
||
|
|
struct instruction *instr;
|
||
|
|
struct ins_format1 *f1_instr;
|
||
|
|
|
||
|
|
if (src->symbol == NULL)
|
||
|
|
src = dest;
|
||
|
|
|
||
|
|
/* Test register permissions */
|
||
|
|
test_writable_symbol(dest->symbol);
|
||
|
|
test_readable_symbol(src->symbol);
|
||
|
|
|
||
|
|
/* Ensure that immediate makes sense for this destination */
|
||
|
|
type_check(dest->symbol, immed, opcode);
|
||
|
|
|
||
|
|
/* Allocate sequencer space for the instruction and fill it out */
|
||
|
|
instr = seq_alloc();
|
||
|
|
f1_instr = &instr->format.format1;
|
||
|
|
f1_instr->opcode_ret = (opcode << 1) | (ret ? RETURN_BIT : 0);
|
||
|
|
f1_instr->destination = dest->symbol->info.rinfo->address
|
||
|
|
+ dest->offset;
|
||
|
|
f1_instr->source = src->symbol->info.rinfo->address
|
||
|
|
+ src->offset;
|
||
|
|
f1_instr->immediate = immed->value;
|
||
|
|
symlist_free(&immed->referenced_syms);
|
||
|
|
instruction_ptr++;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void
|
||
|
|
format_2_instr(opcode, dest, places, src, ret)
|
||
|
|
int opcode;
|
||
|
|
symbol_ref_t *dest;
|
||
|
|
expression_t *places;
|
||
|
|
symbol_ref_t *src;
|
||
|
|
int ret;
|
||
|
|
{
|
||
|
|
struct instruction *instr;
|
||
|
|
struct ins_format2 *f2_instr;
|
||
|
|
u_int8_t shift_control;
|
||
|
|
|
||
|
|
if (src->symbol == NULL)
|
||
|
|
src = dest;
|
||
|
|
|
||
|
|
/* Test register permissions */
|
||
|
|
test_writable_symbol(dest->symbol);
|
||
|
|
test_readable_symbol(src->symbol);
|
||
|
|
|
||
|
|
/* Allocate sequencer space for the instruction and fill it out */
|
||
|
|
instr = seq_alloc();
|
||
|
|
f2_instr = &instr->format.format2;
|
||
|
|
f2_instr->opcode_ret = (AIC_OP_ROL << 1) | (ret ? RETURN_BIT : 0);
|
||
|
|
f2_instr->destination = dest->symbol->info.rinfo->address
|
||
|
|
+ dest->offset;
|
||
|
|
f2_instr->source = src->symbol->info.rinfo->address
|
||
|
|
+ src->offset;
|
||
|
|
if (places->value > 8 || places->value <= 0) {
|
||
|
|
stop("illegal shift value", EX_DATAERR);
|
||
|
|
/* NOTREACHED */
|
||
|
|
}
|
||
|
|
switch (opcode) {
|
||
|
|
case AIC_OP_SHL:
|
||
|
|
if (places->value == 8)
|
||
|
|
shift_control = 0xf0;
|
||
|
|
else
|
||
|
|
shift_control = (places->value << 4) | places->value;
|
||
|
|
break;
|
||
|
|
case AIC_OP_SHR:
|
||
|
|
if (places->value == 8) {
|
||
|
|
shift_control = 0xf8;
|
||
|
|
} else {
|
||
|
|
shift_control = (places->value << 4)
|
||
|
|
| (8 - places->value)
|
||
|
|
| 0x08;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case AIC_OP_ROL:
|
||
|
|
shift_control = places->value & 0x7;
|
||
|
|
break;
|
||
|
|
case AIC_OP_ROR:
|
||
|
|
shift_control = (8 - places->value) | 0x08;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
shift_control = 0; /* Quiet Compiler */
|
||
|
|
stop("Invalid shift operation specified", EX_SOFTWARE);
|
||
|
|
/* NOTREACHED */
|
||
|
|
break;
|
||
|
|
};
|
||
|
|
f2_instr->shift_control = shift_control;
|
||
|
|
symlist_free(&places->referenced_syms);
|
||
|
|
instruction_ptr++;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void
|
||
|
|
format_3_instr(opcode, src, immed, address)
|
||
|
|
int opcode;
|
||
|
|
symbol_ref_t *src;
|
||
|
|
expression_t *immed;
|
||
|
|
symbol_ref_t *address;
|
||
|
|
{
|
||
|
|
struct instruction *instr;
|
||
|
|
struct ins_format3 *f3_instr;
|
||
|
|
int addr;
|
||
|
|
|
||
|
|
/* Test register permissions */
|
||
|
|
test_readable_symbol(src->symbol);
|
||
|
|
|
||
|
|
/* Ensure that immediate makes sense for this source */
|
||
|
|
type_check(src->symbol, immed, opcode);
|
||
|
|
|
||
|
|
/* Allocate sequencer space for the instruction and fill it out */
|
||
|
|
instr = seq_alloc();
|
||
|
|
f3_instr = &instr->format.format3;
|
||
|
|
if (address->symbol == NULL) {
|
||
|
|
/* 'dot' referrence. Use the current instruction pointer */
|
||
|
|
addr = instruction_ptr + address->offset;
|
||
|
|
} else if (address->symbol->type == UNINITIALIZED) {
|
||
|
|
/* forward reference */
|
||
|
|
addr = address->offset;
|
||
|
|
instr->patch_label = address->symbol;
|
||
|
|
} else
|
||
|
|
addr = address->symbol->info.linfo->address + address->offset;
|
||
|
|
f3_instr->opcode_addr = (opcode << 1)
|
||
|
|
| ((addr >> 8) & 0x01);
|
||
|
|
f3_instr->address = addr & 0xff;
|
||
|
|
f3_instr->source = src->symbol->info.rinfo->address
|
||
|
|
+ src->offset;
|
||
|
|
f3_instr->immediate = immed->value;
|
||
|
|
symlist_free(&immed->referenced_syms);
|
||
|
|
instruction_ptr++;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void
|
||
|
|
test_readable_symbol(symbol)
|
||
|
|
symbol_t *symbol;
|
||
|
|
{
|
||
|
|
if (symbol->info.rinfo->mode == WO) {
|
||
|
|
stop("Write Only register specified as source",
|
||
|
|
EX_DATAERR);
|
||
|
|
/* NOTREACHED */
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void
|
||
|
|
test_writable_symbol(symbol)
|
||
|
|
symbol_t *symbol;
|
||
|
|
{
|
||
|
|
if (symbol->info.rinfo->mode == RO) {
|
||
|
|
stop("Read Only register specified as destination",
|
||
|
|
EX_DATAERR);
|
||
|
|
/* NOTREACHED */
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void
|
||
|
|
type_check(symbol, expression, opcode)
|
||
|
|
symbol_t *symbol;
|
||
|
|
expression_t *expression;
|
||
|
|
int opcode;
|
||
|
|
{
|
||
|
|
symbol_node_t *node;
|
||
|
|
int and_op;
|
||
|
|
char buf[255];
|
||
|
|
|
||
|
|
and_op = FALSE;
|
||
|
|
if (opcode == AIC_OP_AND || opcode == AIC_OP_JNZ || AIC_OP_JZ)
|
||
|
|
and_op = TRUE;
|
||
|
|
/*
|
||
|
|
* Make sure that we aren't attempting to write something
|
||
|
|
* that hasn't been defined. If this is an and operation,
|
||
|
|
* this is a mask, so "undefined" bits are okay.
|
||
|
|
*/
|
||
|
|
if (and_op == FALSE
|
||
|
|
&& (expression->value & ~symbol->info.rinfo->valid_bitmask) != 0) {
|
||
|
|
snprintf(buf, sizeof(buf),
|
||
|
|
"Invalid bit(s) 0x%x in immediate written to %s",
|
||
|
|
expression->value & ~symbol->info.rinfo->valid_bitmask,
|
||
|
|
symbol->name);
|
||
|
|
stop(buf, EX_DATAERR);
|
||
|
|
/* NOTREACHED */
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Now make sure that all of the symbols referenced by the
|
||
|
|
* expression are defined for this register.
|
||
|
|
*/
|
||
|
|
if(symbol->info.rinfo->typecheck_masks != FALSE) {
|
||
|
|
for(node = expression->referenced_syms.slh_first;
|
||
|
|
node != NULL;
|
||
|
|
node = node->links.sle_next) {
|
||
|
|
if ((node->symbol->type == MASK
|
||
|
|
|| node->symbol->type == BIT)
|
||
|
|
&& symlist_search(&node->symbol->info.minfo->symrefs,
|
||
|
|
symbol->name) == NULL) {
|
||
|
|
snprintf(buf, sizeof(buf),
|
||
|
|
"Invalid bit or mask %s "
|
||
|
|
"for register %s",
|
||
|
|
node->symbol->name, symbol->name);
|
||
|
|
stop(buf, EX_DATAERR);
|
||
|
|
/* NOTREACHED */
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void
|
||
|
|
make_expression(immed, value)
|
||
|
|
expression_t *immed;
|
||
|
|
int value;
|
||
|
|
{
|
||
|
|
SLIST_INIT(&immed->referenced_syms);
|
||
|
|
immed->value = value & 0xff;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void
|
||
|
|
add_conditional(symbol)
|
||
|
|
symbol_t *symbol;
|
||
|
|
{
|
||
|
|
static int numoptions = 1;
|
||
|
|
|
||
|
|
if (symbol->type == UNINITIALIZED) {
|
||
|
|
symbol->type = CONDITIONAL;
|
||
|
|
initialize_symbol(symbol);
|
||
|
|
symbol->info.condinfo->value = 0x01 << numoptions++;
|
||
|
|
symlist_add(&patch_options, symbol, SYMLIST_INSERT_HEAD);
|
||
|
|
} else if (symbol->type != CONDITIONAL) {
|
||
|
|
stop("Conditional symbol mirrors other symbol",
|
||
|
|
EX_DATAERR);
|
||
|
|
/* NOTREACHED */
|
||
|
|
}
|
||
|
|
cur_patch->options |= symbol->info.condinfo->value;
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
yyerror(string)
|
||
|
|
const char *string;
|
||
|
|
{
|
||
|
|
stop(string, EX_DATAERR);
|
||
|
|
}
|