2017-04-27 19:40:53 +00:00
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/*-
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* BSD LICENSE
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*
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2020-05-26 15:04:49 +00:00
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* Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
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2017-04-27 19:40:53 +00:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef ENA_PLAT_H_
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#define ENA_PLAT_H_
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/condvar.h>
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#include <sys/endian.h>
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#include <sys/kernel.h>
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#include <sys/kthread.h>
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#include <sys/malloc.h>
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#include <sys/mbuf.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/proc.h>
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#include <sys/smp.h>
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#include <sys/socket.h>
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#include <sys/sockio.h>
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#include <sys/sysctl.h>
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#include <sys/taskqueue.h>
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#include <sys/eventhandler.h>
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#include <sys/types.h>
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#include <sys/timetc.h>
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#include <sys/cdefs.h>
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#include <machine/atomic.h>
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#include <machine/bus.h>
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#include <machine/in_cksum.h>
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#include <machine/pcpu.h>
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#include <machine/resource.h>
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2020-05-26 15:04:49 +00:00
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#include <machine/_inttypes.h>
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2017-04-27 19:40:53 +00:00
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#include <net/bpf.h>
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#include <net/ethernet.h>
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#include <net/if.h>
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#include <net/if_var.h>
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#include <net/if_arp.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/if_types.h>
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#include <net/if_vlan_var.h>
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#include <netinet/in_systm.h>
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#include <netinet/in.h>
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#include <netinet/if_ether.h>
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#include <netinet/ip.h>
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#include <netinet/ip6.h>
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#include <netinet/tcp.h>
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#include <netinet/tcp_lro.h>
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#include <netinet/udp.h>
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#include <dev/led/led.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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extern struct ena_bus_space ebs;
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/* Levels */
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#define ENA_ALERT (1 << 0) /* Alerts are providing more error info. */
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#define ENA_WARNING (1 << 1) /* Driver output is more error sensitive. */
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#define ENA_INFO (1 << 2) /* Provides additional driver info. */
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#define ENA_DBG (1 << 3) /* Driver output for debugging. */
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/* Detailed info that will be printed with ENA_INFO or ENA_DEBUG flag. */
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#define ENA_TXPTH (1 << 4) /* Allows TX path tracing. */
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#define ENA_RXPTH (1 << 5) /* Allows RX path tracing. */
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#define ENA_RSC (1 << 6) /* Goes with TXPTH or RXPTH, free/alloc res. */
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#define ENA_IOQ (1 << 7) /* Detailed info about IO queues. */
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#define ENA_ADMQ (1 << 8) /* Detailed info about admin queue. */
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2020-05-26 15:04:49 +00:00
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#define ENA_NETMAP (1 << 9) /* Detailed info about netmap. */
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2017-04-27 19:40:53 +00:00
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2017-11-09 11:37:20 +00:00
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extern int ena_log_level;
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2017-04-27 19:40:53 +00:00
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#define ena_trace_raw(level, fmt, args...) \
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do { \
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2017-11-09 11:37:20 +00:00
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if (((level) & ena_log_level) != (level)) \
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2017-04-27 19:40:53 +00:00
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break; \
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printf(fmt, ##args); \
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} while (0)
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#define ena_trace(level, fmt, args...) \
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ena_trace_raw(level, "%s() [TID:%d]: " \
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2019-05-30 12:27:55 +00:00
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fmt, __func__, curthread->td_tid, ##args)
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2017-04-27 19:40:53 +00:00
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#define ena_trc_dbg(format, arg...) ena_trace(ENA_DBG, format, ##arg)
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#define ena_trc_info(format, arg...) ena_trace(ENA_INFO, format, ##arg)
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#define ena_trc_warn(format, arg...) ena_trace(ENA_WARNING, format, ##arg)
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#define ena_trc_err(format, arg...) ena_trace(ENA_ALERT, format, ##arg)
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2020-05-26 15:04:49 +00:00
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#define unlikely(x) __predict_false(!!(x))
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#define likely(x) __predict_true(!!(x))
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2017-04-27 19:40:53 +00:00
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#define __iomem
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#define ____cacheline_aligned __aligned(CACHE_LINE_SIZE)
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#define MAX_ERRNO 4095
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#define IS_ERR_VALUE(x) unlikely((x) <= (unsigned long)MAX_ERRNO)
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#define ENA_ASSERT(cond, format, arg...) \
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do { \
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if (unlikely(!(cond))) { \
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ena_trc_err( \
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"Assert failed on %s:%s:%d:" format, \
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__FILE__, __func__, __LINE__, ##arg); \
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} \
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} while (0)
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#define ENA_WARN(cond, format, arg...) \
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do { \
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if (unlikely((cond))) { \
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ena_trc_warn(format, ##arg); \
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} \
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} while (0)
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static inline long IS_ERR(const void *ptr)
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{
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return IS_ERR_VALUE((unsigned long)ptr);
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}
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static inline void *ERR_PTR(long error)
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{
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return (void *)error;
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}
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static inline long PTR_ERR(const void *ptr)
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{
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return (long) ptr;
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}
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2019-05-30 12:27:55 +00:00
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#define GENMASK(h, l) (((~0U) - (1U << (l)) + 1) & (~0U >> (32 - 1 - (h))))
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2017-04-27 19:40:53 +00:00
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#define GENMASK_ULL(h, l) (((~0ULL) << (l)) & (~0ULL >> (64 - 1 - (h))))
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2018-05-10 09:18:26 +00:00
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#define BIT(x) (1UL << (x))
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2017-04-27 19:40:53 +00:00
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#define ENA_ABORT() BUG()
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#define BUG() panic("ENA BUG")
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#define SZ_256 (256)
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#define SZ_4K (4096)
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#define ENA_COM_OK 0
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#define ENA_COM_FAULT EFAULT
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#define ENA_COM_INVAL EINVAL
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#define ENA_COM_NO_MEM ENOMEM
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#define ENA_COM_NO_SPACE ENOSPC
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#define ENA_COM_TRY_AGAIN -1
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2017-10-31 12:20:48 +00:00
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#define ENA_COM_UNSUPPORTED EOPNOTSUPP
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2017-04-27 19:40:53 +00:00
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#define ENA_COM_NO_DEVICE ENODEV
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#define ENA_COM_PERMISSION EPERM
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#define ENA_COM_TIMER_EXPIRED ETIMEDOUT
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#define ENA_MSLEEP(x) pause_sbt("ena", SBT_1MS * (x), SBT_1MS, 0)
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2020-05-26 15:04:49 +00:00
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#define ENA_USLEEP(x) pause_sbt("ena", SBT_1US * (x), SBT_1US, 0)
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2017-04-27 19:40:53 +00:00
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#define ENA_UDELAY(x) DELAY(x)
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#define ENA_GET_SYSTEM_TIMEOUT(timeout_us) \
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((long)cputick2usec(cpu_ticks()) + (timeout_us))
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2020-05-26 15:04:49 +00:00
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#define ENA_TIME_EXPIRE(timeout) ((timeout) < cputick2usec(cpu_ticks()))
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2017-04-27 19:40:53 +00:00
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#define ENA_MIGHT_SLEEP()
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#define min_t(type, _x, _y) ((type)(_x) < (type)(_y) ? (type)(_x) : (type)(_y))
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#define max_t(type, _x, _y) ((type)(_x) > (type)(_y) ? (type)(_x) : (type)(_y))
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#define ENA_MIN32(x,y) MIN(x, y)
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#define ENA_MIN16(x,y) MIN(x, y)
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#define ENA_MIN8(x,y) MIN(x, y)
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#define ENA_MAX32(x,y) MAX(x, y)
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#define ENA_MAX16(x,y) MAX(x, y)
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#define ENA_MAX8(x,y) MAX(x, y)
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/* Spinlock related methods */
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#define ena_spinlock_t struct mtx
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#define ENA_SPINLOCK_INIT(spinlock) \
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mtx_init(&(spinlock), "ena_spin", NULL, MTX_SPIN)
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#define ENA_SPINLOCK_DESTROY(spinlock) \
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do { \
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if (mtx_initialized(&(spinlock))) \
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mtx_destroy(&(spinlock)); \
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} while (0)
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#define ENA_SPINLOCK_LOCK(spinlock, flags) \
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do { \
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(void)(flags); \
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mtx_lock_spin(&(spinlock)); \
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} while (0)
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#define ENA_SPINLOCK_UNLOCK(spinlock, flags) \
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do { \
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(void)(flags); \
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mtx_unlock_spin(&(spinlock)); \
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} while (0)
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/* Wait queue related methods */
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#define ena_wait_event_t struct { struct cv wq; struct mtx mtx; }
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#define ENA_WAIT_EVENT_INIT(waitqueue) \
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do { \
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cv_init(&((waitqueue).wq), "cv"); \
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mtx_init(&((waitqueue).mtx), "wq", NULL, MTX_DEF); \
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} while (0)
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#define ENA_WAIT_EVENT_DESTROY(waitqueue) \
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do { \
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cv_destroy(&((waitqueue).wq)); \
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mtx_destroy(&((waitqueue).mtx)); \
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} while (0)
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#define ENA_WAIT_EVENT_CLEAR(waitqueue) \
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cv_init(&((waitqueue).wq), (waitqueue).wq.cv_description)
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#define ENA_WAIT_EVENT_WAIT(waitqueue, timeout_us) \
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do { \
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mtx_lock(&((waitqueue).mtx)); \
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cv_timedwait(&((waitqueue).wq), &((waitqueue).mtx), \
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timeout_us * hz / 1000 / 1000 ); \
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mtx_unlock(&((waitqueue).mtx)); \
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} while (0)
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2018-05-10 09:18:26 +00:00
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#define ENA_WAIT_EVENT_SIGNAL(waitqueue) \
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do { \
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mtx_lock(&((waitqueue).mtx)); \
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cv_broadcast(&((waitqueue).wq)); \
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mtx_unlock(&((waitqueue).mtx)); \
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} while (0)
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2017-04-27 19:40:53 +00:00
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#define dma_addr_t bus_addr_t
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#define u8 uint8_t
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#define u16 uint16_t
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#define u32 uint32_t
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#define u64 uint64_t
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typedef struct {
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bus_addr_t paddr;
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caddr_t vaddr;
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bus_dma_tag_t tag;
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bus_dmamap_t map;
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bus_dma_segment_t seg;
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int nseg;
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} ena_mem_handle_t;
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struct ena_bus {
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bus_space_handle_t reg_bar_h;
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bus_space_tag_t reg_bar_t;
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bus_space_handle_t mem_bar_h;
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bus_space_tag_t mem_bar_t;
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};
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typedef uint32_t ena_atomic32_t;
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2020-05-26 15:04:49 +00:00
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#define ENA_PRIu64 PRIu64
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typedef uint64_t ena_time_t;
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2017-04-27 19:40:53 +00:00
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void ena_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nseg,
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int error);
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int ena_dma_alloc(device_t dmadev, bus_size_t size, ena_mem_handle_t *dma,
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int mapflags);
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2020-05-26 15:04:49 +00:00
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static inline uint32_t
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ena_reg_read32(struct ena_bus *bus, bus_size_t offset)
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{
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uint32_t v = bus_space_read_4(bus->reg_bar_t, bus->reg_bar_h, offset);
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rmb();
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return v;
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}
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2017-10-31 12:20:48 +00:00
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#define ENA_MEMCPY_TO_DEVICE_64(dst, src, size) \
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do { \
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int count, i; \
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volatile uint64_t *to = (volatile uint64_t *)(dst); \
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const uint64_t *from = (const uint64_t *)(src); \
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count = (size) / 8; \
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\
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for (i = 0; i < count; i++, from++, to++) \
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*to = *from; \
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} while (0)
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2017-04-27 19:40:53 +00:00
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#define ENA_MEM_ALLOC(dmadev, size) malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO)
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#define ENA_MEM_ALLOC_NODE(dmadev, size, virt, node, dev_node) (virt = NULL)
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2020-05-26 15:04:49 +00:00
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#define ENA_MEM_FREE(dmadev, ptr, size) \
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do { \
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(void)(size); \
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free(ptr, M_DEVBUF); \
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} while (0)
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2017-04-27 19:40:53 +00:00
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#define ENA_MEM_ALLOC_COHERENT_NODE(dmadev, size, virt, phys, handle, node, \
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dev_node) \
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|
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do { \
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((virt) = NULL); \
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(void)(dev_node); \
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|
} while (0)
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|
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|
|
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#define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, dma) \
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|
|
|
do { \
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|
|
|
ena_dma_alloc((dmadev), (size), &(dma), 0); \
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|
|
|
(virt) = (void *)(dma).vaddr; \
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|
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(phys) = (dma).paddr; \
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|
|
|
} while (0)
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|
|
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|
|
|
#define ENA_MEM_FREE_COHERENT(dmadev, size, virt, phys, dma) \
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|
|
|
do { \
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|
|
(void)size; \
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|
|
|
bus_dmamap_unload((dma).tag, (dma).map); \
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|
|
bus_dmamem_free((dma).tag, (virt), (dma).map); \
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|
|
bus_dma_tag_destroy((dma).tag); \
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|
|
|
(dma).tag = NULL; \
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|
|
(virt) = NULL; \
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
/* Register R/W methods */
|
|
|
|
#define ENA_REG_WRITE32(bus, value, offset) \
|
2020-05-26 15:04:49 +00:00
|
|
|
do { \
|
|
|
|
wmb(); \
|
|
|
|
ENA_REG_WRITE32_RELAXED(bus, value, offset); \
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
#define ENA_REG_WRITE32_RELAXED(bus, value, offset) \
|
2017-04-27 19:40:53 +00:00
|
|
|
bus_space_write_4( \
|
|
|
|
((struct ena_bus*)bus)->reg_bar_t, \
|
|
|
|
((struct ena_bus*)bus)->reg_bar_h, \
|
|
|
|
(bus_size_t)(offset), (value))
|
|
|
|
|
|
|
|
#define ENA_REG_READ32(bus, offset) \
|
2020-05-26 15:04:49 +00:00
|
|
|
ena_reg_read32((struct ena_bus*)(bus), (bus_size_t)(offset))
|
2017-04-27 19:40:53 +00:00
|
|
|
|
2019-05-30 12:27:55 +00:00
|
|
|
#define ENA_DB_SYNC_WRITE(mem_handle) bus_dmamap_sync( \
|
|
|
|
(mem_handle)->tag, (mem_handle)->map, BUS_DMASYNC_PREWRITE)
|
|
|
|
#define ENA_DB_SYNC_PREREAD(mem_handle) bus_dmamap_sync( \
|
|
|
|
(mem_handle)->tag, (mem_handle)->map, BUS_DMASYNC_PREREAD)
|
|
|
|
#define ENA_DB_SYNC_POSTREAD(mem_handle) bus_dmamap_sync( \
|
|
|
|
(mem_handle)->tag, (mem_handle)->map, BUS_DMASYNC_POSTREAD)
|
|
|
|
#define ENA_DB_SYNC(mem_handle) ENA_DB_SYNC_WRITE(mem_handle)
|
2017-10-31 12:20:48 +00:00
|
|
|
|
2017-04-27 19:40:53 +00:00
|
|
|
#define time_after(a,b) ((long)((unsigned long)(b) - (unsigned long)(a)) < 0)
|
|
|
|
|
|
|
|
#define VLAN_HLEN sizeof(struct ether_vlan_header)
|
|
|
|
#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP)
|
|
|
|
|
2019-05-30 12:27:55 +00:00
|
|
|
#define prefetch(x) (void)(x)
|
|
|
|
#define prefetchw(x) (void)(x)
|
2017-04-27 19:40:53 +00:00
|
|
|
|
|
|
|
/* DMA buffers access */
|
|
|
|
#define dma_unmap_addr(p, name) ((p)->dma->name)
|
|
|
|
#define dma_unmap_addr_set(p, name, v) (((p)->dma->name) = (v))
|
|
|
|
#define dma_unmap_len(p, name) ((p)->name)
|
|
|
|
#define dma_unmap_len_set(p, name, v) (((p)->name) = (v))
|
|
|
|
|
|
|
|
#define memcpy_toio memcpy
|
|
|
|
|
|
|
|
#define ATOMIC32_INC(I32_PTR) atomic_add_int(I32_PTR, 1)
|
|
|
|
#define ATOMIC32_DEC(I32_PTR) atomic_add_int(I32_PTR, -1)
|
|
|
|
#define ATOMIC32_READ(I32_PTR) atomic_load_acq_int(I32_PTR)
|
|
|
|
#define ATOMIC32_SET(I32_PTR, VAL) atomic_store_rel_int(I32_PTR, VAL)
|
|
|
|
|
|
|
|
#define barrier() __asm__ __volatile__("": : :"memory")
|
2019-05-30 12:27:55 +00:00
|
|
|
#define dma_rmb() barrier()
|
|
|
|
#define mmiowb() barrier()
|
|
|
|
|
2017-04-27 19:40:53 +00:00
|
|
|
#define ACCESS_ONCE(x) (*(volatile __typeof(x) *)&(x))
|
|
|
|
#define READ_ONCE(x) ({ \
|
|
|
|
__typeof(x) __var; \
|
|
|
|
barrier(); \
|
|
|
|
__var = ACCESS_ONCE(x); \
|
|
|
|
barrier(); \
|
|
|
|
__var; \
|
|
|
|
})
|
2019-05-30 12:27:55 +00:00
|
|
|
#define READ_ONCE8(x) READ_ONCE(x)
|
|
|
|
#define READ_ONCE16(x) READ_ONCE(x)
|
|
|
|
#define READ_ONCE32(x) READ_ONCE(x)
|
|
|
|
|
|
|
|
#define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16))
|
|
|
|
#define lower_32_bits(n) ((uint32_t)(n))
|
|
|
|
|
|
|
|
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
|
2017-04-27 19:40:53 +00:00
|
|
|
|
2020-05-26 15:04:49 +00:00
|
|
|
#define ENA_FFS(x) ffs(x)
|
|
|
|
|
|
|
|
void ena_rss_key_fill(void *key, size_t size);
|
|
|
|
|
|
|
|
#define ENA_RSS_FILL_KEY(key, size) ena_rss_key_fill(key, size)
|
|
|
|
|
2017-10-31 12:20:48 +00:00
|
|
|
#include "ena_defs/ena_includes.h"
|
2017-04-27 19:40:53 +00:00
|
|
|
|
|
|
|
#endif /* ENA_PLAT_H_ */
|