2002-06-05 19:52:45 +00:00
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/*
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* Core definitions and data structures shareable across OS platforms.
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*
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2002-08-31 06:48:42 +00:00
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* Copyright (c) 1994-2002 Justin T. Gibbs.
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* Copyright (c) 2000-2002 Adaptec Inc.
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2002-06-05 19:52:45 +00:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* substantially similar to the "NO WARRANTY" disclaimer below
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* ("Disclaimer") and any redistribution must be conditioned upon
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* including a substantially similar Disclaimer requirement for further
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* binary redistribution.
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* 3. Neither the names of the above-listed copyright holders nor the names
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* of any contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2 as published by the Free
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* Software Foundation.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGES.
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*
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aic79xx.c:
Allow 500us between pauses in ahd_pause_and_flushwork().
The maximum we will wait is now 500ms.
In the same routine, remove any attempt to clear ENSELO.
Let the firmware do it once the current selection has
completed. This avoids some race conditions having to
do with non-packetized completions and the auto-clearing
of ENSELO on packetized completions.
Also avoid attempts to clear critical sections when
interrups are pending. We are going to loop again
anyway, so clearing critical sections is a waste of
time. It also may not be possible to clear a critical
section if the source of the interrupt was a SEQINT.
aic79xx_pci.c:
Use the Generic 9005 mask when looking for generic 7901B
parts. This allows the driver to attach to 7901B parts
on motherboards using a non-Adaptec subvendor ID.
aic79xx_inline.h:
Test for the SCBRAM_RD_BUG against the bugs
field, not the flags field in the softc.
aic79xx.c:
Cancel pending transactions on devices that
respond with a selection timeout. This decreases
the duration of timeout recovery when a device
disappears.
aic79xx.c:
Don't bother forcing renegotiation on a selection
timeout now that we use the device reset handler
to abort any pending commands on the target.
The device reset handler already takes us down
to async narrow and forces a renegotiation.
In the device reset handlers, only send a
BDR sent async event if the status is not
CAM_SEL_TIMEOUT. This avoids sending this
event in the selection timeout case
aic79xx.c:
Modify the Core timeout handler to verify that another
command has the potential to timeout before passing off
a command timeout as due to some other command. This
safety measure is added in response to a timeout recovery
failure on H2B where it appears that incoming reselection
status was lost during a drive pull test. In that case,
the recovery handler continued to wait for the command
that was active on the bus indefinetly. While the root
cause of the above issue is still being determined seems
a prudent safeguard.
aic79xx_pci.c:
Add a specific probe entry for the Dell OEM 39320(B).
aic79xx.c:
aic79xx.h:
aic79xx.reg:
aic79xx.seq:
Modify the aic79xx firmware to never cross a cacheline or
ADB boundary when DMA'ing completion entries to the host.
In PCI mode, at least in 32/33 configurations, the SCB
DMA engine may lose its place in the data-stream should
the target force a retry on something other than an
8byte aligned boundary. In PCI-X mode, we do this to
avoid split transactions since many chipsets seem to be
unable to format proper split completions to continue
the data transfer.
The above change allows us to drop our completion entries
from 8 bytes to 4. We were using 8 byte entries to ensure
that PCI retries could only occur on an 8byte aligned
boundary. Now that the sequencer guarantees this by splitting
up completions, we can safely drop the size to 4 bytes (2
byte tag, one byte SG_RESID, one byte pad).
Both the split-completion and PCI retry problems only show
up under high tag load when interrupt coalescing is being
especially effective. The switch from a 2byte completion
entry to an 8 byte entry to solve the PCI problem increased
the chance of incurring a split in PCI-X mode when multiple
transactions were completed at once. Dropping the completion
size to 4 bytes also means that we can complete more commands
in a single DMA (128byte FIFO -> 32 commands instead of 16).
aic79xx.c:
Modify the SCSIINT handler to defer clearing
sequencer critical sections to the individual
interrupt handlers. This allows us to
immediately disable any outgoing selections in
the case of an unexpected busfree so we don't
inadvertantly clear ENSELO *after* a new selection
has started. Doing so may cause the sequencer
to miss a successful selection.
In ahd_update_pending_scbs(), only clear ENSELO if
the bus is currently busy and a selection is not
already in progress or the sequencer has yet to
handle a pending selection. While we want to ensure
that the selection for the SCB at the head of the
selection queue is restarted so that any change in
negotiation request can take effect, we can't clobber
pending selection state without confusing the sequencer
into missing a selection.
2004-05-11 20:46:05 +00:00
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* $Id: //depot/aic7xxx/aic7xxx/aic79xx.h#107 $
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2002-06-05 19:52:45 +00:00
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*
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* $FreeBSD$
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*/
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#ifndef _AIC79XX_H_
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#define _AIC79XX_H_
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/* Register Definitions */
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#include "aic79xx_reg.h"
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/************************* Forward Declarations *******************************/
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struct ahd_platform_data;
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struct scb_platform_data;
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/****************************** Useful Macros *********************************/
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#ifndef MAX
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#define MAX(a,b) (((a) > (b)) ? (a) : (b))
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#endif
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#ifndef MIN
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#define MIN(a,b) (((a) < (b)) ? (a) : (b))
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#endif
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#ifndef TRUE
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#define TRUE 1
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#endif
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#ifndef FALSE
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#define FALSE 0
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#endif
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#define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array))
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#define ALL_CHANNELS '\0'
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#define ALL_TARGETS_MASK 0xFFFF
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#define INITIATOR_WILDCARD (~0)
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#define SCB_LIST_NULL 0xFF00
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ahc_eisa.c:
ahc_pci.c:
ahd_pci.c:
aic7xxx.c:
aic79xx.c:
aic_osm_lib.c:
aic_osm_lib.h:
Use common OSM routines from aic_osm_lib for bus dma operations,
delay routines, accessing CCBs, byte swapping, etc.
aic7xxx_pci.c:
Provide a better description for the 2915/30LP on attach.
aic7xxx.c:
aic79xx.c:
aic7770.c:
aic79xx_pci.c:
aic7xxx_pci.c:
aic7xxx_93cx6.c:
Move FBSDID behind an ifdef so that these core files will
still compile under other OSes.
aic79xx.h:
aic79xx_pci.c:
aic79xx.seq:
To speed up non-packetized CDB delivery in Rev B, all CDB
acks are "released" to the output sync as soon as the
command phase starts. There is only one problem with this
approach. If the target changes phase before all data are
sent, we have left over acks that can go out on the bus in
a data phase. Due to other chip contraints, this only
happens if the target goes to data-in, but if the acks go
out before we can test SDONE, we'll think that the transfer
has completed successfully. Work around this by taking
advantage of the 400ns or 800ns dead time between command
phase and the REQ of the new phase. If the transfer has
completed successfully, SCSIEN should fall *long* before we
see a phase change. We thus treat any phasemiss that
occurs before SCSIEN falls as an incomplete transfer.
aic79xx.h:
Add the AHD_FAST_CDB_DELIVERY feature.
aic79xx_pci.c:
Set AHD_FAST_CDB_DELIVERY for all Rev. B parts.
aic79xx.seq:
Test for PHASEMIS in the command phase for
all AHD_FAST_CDB_DELIVERY controlelrs.
ahd_pci.c:
ahc_pci.c:
aic7xxx.h:
aic79xx.h:
Move definition of controller BAR offsets to core header files.
aic7xxx.c:
aic79xx.c:
In the softc free routine, leave removal of a softc from the
global list of softcs to the OSM (the caller of this routine).
This allows us to avoid holding the softc list_lock during device
destruction where we may have to sleep waiting for our recovery
thread to halt.
ahc_pci.c:
Use ahc_pci_test_register access to validate I/O mapped in
addition to the tests already performed for memory mapped
access.
Remove unused ahc_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
ahd_pci.c:
Remove reduntant definition of controller BAR offsets. These
are also defined in aic79xx.h.
Remove unused ahd_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
aic7xxx.c:
aic79xx.c:
aic79xx.h:
aic7xxx.h:
aic7xxx_osm.c:
aic79xx_osm.c:
Move timeout handling to the driver cores. In the case
of the aic79xx driver, the algorithm has been enhanced
to try target resets before performing a bus reset. For
the aic7xxx driver, the algorithm is unchanged. Although
the drivers do not currently sleep during recovery (recovery
is timeout driven), the cores do expect all processing to
be performed via a recovery thread. Our timeout handlers
are now little stubs that wakeup the recovery thread.
aic79xx.c:
aic79xx.h:
aic79xx_inline.h:
Change shared_data allocation to use a map_node so
that the sentinel hscb can use this map node in
ahd_swap_with_next_hscb. This routine now swaps
the hscb_map pointer in additon to the hscb
contents so that any sync operations occur on
the correct map.
physaddr -> busaddr
Pointed out by: Jason Thorpe <thorpej@wasabisystems.com>
aic79xx.c:
Make more use of the in/out/w/l/q macros for accessing
byte registers in the chip.
Correct some issues in the ahd_flush_qoutfifo() routine.
o Run the qoutfifo only once the command channel
DMA engine has been halted. This closes a window
where we might have missed some entries.
o Change ahd_run_data_fifo() to not loop to completion.
If we happen to start on the wrong FIFO and the other
FIFO has a snapshot savepointers, we might deadlock.
This required our delay between FIFO tests to be
moved to the ahd_flush_qoutfifo() routine.
o Update/add comments.
o Remove spurious test for COMPLETE_DMA list being empty
when completing transactions from the GSFIFO with
residuals. The SCB must be put on the COMPLETE_DMA
scb list unconditionally.
o When halting command channel DMA activity, we must
disable the DMA channel in all cases but an update
of the QOUTFIFO. The latter case is required so
that the sequencer will update its position in the
QOUTFIFO. Previously, we left the channel enabled
for all "push" DMAs. This left us vulnerable to
the sequencer handling an SCB push long after that
SCB was already processed manually by this routine.
o Correct the polarity of tests involving
ahd_scb_active_in_fifo(). This routine returns
non-zero for true.
Return to processing bad status completions through
the qoutfifo. This reduces the time that the sequencer
is kept paused when handling transactions with bad
status or underruns.
When waiting for the controller to quiece selections,
add a delay to our loop. Otherwise we may fail to wait
long enough for the sequencer to comply.
On H2A4 hardware, use the slow slewrate for non-paced
transfers. This mirrors what the Adaptec Windows
drivers do.
On the Rev B. only slow down the CRC timing for
older U160 devices that might need the slower timing.
We define "older" as devices that do not support
packetized protocol.
Wait up to 5000 * 5us for the SEEPROM to become unbusy.
Write ops seem to take much longer than read ops.
aic79xx.seq:
For controllers with the FAINT_LED bug, turn the diagnostic
led feature on during selection and reselection. This covers
the non-packetized case. The LED will be disabled for
non-packetized transfers once we return to the top level idle
loop. Add more comments about the busy LED workaround.
Extend a critical section around the entire
command channel idle loop process. Previously
the portion of this handler that directly manipulated
the linked list of completed SCBs was not protected.
This is the likely cause of the recent reports of
commands being completed twice by the driver.
Extend critical sections across the test for,
and the longjump to, longjump routines. This
prevents the firmware from trying to jump to
a longjmp handler that was just cleared by the
host.
Improve the locations of several critical section
begin and end points. Typically these changes
remove instructions that did not need to be
inside a critical section.
Close the "busfree after selection, but before busfree
interrupts can be enabled" race to just a single sequencer
instruction. We now test the BSY line explicitly before
clearing the busfree status and enabling the busfree
interrupt.
Close a race condition in the processing of HS_MAILBOX
updates. We now clear the "updated" status before the
copy. This ensures that we don't accidentally clear
the status incorrectly when the host sneaks in an update
just after our last copy, but before we clear the status.
This race has never been observed.
Don't re-enable SCSIEN if we lose the race to disable SCSIEN
in our interrupt handler's workaround for the RevA data-valid
too early issue.
aic79xx_inline.h:
Add comments indicating that the order in which bytes are
read or written in ahd_inw and ahd_outw is important. This
allows us to use these inlines when accessing registers with
side-effects.
aic79xx_pci.c:
The 29320 and the 29320B are 7902 not 7901 based products.
Correct the driver banner.
aic7xxx.h:
Enable the use of the auto-access pause feature
on the aic7870 and aic7880. It was disabled due
to an oversight.
aic7xxx.reg:
Move TARG_IMMEDIATE_SCB to alias LAST_MSG to
avoid leaving garbage in MWI_RESIDUAL. This
prevents spurious overflows whn operating target
mode on controllers that require the MWI_RESIDUAL
work-around.
aic7xxx.seq:
AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag.
Reference the correct softc field when testing
for its presence.
Set the NOT_IDENTIFIED and NO_CDB_SENT bits
in SEQ_FLAGS to indicate that the nexus is
invalid in await busfree.
aic7xxx_93cx6.c:
Add support for the C56/C66 versions of the EWEN and EWDS
commands.
aic7xxx.c:
aic7xxx_pci.c:
Move test for the validity of left over BIOS data
to ahc_test_register_access(). This guarantees that
any left over CHIPRST value is not clobbered by our
register access test and lost to the test that was
in ahc_reset.
2003-12-17 00:02:10 +00:00
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#define SCB_LIST_NULL_LE (aic_htole16(SCB_LIST_NULL))
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aic79xx.c:
aic79xx.seq:
Convert the COMPLETE_DMA_SCB list to an "stailq". This allows us to
safely keep the SCB that is currently being DMA'ed back the host on
the head of the list while processing completions off of the bus. The
newly completed SCBs are appended to the tail of the queue. In the
past, we just dequeued the SCB that was in flight from the list, but
this could result in a lost completion should the host perform certain
types of error recovery that must cancel all in-flight SCB DMA operations.
Switch from using a 16bit completion entry, holding just the tag and the
completion valid bit, to a 64bit completion entry that also contains a
"status packet valid" indicator. This solves two problems:
o The SCB DMA engine on at least Rev B. silicon does not properly deal
with a PCI disconnect that occurs at a non-64bit aligned offset in the
chips "source buffer". When the transfer is resumed, the DMA engine
continues at the correct offset, but may wrap to the head of the buffer
causing duplicate completions to be reported to the host. By using a
completion buffer in host memory that is 64bit aligned and using 64bit
completion entries, such disconnects should only occur at aligned addresses.
This assumes that the host bridge will only disconnect on cache-line
boundaries and that cache-lines are multpiles of 64bits.
o By embedding the status information in the completion entry we can avoid
an extra memory reference to the HSCB for commands that complete without
error.
Use the comparison of a "host freeze count" and a "sequencer freeze count"
to allow the host to process most SCBs that complete with non-zero status
without having to clear critical sections. Instead the host can just pause the
sequencer, performs any necessary cleanup in the waiting for selection list,
increments its freeze count on the controller, and unpauses. This is only
possible because the sequencer defers completions of SCBs with bad status
until after all pending selections have completed. The sequencer then avoids
referencing any data structures the host may touch during completion of the
SCB until the freeze counts match.
aic79xx.c:
Change the strategy for allocating our sentinal HSCB for the QINFIFO. In
the past, this allocation was tacked onto the QOUTFIFO allocation. Now that
the qoutfifo has grown to accomodate larger completion entries, the old
approach will result in a 64byte allocation that costs an extra page of
coherent memory. We now do this extra allocation via ahd_alloc_scbs()
where the "unused space" can be used to allocate "normal" HSCBs.
In our packetized busfree handler, use the ENSELO bit to differentiate
between packetized and non-packetized unexpected busfree events that
occur just after selection, but before the sequencer has had the oportunity
to service the selection.
When cleaning out the waiting for selection list, use the SCSI mode
instead of the command channel mode. The SCB pointer in the command
channel mode may be referenced by the SCB dma engine even while the
sequencer is paused, whereas the SCSI mode SCB pointer is only accessed
by the sequencer.
Print the "complete on qfreeze" sequencer SCB completion list in
ahd_dump_card_state(). This list holds all SCB completions that are deferred
until a pending select-out qfreeze event has taken effect.
aic79xx.h:
Add definitions and structures to handle the new SCB completion scheme.
Add a controller flag that indicates if the controller is in HostRAID
mode.
aic79xx.reg:
Remove macros used for toggling from one data fifo mode to the other.
They have not been in use for some time.
Add scratch ram fields for our new qfreeze count scheme, converting
the complete dma list into an "stailq", and providing for the "complete
on qfreeze" SCB completion list. Some other fields were moved to retain
proper field alignment (alignment >= field size in bytes).
aic79xx.seq:
Add code to our idle loop to:
o Process deferred completions once a qfreeze event has taken full
effect.
o Thaw the queue once the sequencer and host qfreeze counts match.
Generate 64bit completion entries passing the SCB_SGPTR field as the
"good status" indicator. The first bit in this field is only set if
we have a valid status packet to send to the host.
Convert the COMPLETE_DMA_SCB list to an "stailq".
When using "setjmp" to register an idle loop handler, do not combine
the "ret" with the block move to pop the stack address in the same
instruction. At least on the A, this results in a return to the setjmp
caller, not to the new address at the top of the stack. Since we want
the latter (we want the newly registered handler to only be invoked from
the idle loop), we must use a separate ret instruction.
Add a few missing critical sections.
Close a race condition that can occur on Rev A. silicon. If both FIFOs
happen to be allocated before the sequencer has a chance to service the
FIFO that was allocated first, we must take special care to service the
FIFO that is not active on the SCSI bus first. This guarantees that a
FIFO will be freed to handle any snapshot requests for the FIFO that is
still on the bus. Chosing the incorrect FIFO will result in deadlock.
Update comments.
aic79xx_inline.h
Correct the offset calculation for the syncing of our qoutfifo.
Update ahd_check_cmdcmpltqueues() for the larger completion entries.
aic79xx_pci.c:
Attach to HostRAID controllers by default. In the future I may add a
sysctl to modify the behavior, but since FreeBSD does not have any
HostRAID drivers, failing to attach just results in more email and
bug reports for the author.
MFC After: 1week
2004-02-04 16:38:38 +00:00
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#define QOUTFIFO_ENTRY_VALID 0x80
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2002-06-05 19:52:45 +00:00
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#define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL)
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#define SCSIID_TARGET(ahd, scsiid) \
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(((scsiid) & TID) >> TID_SHIFT)
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#define SCSIID_OUR_ID(scsiid) \
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((scsiid) & OID)
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#define SCSIID_CHANNEL(ahd, scsiid) ('A')
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#define SCB_IS_SCSIBUS_B(ahd, scb) (0)
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#define SCB_GET_OUR_ID(scb) \
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SCSIID_OUR_ID((scb)->hscb->scsiid)
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#define SCB_GET_TARGET(ahd, scb) \
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SCSIID_TARGET((ahd), (scb)->hscb->scsiid)
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#define SCB_GET_CHANNEL(ahd, scb) \
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SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid)
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#define SCB_GET_LUN(scb) \
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((scb)->hscb->lun)
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#define SCB_GET_TARGET_OFFSET(ahd, scb) \
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SCB_GET_TARGET(ahd, scb)
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#define SCB_GET_TARGET_MASK(ahd, scb) \
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(0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb)))
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aic79xx.c:
Implement the SCB_SILENT flag. This is useful for
hushing up the driver during DV or other operations
that we expect to cause transmission errors. The
messages will still print if the SHOW_MASKED_ERRORS
debug option is enabled.
Save and restore the NEGOADDR address when setting
new transfer settings. The sequencer performs lookups
in the negotiation table too and it expects NEGOADDR
to remain consistent across pause/unpause sessions.
Consistently use "offset" instead of "period" to determine
if we are running sync or not.
Add a SHOW_MESSAGES diagnostic for when we assert ATN
during message processing.
Print out IU, QAS, and RTI features when showing transfer options.
Limit the syncrate after all option conformance
changes have taken place in ahd_devlimited_syncrate.
Changes in options may change the final syncrate we
accept.
Keep a copy of the hs_mailbox in our softc so that
we can perform read/modify/write operations on the
hs_mailbox without having to pause the sequencer to
read the last written value. Use the ENINT_COALESS
flag in the hs_mailbox to toggle interrupt coalessing.
Add entrypoints for enabling interrupt coalessing and
setting both a timeout (how long to wait for commands
to be coalessed) and a maximum commands to coaless value.
Add a statistics timer that decides when to enable or
disable interrupt coalessing based on load.
Add a routine, ahd_reset_cmds_pending() which is used
to update the CMDS_PENDING sequencer variable whenever
error recovery compeltes SCBs without notifying the
sequencer. Since ahd_reset_cmds_pending is called
during ahd_unpause() only if we've aborted SCBs, its
call to ahd_flush_qoutfifo should not cause recursion
through ahd_run_qoutfifo(). A panic has been added to
ensure that this recursion does not occur.
In ahd_search_qinfifo, update the CMDS_PENDING sequencer
variable directly. ahd_search_qinififo can be called
in situations where using ahd_reset_cmds_pending() might
cause recursion. Since we can safely determine the
exact number to reduce CMDS_PENDING by in this scenario
without running the qoutfifo, the manual update is sufficient.
Clean up diagnostics.
Add ahd_flush_qoutfifo() which will run the qoutfifo
as well as complete any commands sitting on the
sequencer's COMPLETE_SCB lists or the good status FIFO.
Use this routine in several places that did similar
things in an add-hoc, but incomplete, fashion. A call
to this routine was also added to ahd_abort_scbs() to
close a race.
In ahd_pause_and_flushwork() only return once selections
are safely disabled. Flush all completed commands via
ahd_flush_qoutfifo().
Remove "Now packetized" diagnostic now that this
information is incorperated into the actual negotiation
messages that are displayed.
When forcing renegotiation, don't clober the current
ppr_options. Much of the driver uses this information
to determine if we are currently packetized or not.
Remove some stray spaces at column 1 in ahd_set_tags.
When complaining about getting a host message loop
request with no pending messages, print out the
SCB_CONTROL register down on the card.
Modify the ahd_sent_msg() routine to handle a search
for an outgoing identify message. Use this to detect
a msg reject on an identify message which typically
indicates that the target thought we were packetized.
Force a renegotiation in this case.
In ahd_search_qinfifo(), wait more effectively for SCB
DMA activities to cease. We also disable SCB fetch
operations since we are about to change the qinfifo
and any fetch in progress will likely be invalidated.
In ahd_qinfifo_count(), fix the qinfifo empty case.
In ahd_dump_card_state(), print out CCSCBCTL in the
correct mode.
If we are a narrow controller, don't set the current
width to unknown when forcing a future negotiation.
This just confuses the code into attempting a wide
negotiation on a narrow bus.
Add support for task management function completions.
Modify ahd_handle_devreset so that it can handle
lun resets in addition to target resets. Use
ahd_handle_devreset for lun and target reset task
management functions.
Handle the abort task TMF race case better. We now
wait until any current selections are over and then
set the TMF back to zero. This should cause the sequencer
to ignore the abort TMF completion should it occur.
Correct a bug in the illegal phase handler that
caused us to drop down to narrow when handling the
unexpected command phase case after 3rd party
reset of a packetized device.
Indicate the features, bugs, and flags set in the softc
that are used to control firmware patch download when
booting verbose.
aic79xx.h:
Add coalessing and HS_MAILBOX fields.
Add per-softc variables for the stats "daemon".
Add a debug option for interrupt coalessing activities.
Add two new softc flags:
o AHD_UPDATE_PEND_CMDS
Run ahd_reset_cmds_pending() on the next unpause.
o AHD_RUNNING_QOUTFIFO
Used to catch recursion through ahd_run_qoutfifo().
aic79xx.reg:
Correct register addresses related to the software timer
and the DFDBCTL register.
Add constants paramaterizing the software timer.
Add scratch ram locations for storing interrupt coalessing
tunables.
Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2.
In at least the REV A, these are writable bits. We make
use of that for a swtimer workaround in the sequencer.
Since HS_MAILBOX autoclears, provide a sequencer variable
to store its contents.
Add SEQINT codes for handling task management completions.
aic79xx.seq:
Correct ignore wide residue processing check for
a wide negotiation being in effect. We must be
in the SCSI register window in order to access the
negotiation table.
Use the software timer and a commands completed count to
implement interrupt coalessing. The command complete is
deferred until either the maximum command threshold or a
the expiration of a command deferral timer. If we have
more SCBs to complete to the host (sitting in COMPLETE_SCB
lists), always try to coaless them up to our coalessing limit.
If coalessing is enabled, but we have fewer commands oustanting
than the host's min coalessing limit, complete the command
immediately.
Add code to track the number of commands outstanding.
Commands are outstanding from the time they are placed
into the execution queue until the DMA to post completion
is setup.
Add a workaround for intvec_2 interrupts on the H2A4.
In H2A4, the mode pointer is not saved for intvec2, but
is restored on iret. This can lead to the restoration
of a bogus mode ptr. Manually clear the intmask bits and
do a normal return to compensate. We use intvec_2 to
track interrupt coalessing timeouts.
Since we cannot disable the swtimer's countdown, simply
mask its interrupt once we no longer care about it firing.
In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime
we are notified of an HS_MAILBOX update via the
HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a
local copy of persistant portions of the HS_MAILBOX as
the mailbox auto-clears on any read.
Move the test for the cfg4istat interrupt up an instruction
to hopefully close a race between the next outgoing selection
and our disabling of selections.
Add a missing ret to the last instruction in load_overrun_buf.
Add notifications to the host of task management
completions as well as the completions for commands
that completed successfully before their corresponding
TMF could be sent.
Hold a critical section during select-out processing
until we have a fully identified connection. This
removes a race condition with the legacy abort handler.
Correct a few spelling errors in some comments.
aic79xx_inline.h:
Call ahd_reset_cmds_pending() in ahd_unpause if required.
Update cmdcmplt interrupt statistics in our interrupt
handler.
Allow callers to ahd_send_scb() to set the task management
function.
aic79xx_pci.c:
Disable SERR and pause the controller prior to performing
our mmapped I/O test. The U320 controllers do not support
"auto-access-pause".
aic79xx_osm.c:
Set the task management function now that
ahd_send_scb() doesn't do it for us. We
also perform a lun reset in response to BDR
requests to packetized devices.
2003-01-20 20:17:35 +00:00
|
|
|
#ifdef AHD_DEBUG
|
|
|
|
|
#define SCB_IS_SILENT(scb) \
|
|
|
|
|
((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \
|
|
|
|
|
&& (((scb)->flags & SCB_SILENT) != 0))
|
|
|
|
|
#else
|
|
|
|
|
#define SCB_IS_SILENT(scb) \
|
|
|
|
|
(((scb)->flags & SCB_SILENT) != 0)
|
|
|
|
|
#endif
|
2002-06-05 19:52:45 +00:00
|
|
|
/*
|
|
|
|
|
* TCLs have the following format: TTTTLLLLLLLL
|
|
|
|
|
*/
|
|
|
|
|
#define TCL_TARGET_OFFSET(tcl) \
|
|
|
|
|
((((tcl) >> 4) & TID) >> 4)
|
|
|
|
|
#define TCL_LUN(tcl) \
|
2002-08-31 06:48:42 +00:00
|
|
|
(tcl & (AHD_NUM_LUNS - 1))
|
2002-06-05 19:52:45 +00:00
|
|
|
#define BUILD_TCL(scsiid, lun) \
|
|
|
|
|
((lun) | (((scsiid) & TID) << 4))
|
|
|
|
|
#define BUILD_TCL_RAW(target, channel, lun) \
|
|
|
|
|
((lun) | ((target) << 8))
|
|
|
|
|
|
|
|
|
|
#define SCB_GET_TAG(scb) \
|
ahc_eisa.c:
ahc_pci.c:
ahd_pci.c:
aic7xxx.c:
aic79xx.c:
aic_osm_lib.c:
aic_osm_lib.h:
Use common OSM routines from aic_osm_lib for bus dma operations,
delay routines, accessing CCBs, byte swapping, etc.
aic7xxx_pci.c:
Provide a better description for the 2915/30LP on attach.
aic7xxx.c:
aic79xx.c:
aic7770.c:
aic79xx_pci.c:
aic7xxx_pci.c:
aic7xxx_93cx6.c:
Move FBSDID behind an ifdef so that these core files will
still compile under other OSes.
aic79xx.h:
aic79xx_pci.c:
aic79xx.seq:
To speed up non-packetized CDB delivery in Rev B, all CDB
acks are "released" to the output sync as soon as the
command phase starts. There is only one problem with this
approach. If the target changes phase before all data are
sent, we have left over acks that can go out on the bus in
a data phase. Due to other chip contraints, this only
happens if the target goes to data-in, but if the acks go
out before we can test SDONE, we'll think that the transfer
has completed successfully. Work around this by taking
advantage of the 400ns or 800ns dead time between command
phase and the REQ of the new phase. If the transfer has
completed successfully, SCSIEN should fall *long* before we
see a phase change. We thus treat any phasemiss that
occurs before SCSIEN falls as an incomplete transfer.
aic79xx.h:
Add the AHD_FAST_CDB_DELIVERY feature.
aic79xx_pci.c:
Set AHD_FAST_CDB_DELIVERY for all Rev. B parts.
aic79xx.seq:
Test for PHASEMIS in the command phase for
all AHD_FAST_CDB_DELIVERY controlelrs.
ahd_pci.c:
ahc_pci.c:
aic7xxx.h:
aic79xx.h:
Move definition of controller BAR offsets to core header files.
aic7xxx.c:
aic79xx.c:
In the softc free routine, leave removal of a softc from the
global list of softcs to the OSM (the caller of this routine).
This allows us to avoid holding the softc list_lock during device
destruction where we may have to sleep waiting for our recovery
thread to halt.
ahc_pci.c:
Use ahc_pci_test_register access to validate I/O mapped in
addition to the tests already performed for memory mapped
access.
Remove unused ahc_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
ahd_pci.c:
Remove reduntant definition of controller BAR offsets. These
are also defined in aic79xx.h.
Remove unused ahd_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
aic7xxx.c:
aic79xx.c:
aic79xx.h:
aic7xxx.h:
aic7xxx_osm.c:
aic79xx_osm.c:
Move timeout handling to the driver cores. In the case
of the aic79xx driver, the algorithm has been enhanced
to try target resets before performing a bus reset. For
the aic7xxx driver, the algorithm is unchanged. Although
the drivers do not currently sleep during recovery (recovery
is timeout driven), the cores do expect all processing to
be performed via a recovery thread. Our timeout handlers
are now little stubs that wakeup the recovery thread.
aic79xx.c:
aic79xx.h:
aic79xx_inline.h:
Change shared_data allocation to use a map_node so
that the sentinel hscb can use this map node in
ahd_swap_with_next_hscb. This routine now swaps
the hscb_map pointer in additon to the hscb
contents so that any sync operations occur on
the correct map.
physaddr -> busaddr
Pointed out by: Jason Thorpe <thorpej@wasabisystems.com>
aic79xx.c:
Make more use of the in/out/w/l/q macros for accessing
byte registers in the chip.
Correct some issues in the ahd_flush_qoutfifo() routine.
o Run the qoutfifo only once the command channel
DMA engine has been halted. This closes a window
where we might have missed some entries.
o Change ahd_run_data_fifo() to not loop to completion.
If we happen to start on the wrong FIFO and the other
FIFO has a snapshot savepointers, we might deadlock.
This required our delay between FIFO tests to be
moved to the ahd_flush_qoutfifo() routine.
o Update/add comments.
o Remove spurious test for COMPLETE_DMA list being empty
when completing transactions from the GSFIFO with
residuals. The SCB must be put on the COMPLETE_DMA
scb list unconditionally.
o When halting command channel DMA activity, we must
disable the DMA channel in all cases but an update
of the QOUTFIFO. The latter case is required so
that the sequencer will update its position in the
QOUTFIFO. Previously, we left the channel enabled
for all "push" DMAs. This left us vulnerable to
the sequencer handling an SCB push long after that
SCB was already processed manually by this routine.
o Correct the polarity of tests involving
ahd_scb_active_in_fifo(). This routine returns
non-zero for true.
Return to processing bad status completions through
the qoutfifo. This reduces the time that the sequencer
is kept paused when handling transactions with bad
status or underruns.
When waiting for the controller to quiece selections,
add a delay to our loop. Otherwise we may fail to wait
long enough for the sequencer to comply.
On H2A4 hardware, use the slow slewrate for non-paced
transfers. This mirrors what the Adaptec Windows
drivers do.
On the Rev B. only slow down the CRC timing for
older U160 devices that might need the slower timing.
We define "older" as devices that do not support
packetized protocol.
Wait up to 5000 * 5us for the SEEPROM to become unbusy.
Write ops seem to take much longer than read ops.
aic79xx.seq:
For controllers with the FAINT_LED bug, turn the diagnostic
led feature on during selection and reselection. This covers
the non-packetized case. The LED will be disabled for
non-packetized transfers once we return to the top level idle
loop. Add more comments about the busy LED workaround.
Extend a critical section around the entire
command channel idle loop process. Previously
the portion of this handler that directly manipulated
the linked list of completed SCBs was not protected.
This is the likely cause of the recent reports of
commands being completed twice by the driver.
Extend critical sections across the test for,
and the longjump to, longjump routines. This
prevents the firmware from trying to jump to
a longjmp handler that was just cleared by the
host.
Improve the locations of several critical section
begin and end points. Typically these changes
remove instructions that did not need to be
inside a critical section.
Close the "busfree after selection, but before busfree
interrupts can be enabled" race to just a single sequencer
instruction. We now test the BSY line explicitly before
clearing the busfree status and enabling the busfree
interrupt.
Close a race condition in the processing of HS_MAILBOX
updates. We now clear the "updated" status before the
copy. This ensures that we don't accidentally clear
the status incorrectly when the host sneaks in an update
just after our last copy, but before we clear the status.
This race has never been observed.
Don't re-enable SCSIEN if we lose the race to disable SCSIEN
in our interrupt handler's workaround for the RevA data-valid
too early issue.
aic79xx_inline.h:
Add comments indicating that the order in which bytes are
read or written in ahd_inw and ahd_outw is important. This
allows us to use these inlines when accessing registers with
side-effects.
aic79xx_pci.c:
The 29320 and the 29320B are 7902 not 7901 based products.
Correct the driver banner.
aic7xxx.h:
Enable the use of the auto-access pause feature
on the aic7870 and aic7880. It was disabled due
to an oversight.
aic7xxx.reg:
Move TARG_IMMEDIATE_SCB to alias LAST_MSG to
avoid leaving garbage in MWI_RESIDUAL. This
prevents spurious overflows whn operating target
mode on controllers that require the MWI_RESIDUAL
work-around.
aic7xxx.seq:
AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag.
Reference the correct softc field when testing
for its presence.
Set the NOT_IDENTIFIED and NO_CDB_SENT bits
in SEQ_FLAGS to indicate that the nexus is
invalid in await busfree.
aic7xxx_93cx6.c:
Add support for the C56/C66 versions of the EWEN and EWDS
commands.
aic7xxx.c:
aic7xxx_pci.c:
Move test for the validity of left over BIOS data
to ahc_test_register_access(). This guarantees that
any left over CHIPRST value is not clobbered by our
register access test and lost to the test that was
in ahc_reset.
2003-12-17 00:02:10 +00:00
|
|
|
aic_le16toh(scb->hscb->tag)
|
2002-06-05 19:52:45 +00:00
|
|
|
|
|
|
|
|
#ifndef AHD_TARGET_MODE
|
|
|
|
|
#undef AHD_TMODE_ENABLE
|
|
|
|
|
#define AHD_TMODE_ENABLE 0
|
|
|
|
|
#endif
|
|
|
|
|
|
2002-08-31 06:48:42 +00:00
|
|
|
#define AHD_BUILD_COL_IDX(target, lun) \
|
|
|
|
|
(((lun) << 4) | target)
|
|
|
|
|
|
|
|
|
|
#define AHD_GET_SCB_COL_IDX(ahd, scb) \
|
|
|
|
|
((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb))
|
|
|
|
|
|
|
|
|
|
#define AHD_SET_SCB_COL_IDX(scb, col_idx) \
|
|
|
|
|
do { \
|
|
|
|
|
(scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID; \
|
|
|
|
|
(scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1); \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
|
|
#define AHD_COPY_SCB_COL_IDX(dst, src) \
|
|
|
|
|
do { \
|
|
|
|
|
dst->hscb->scsiid = src->hscb->scsiid; \
|
|
|
|
|
dst->hscb->lun = src->hscb->lun; \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
|
|
#define AHD_NEVER_COL_IDX 0xFFFF
|
|
|
|
|
|
2002-06-05 19:52:45 +00:00
|
|
|
/**************************** Driver Constants ********************************/
|
|
|
|
|
/*
|
|
|
|
|
* The maximum number of supported targets.
|
|
|
|
|
*/
|
|
|
|
|
#define AHD_NUM_TARGETS 16
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The maximum number of supported luns.
|
|
|
|
|
* The identify message only supports 64 luns in non-packetized transfers.
|
|
|
|
|
* You can have 2^64 luns when information unit transfers are enabled,
|
|
|
|
|
* but until we see a need to support that many, we support 256.
|
|
|
|
|
*/
|
|
|
|
|
#define AHD_NUM_LUNS_NONPKT 64
|
|
|
|
|
#define AHD_NUM_LUNS 256
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The maximum transfer per S/G segment.
|
|
|
|
|
*/
|
|
|
|
|
#define AHD_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The maximum amount of SCB storage in hardware on a controller.
|
|
|
|
|
* This value represents an upper bound. Due to software design,
|
|
|
|
|
* we may not be able to use this number.
|
|
|
|
|
*/
|
|
|
|
|
#define AHD_SCB_MAX 512
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The maximum number of concurrent transactions supported per driver instance.
|
|
|
|
|
* Sequencer Control Blocks (SCBs) store per-transaction information.
|
|
|
|
|
*/
|
2002-08-31 06:48:42 +00:00
|
|
|
#define AHD_MAX_QUEUE AHD_SCB_MAX
|
2002-06-05 19:52:45 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Define the size of our QIN and QOUT FIFOs. They must be a power of 2
|
Correct spelling errors.
Switch to handling bad SCSI status as a sequencer interrupt
instead of having the kernel proccess these failures via
the completion queue. This is done because:
o The old scheme required us to pause the sequencer and clear
critical sections for each SCB. It seems that these pause
actions, if coincident with a sequencer FIFO interrupt, would
result in a FIFO interrupt getting lost or directing to the
wrong FIFO. This caused hangs when the driver was stressed
under high "queue full" loads.
o The completion code assumed that it was always called with
the sequencer running. This may not be the case in timeout
processing where completions occur manually via
ahd_pause_and_flushwork().
o With this scheme, the extra expense of clearing critical
sections is avoided since the sequencer will only self pause
once all pending selections have cleared and it is not in
a critical section.
aic79xx.c
Add code to handle the new BAD_SCB_STATUS sequencer
interrupt code. This just redirects the SCB through
the already existing ahd_complete_scb() code path.
Remove code in ahd_handle_scsi_status() that paused
the sequencer, made sure that no selections where
pending, and cleared critical sections. Bad
status SCBs are now only processed when all of these
conditions are true.
aic79xx.reg:
Add the BAD_SCB_STATUS sequencer interrupt code.
aic79xx.seq:
When completing an SCB upload to the host, if
we are doing this because the SCB contains non-zero
SCSI status, defer completing the SCB until there
are no pending selection events. When completing
these SCBs, use the new BAD_SCB_STATUS sequencer
interrupt. For all other uploaded SCBs (currently
only for underruns), the SCB is completed via the
normal done queue. Additionally, keep the SCB that
is currently being uploaded on the COMPLETE_DMA_SCB
list until the dma is completed, not just until the
DMA is started. This ensures that the DMA is restarted
properly should the host disable the DMA transfer for
some reason.
In our RevA workaround for Maxtor drives, guard against
the host pausing us while trying to pause I/O until the
first data-valid REQ by clearing the current snapshot
so that we can tell if the transfer has completed prior
to us noticing the REQINIT status.
In cfg4data_intr, shave off an instruction before getting
the data path running by adding an entrypoint to the
overrun handler to also increment the FIFO use count.
In the overrun handler, be sure to clear our LONGJMP
address in both exit paths.
Perform a few sequencer optimizations.
aic79xx.c:
Print the full path from the SCB when a packetized
status overrun occurs.
Remove references to LONGJMP_SCB which is being
removed from firmware usage.
Print the new SCB_FIFO_USE_COUNT field in the
per-SCB section of ahd_dump_card_state(). The
SCB_TAG field is now re-used by the sequencer,
so it no longer makes sense to reference this
field in the kernel driver.
aic79xx.h:
Re-arrange fields in the hardware SCB from largest
size type to smallest. This makes it easier to
move fields without changing field alignment.
The hardware scb tag field is now down near the
"spare" portion of the SCB to facilitate reuse
by the sequencer.
aic79xx.reg:
Remove LONGJMP_ADDR.
Rearrange SCB fields to match aic79xx.h.
Add SCB_FIFO_USE_COUNT as the first byte
of the SCB_TAG field.
aic79xx.seq:
Add a per-SCB "Fifos in use count" field and use
it to determine when it is safe (all data posted)
to deliver status back to the host. The old method
involved polling one or both FIFOs to verify that
the current task did not have pending data. This
makes running down the GSFIFO very cheap, so we
will empty the GSFIFO in one idle loop pass in
all cases.
Use this simplification of the completion process
to prune down the data FIFO teardown sequencer for
packetized transfers. Much more code is now shared
between the data residual and transfer complete cases.
Correct some issues in the packetized status handler.
It used to be possible to CLRCHN our FIFO before status
had fully transferred to the host. We also failed to
handle NONPACKREQ phases that could occur should a CRC
error occur during transmission of the status data packet.
Correct a few big endian issues:
aic79xx.c:
aic79xx_inline.h:
aic79xx_pci.c:
aic79xx_osm.c:
o Always get the SCB's tag via the SCB_GET_TAG acccessor
o Add missing use of byte swapping macros when touching
hscb fields.
o Don't double swap SEEPROM data when it is printed.
Correct a big-endian bug. We cannot assign a
o When assigning a 32bit LE variable to a 64bit LE
variable, we must be explict about how the words
of the 64bit LE variable are initialized. Cast to
(uint32_t*) to do this.
aic79xx.c:
In ahd_clear_critical_section(), hit CRLSCSIINT
after restoring the interrupt masks to avoid what
appears to be a glitch on SCSIINT. Any real SCSIINT
status will be persistent and will immidiately
reset SCSIINT. This clear should only get rid of
spurious SCSIINTs.
This glitch was the cause of the "Unexpected PKT busfree"
status that occurred under high queue full loads
Call ahd_fini_scbdata() after shutdown so that
any ahd_chip_init() routine that might access
SCB data will not access free'd memory.
Reset the bus on an IOERR since the chip doesn't
seem to reset to the new voltage level without
this.
Change offset calculation for scatter gather maps
so that the calculation is correct if an integral
multiple of sg lists does not fit in the allocation
size.
Adjust bus dma tag for data buffers based on 39BIT
addressing flag in our softc.
Use the QFREEZE count to simplify ahd_pause_and_flushworkd().
We can thus rely on the sequencer eventually clearing ENSELO.
In ahd_abort_scbs(), fix a bug that could potentially
corrupt sequencer state. The saved SCB was being
restored in the SCSI mode instead of the saved mode.
It turns out that the SCB did not need to be saved at all
as the scbptr is already restored by all subroutines
called during this function that modify that register.
aic79xx.c:
aic79xx.h:
aic79xx_pci.c:
Add support for parsing the seeprom vital product
data. The VPD data are currently unused.
aic79xx.h:
aic79xx.seq:
aic79xx_pci.c:
Add a firmware workaround to make the LED blink
brighter during packetized operations on the H2A.
aic79xx_inline.h:
The host does not use timer interrupts, so don't
gate our decision on whether or not to unpause
the sequencer on whether or not a timer interrupt
is pending.
2003-05-04 00:20:07 +00:00
|
|
|
* in size and accommodate as many transactions as can be queued concurrently.
|
2002-06-05 19:52:45 +00:00
|
|
|
*/
|
2002-08-31 06:48:42 +00:00
|
|
|
#define AHD_QIN_SIZE AHD_MAX_QUEUE
|
|
|
|
|
#define AHD_QOUT_SIZE AHD_MAX_QUEUE
|
2002-06-05 19:52:45 +00:00
|
|
|
|
|
|
|
|
#define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1))
|
|
|
|
|
/*
|
2002-08-31 06:48:42 +00:00
|
|
|
* The maximum amount of SCB storage we allocate in host memory.
|
2002-06-05 19:52:45 +00:00
|
|
|
*/
|
2002-08-31 06:48:42 +00:00
|
|
|
#define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE
|
2002-06-05 19:52:45 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Ring Buffer of incoming target commands.
|
|
|
|
|
* We allocate 256 to simplify the logic in the sequencer
|
|
|
|
|
* by using the natural wrap point of an 8bit counter.
|
|
|
|
|
*/
|
|
|
|
|
#define AHD_TMODE_CMDS 256
|
|
|
|
|
|
|
|
|
|
/* Reset line assertion time in us */
|
2002-08-31 06:48:42 +00:00
|
|
|
#define AHD_BUSRESET_DELAY 25
|
2002-06-05 19:52:45 +00:00
|
|
|
|
|
|
|
|
/******************* Chip Characteristics/Operating Settings *****************/
|
aic79xx.c:
aic79xx.seq:
Convert the COMPLETE_DMA_SCB list to an "stailq". This allows us to
safely keep the SCB that is currently being DMA'ed back the host on
the head of the list while processing completions off of the bus. The
newly completed SCBs are appended to the tail of the queue. In the
past, we just dequeued the SCB that was in flight from the list, but
this could result in a lost completion should the host perform certain
types of error recovery that must cancel all in-flight SCB DMA operations.
Switch from using a 16bit completion entry, holding just the tag and the
completion valid bit, to a 64bit completion entry that also contains a
"status packet valid" indicator. This solves two problems:
o The SCB DMA engine on at least Rev B. silicon does not properly deal
with a PCI disconnect that occurs at a non-64bit aligned offset in the
chips "source buffer". When the transfer is resumed, the DMA engine
continues at the correct offset, but may wrap to the head of the buffer
causing duplicate completions to be reported to the host. By using a
completion buffer in host memory that is 64bit aligned and using 64bit
completion entries, such disconnects should only occur at aligned addresses.
This assumes that the host bridge will only disconnect on cache-line
boundaries and that cache-lines are multpiles of 64bits.
o By embedding the status information in the completion entry we can avoid
an extra memory reference to the HSCB for commands that complete without
error.
Use the comparison of a "host freeze count" and a "sequencer freeze count"
to allow the host to process most SCBs that complete with non-zero status
without having to clear critical sections. Instead the host can just pause the
sequencer, performs any necessary cleanup in the waiting for selection list,
increments its freeze count on the controller, and unpauses. This is only
possible because the sequencer defers completions of SCBs with bad status
until after all pending selections have completed. The sequencer then avoids
referencing any data structures the host may touch during completion of the
SCB until the freeze counts match.
aic79xx.c:
Change the strategy for allocating our sentinal HSCB for the QINFIFO. In
the past, this allocation was tacked onto the QOUTFIFO allocation. Now that
the qoutfifo has grown to accomodate larger completion entries, the old
approach will result in a 64byte allocation that costs an extra page of
coherent memory. We now do this extra allocation via ahd_alloc_scbs()
where the "unused space" can be used to allocate "normal" HSCBs.
In our packetized busfree handler, use the ENSELO bit to differentiate
between packetized and non-packetized unexpected busfree events that
occur just after selection, but before the sequencer has had the oportunity
to service the selection.
When cleaning out the waiting for selection list, use the SCSI mode
instead of the command channel mode. The SCB pointer in the command
channel mode may be referenced by the SCB dma engine even while the
sequencer is paused, whereas the SCSI mode SCB pointer is only accessed
by the sequencer.
Print the "complete on qfreeze" sequencer SCB completion list in
ahd_dump_card_state(). This list holds all SCB completions that are deferred
until a pending select-out qfreeze event has taken effect.
aic79xx.h:
Add definitions and structures to handle the new SCB completion scheme.
Add a controller flag that indicates if the controller is in HostRAID
mode.
aic79xx.reg:
Remove macros used for toggling from one data fifo mode to the other.
They have not been in use for some time.
Add scratch ram fields for our new qfreeze count scheme, converting
the complete dma list into an "stailq", and providing for the "complete
on qfreeze" SCB completion list. Some other fields were moved to retain
proper field alignment (alignment >= field size in bytes).
aic79xx.seq:
Add code to our idle loop to:
o Process deferred completions once a qfreeze event has taken full
effect.
o Thaw the queue once the sequencer and host qfreeze counts match.
Generate 64bit completion entries passing the SCB_SGPTR field as the
"good status" indicator. The first bit in this field is only set if
we have a valid status packet to send to the host.
Convert the COMPLETE_DMA_SCB list to an "stailq".
When using "setjmp" to register an idle loop handler, do not combine
the "ret" with the block move to pop the stack address in the same
instruction. At least on the A, this results in a return to the setjmp
caller, not to the new address at the top of the stack. Since we want
the latter (we want the newly registered handler to only be invoked from
the idle loop), we must use a separate ret instruction.
Add a few missing critical sections.
Close a race condition that can occur on Rev A. silicon. If both FIFOs
happen to be allocated before the sequencer has a chance to service the
FIFO that was allocated first, we must take special care to service the
FIFO that is not active on the SCSI bus first. This guarantees that a
FIFO will be freed to handle any snapshot requests for the FIFO that is
still on the bus. Chosing the incorrect FIFO will result in deadlock.
Update comments.
aic79xx_inline.h
Correct the offset calculation for the syncing of our qoutfifo.
Update ahd_check_cmdcmpltqueues() for the larger completion entries.
aic79xx_pci.c:
Attach to HostRAID controllers by default. In the future I may add a
sysctl to modify the behavior, but since FreeBSD does not have any
HostRAID drivers, failing to attach just results in more email and
bug reports for the author.
MFC After: 1week
2004-02-04 16:38:38 +00:00
|
|
|
extern uint32_t ahd_attach_to_HostRAID_controllers;
|
|
|
|
|
|
2002-06-05 19:52:45 +00:00
|
|
|
/*
|
|
|
|
|
* Chip Type
|
|
|
|
|
* The chip order is from least sophisticated to most sophisticated.
|
|
|
|
|
*/
|
|
|
|
|
typedef enum {
|
|
|
|
|
AHD_NONE = 0x0000,
|
|
|
|
|
AHD_CHIPID_MASK = 0x00FF,
|
|
|
|
|
AHD_AIC7901 = 0x0001,
|
|
|
|
|
AHD_AIC7902 = 0x0002,
|
2002-08-31 06:48:42 +00:00
|
|
|
AHD_AIC7901A = 0x0003,
|
2002-06-05 19:52:45 +00:00
|
|
|
AHD_PCI = 0x0100, /* Bus type PCI */
|
|
|
|
|
AHD_PCIX = 0x0200, /* Bus type PCIX */
|
|
|
|
|
AHD_BUS_MASK = 0x0F00
|
|
|
|
|
} ahd_chip;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Features available in each chip type.
|
|
|
|
|
*/
|
|
|
|
|
typedef enum {
|
2002-12-01 08:13:37 +00:00
|
|
|
AHD_FENONE = 0x00000,
|
|
|
|
|
AHD_WIDE = 0x00001,/* Wide Channel */
|
|
|
|
|
AHD_MULTI_FUNC = 0x00100,/* Multi-Function/Channel Device */
|
|
|
|
|
AHD_TARGETMODE = 0x01000,/* Has tested target mode support */
|
|
|
|
|
AHD_MULTIROLE = 0x02000,/* Space for two roles at a time */
|
|
|
|
|
AHD_RTI = 0x04000,/* Retained Training Support */
|
|
|
|
|
AHD_NEW_IOCELL_OPTS = 0x08000,/* More Signal knobs in the IOCELL */
|
|
|
|
|
AHD_NEW_DFCNTRL_OPTS = 0x10000,/* SCSIENWRDIS bit */
|
ahc_eisa.c:
ahc_pci.c:
ahd_pci.c:
aic7xxx.c:
aic79xx.c:
aic_osm_lib.c:
aic_osm_lib.h:
Use common OSM routines from aic_osm_lib for bus dma operations,
delay routines, accessing CCBs, byte swapping, etc.
aic7xxx_pci.c:
Provide a better description for the 2915/30LP on attach.
aic7xxx.c:
aic79xx.c:
aic7770.c:
aic79xx_pci.c:
aic7xxx_pci.c:
aic7xxx_93cx6.c:
Move FBSDID behind an ifdef so that these core files will
still compile under other OSes.
aic79xx.h:
aic79xx_pci.c:
aic79xx.seq:
To speed up non-packetized CDB delivery in Rev B, all CDB
acks are "released" to the output sync as soon as the
command phase starts. There is only one problem with this
approach. If the target changes phase before all data are
sent, we have left over acks that can go out on the bus in
a data phase. Due to other chip contraints, this only
happens if the target goes to data-in, but if the acks go
out before we can test SDONE, we'll think that the transfer
has completed successfully. Work around this by taking
advantage of the 400ns or 800ns dead time between command
phase and the REQ of the new phase. If the transfer has
completed successfully, SCSIEN should fall *long* before we
see a phase change. We thus treat any phasemiss that
occurs before SCSIEN falls as an incomplete transfer.
aic79xx.h:
Add the AHD_FAST_CDB_DELIVERY feature.
aic79xx_pci.c:
Set AHD_FAST_CDB_DELIVERY for all Rev. B parts.
aic79xx.seq:
Test for PHASEMIS in the command phase for
all AHD_FAST_CDB_DELIVERY controlelrs.
ahd_pci.c:
ahc_pci.c:
aic7xxx.h:
aic79xx.h:
Move definition of controller BAR offsets to core header files.
aic7xxx.c:
aic79xx.c:
In the softc free routine, leave removal of a softc from the
global list of softcs to the OSM (the caller of this routine).
This allows us to avoid holding the softc list_lock during device
destruction where we may have to sleep waiting for our recovery
thread to halt.
ahc_pci.c:
Use ahc_pci_test_register access to validate I/O mapped in
addition to the tests already performed for memory mapped
access.
Remove unused ahc_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
ahd_pci.c:
Remove reduntant definition of controller BAR offsets. These
are also defined in aic79xx.h.
Remove unused ahd_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
aic7xxx.c:
aic79xx.c:
aic79xx.h:
aic7xxx.h:
aic7xxx_osm.c:
aic79xx_osm.c:
Move timeout handling to the driver cores. In the case
of the aic79xx driver, the algorithm has been enhanced
to try target resets before performing a bus reset. For
the aic7xxx driver, the algorithm is unchanged. Although
the drivers do not currently sleep during recovery (recovery
is timeout driven), the cores do expect all processing to
be performed via a recovery thread. Our timeout handlers
are now little stubs that wakeup the recovery thread.
aic79xx.c:
aic79xx.h:
aic79xx_inline.h:
Change shared_data allocation to use a map_node so
that the sentinel hscb can use this map node in
ahd_swap_with_next_hscb. This routine now swaps
the hscb_map pointer in additon to the hscb
contents so that any sync operations occur on
the correct map.
physaddr -> busaddr
Pointed out by: Jason Thorpe <thorpej@wasabisystems.com>
aic79xx.c:
Make more use of the in/out/w/l/q macros for accessing
byte registers in the chip.
Correct some issues in the ahd_flush_qoutfifo() routine.
o Run the qoutfifo only once the command channel
DMA engine has been halted. This closes a window
where we might have missed some entries.
o Change ahd_run_data_fifo() to not loop to completion.
If we happen to start on the wrong FIFO and the other
FIFO has a snapshot savepointers, we might deadlock.
This required our delay between FIFO tests to be
moved to the ahd_flush_qoutfifo() routine.
o Update/add comments.
o Remove spurious test for COMPLETE_DMA list being empty
when completing transactions from the GSFIFO with
residuals. The SCB must be put on the COMPLETE_DMA
scb list unconditionally.
o When halting command channel DMA activity, we must
disable the DMA channel in all cases but an update
of the QOUTFIFO. The latter case is required so
that the sequencer will update its position in the
QOUTFIFO. Previously, we left the channel enabled
for all "push" DMAs. This left us vulnerable to
the sequencer handling an SCB push long after that
SCB was already processed manually by this routine.
o Correct the polarity of tests involving
ahd_scb_active_in_fifo(). This routine returns
non-zero for true.
Return to processing bad status completions through
the qoutfifo. This reduces the time that the sequencer
is kept paused when handling transactions with bad
status or underruns.
When waiting for the controller to quiece selections,
add a delay to our loop. Otherwise we may fail to wait
long enough for the sequencer to comply.
On H2A4 hardware, use the slow slewrate for non-paced
transfers. This mirrors what the Adaptec Windows
drivers do.
On the Rev B. only slow down the CRC timing for
older U160 devices that might need the slower timing.
We define "older" as devices that do not support
packetized protocol.
Wait up to 5000 * 5us for the SEEPROM to become unbusy.
Write ops seem to take much longer than read ops.
aic79xx.seq:
For controllers with the FAINT_LED bug, turn the diagnostic
led feature on during selection and reselection. This covers
the non-packetized case. The LED will be disabled for
non-packetized transfers once we return to the top level idle
loop. Add more comments about the busy LED workaround.
Extend a critical section around the entire
command channel idle loop process. Previously
the portion of this handler that directly manipulated
the linked list of completed SCBs was not protected.
This is the likely cause of the recent reports of
commands being completed twice by the driver.
Extend critical sections across the test for,
and the longjump to, longjump routines. This
prevents the firmware from trying to jump to
a longjmp handler that was just cleared by the
host.
Improve the locations of several critical section
begin and end points. Typically these changes
remove instructions that did not need to be
inside a critical section.
Close the "busfree after selection, but before busfree
interrupts can be enabled" race to just a single sequencer
instruction. We now test the BSY line explicitly before
clearing the busfree status and enabling the busfree
interrupt.
Close a race condition in the processing of HS_MAILBOX
updates. We now clear the "updated" status before the
copy. This ensures that we don't accidentally clear
the status incorrectly when the host sneaks in an update
just after our last copy, but before we clear the status.
This race has never been observed.
Don't re-enable SCSIEN if we lose the race to disable SCSIEN
in our interrupt handler's workaround for the RevA data-valid
too early issue.
aic79xx_inline.h:
Add comments indicating that the order in which bytes are
read or written in ahd_inw and ahd_outw is important. This
allows us to use these inlines when accessing registers with
side-effects.
aic79xx_pci.c:
The 29320 and the 29320B are 7902 not 7901 based products.
Correct the driver banner.
aic7xxx.h:
Enable the use of the auto-access pause feature
on the aic7870 and aic7880. It was disabled due
to an oversight.
aic7xxx.reg:
Move TARG_IMMEDIATE_SCB to alias LAST_MSG to
avoid leaving garbage in MWI_RESIDUAL. This
prevents spurious overflows whn operating target
mode on controllers that require the MWI_RESIDUAL
work-around.
aic7xxx.seq:
AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag.
Reference the correct softc field when testing
for its presence.
Set the NOT_IDENTIFIED and NO_CDB_SENT bits
in SEQ_FLAGS to indicate that the nexus is
invalid in await busfree.
aic7xxx_93cx6.c:
Add support for the C56/C66 versions of the EWEN and EWDS
commands.
aic7xxx.c:
aic7xxx_pci.c:
Move test for the validity of left over BIOS data
to ahc_test_register_access(). This guarantees that
any left over CHIPRST value is not clobbered by our
register access test and lost to the test that was
in ahc_reset.
2003-12-17 00:02:10 +00:00
|
|
|
AHD_FAST_CDB_DELIVERY = 0x20000,/* CDB acks released to Output Sync */
|
2002-12-01 08:13:37 +00:00
|
|
|
AHD_REMOVABLE = 0x00000,/* Hot-Swap supported - None so far*/
|
|
|
|
|
AHD_AIC7901_FE = AHD_FENONE,
|
2003-06-28 04:39:49 +00:00
|
|
|
AHD_AIC7901A_FE = AHD_FENONE,
|
2002-12-01 08:13:37 +00:00
|
|
|
AHD_AIC7902_FE = AHD_MULTI_FUNC
|
2002-06-05 19:52:45 +00:00
|
|
|
} ahd_feature;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Bugs in the silicon that we work around in software.
|
|
|
|
|
*/
|
|
|
|
|
typedef enum {
|
|
|
|
|
AHD_BUGNONE = 0x0000,
|
2002-12-01 08:13:37 +00:00
|
|
|
/*
|
|
|
|
|
* Rev A hardware fails to update LAST/CURR/NEXTSCB
|
|
|
|
|
* correctly in certain packetized selection cases.
|
|
|
|
|
*/
|
2002-06-05 19:52:45 +00:00
|
|
|
AHD_SENT_SCB_UPDATE_BUG = 0x0001,
|
2002-12-01 08:13:37 +00:00
|
|
|
/* The wrong SCB is accessed to check the abort pending bit. */
|
2002-06-05 19:52:45 +00:00
|
|
|
AHD_ABORT_LQI_BUG = 0x0002,
|
2002-12-01 08:13:37 +00:00
|
|
|
/* Packetized bitbucket crosses packet boundaries. */
|
2002-06-05 19:52:45 +00:00
|
|
|
AHD_PKT_BITBUCKET_BUG = 0x0004,
|
2002-12-01 08:13:37 +00:00
|
|
|
/* The selection timer runs twice as long as its setting. */
|
2002-06-05 19:52:45 +00:00
|
|
|
AHD_LONG_SETIMO_BUG = 0x0008,
|
2002-12-01 08:13:37 +00:00
|
|
|
/* The Non-LQ CRC error status is delayed until phase change. */
|
2002-06-05 19:52:45 +00:00
|
|
|
AHD_NLQICRC_DELAYED_BUG = 0x0010,
|
2002-12-01 08:13:37 +00:00
|
|
|
/* The chip must be reset for all outgoing bus resets. */
|
2002-06-05 19:52:45 +00:00
|
|
|
AHD_SCSIRST_BUG = 0x0020,
|
2002-12-01 08:13:37 +00:00
|
|
|
/* Some PCIX fields must be saved and restored across chip reset. */
|
2002-08-31 06:48:42 +00:00
|
|
|
AHD_PCIX_CHIPRST_BUG = 0x0040,
|
2002-12-01 08:13:37 +00:00
|
|
|
/* MMAPIO is not functional in PCI-X mode. */
|
2002-08-31 06:48:42 +00:00
|
|
|
AHD_PCIX_MMAPIO_BUG = 0x0080,
|
2003-03-06 23:58:34 +00:00
|
|
|
/* Reads to SCBRAM fail to reset the discard timer. */
|
|
|
|
|
AHD_PCIX_SCBRAM_RD_BUG = 0x0100,
|
2002-06-05 19:52:45 +00:00
|
|
|
/* Bug workarounds that can be disabled on non-PCIX busses. */
|
2002-08-31 06:48:42 +00:00
|
|
|
AHD_PCIX_BUG_MASK = AHD_PCIX_CHIPRST_BUG
|
2003-03-06 23:58:34 +00:00
|
|
|
| AHD_PCIX_MMAPIO_BUG
|
|
|
|
|
| AHD_PCIX_SCBRAM_RD_BUG,
|
2002-12-01 08:13:37 +00:00
|
|
|
/*
|
|
|
|
|
* LQOSTOP0 status set even for forced selections with ATN
|
|
|
|
|
* to perform non-packetized message delivery.
|
|
|
|
|
*/
|
2003-03-06 23:58:34 +00:00
|
|
|
AHD_LQO_ATNO_BUG = 0x0200,
|
2002-12-01 08:13:37 +00:00
|
|
|
/* FIFO auto-flush does not always trigger. */
|
2003-03-06 23:58:34 +00:00
|
|
|
AHD_AUTOFLUSH_BUG = 0x0400,
|
2002-12-01 08:13:37 +00:00
|
|
|
/* The CLRLQO registers are not self-clearing. */
|
2003-03-06 23:58:34 +00:00
|
|
|
AHD_CLRLQO_AUTOCLR_BUG = 0x0800,
|
2002-12-01 08:13:37 +00:00
|
|
|
/* The PACKETIZED status bit refers to the previous connection. */
|
2003-03-06 23:58:34 +00:00
|
|
|
AHD_PKTIZED_STATUS_BUG = 0x1000,
|
2002-12-01 08:13:37 +00:00
|
|
|
/* "Short Luns" are not placed into outgoing LQ packets correctly. */
|
2003-03-06 23:58:34 +00:00
|
|
|
AHD_PKT_LUN_BUG = 0x2000,
|
2002-12-01 08:13:37 +00:00
|
|
|
/*
|
|
|
|
|
* Only the FIFO allocated to the non-packetized connection may
|
|
|
|
|
* be in use during a non-packetzied connection.
|
|
|
|
|
*/
|
2003-03-06 23:58:34 +00:00
|
|
|
AHD_NONPACKFIFO_BUG = 0x4000,
|
2002-12-01 08:13:37 +00:00
|
|
|
/*
|
|
|
|
|
* Writing to a DFF SCBPTR register may fail if concurent with
|
|
|
|
|
* a hardware write to the other DFF SCBPTR register. This is
|
|
|
|
|
* not currently a concern in our sequencer since all chips with
|
|
|
|
|
* this bug have the AHD_NONPACKFIFO_BUG and all writes of concern
|
|
|
|
|
* occur in non-packetized connections.
|
|
|
|
|
*/
|
2003-03-06 23:58:34 +00:00
|
|
|
AHD_MDFF_WSCBPTR_BUG = 0x8000,
|
2002-12-01 08:13:37 +00:00
|
|
|
/* SGHADDR updates are slow. */
|
2003-03-06 23:58:34 +00:00
|
|
|
AHD_REG_SLOW_SETTLE_BUG = 0x10000,
|
2002-12-01 08:13:37 +00:00
|
|
|
/*
|
|
|
|
|
* Changing the MODE_PTR coincident with an interrupt that
|
|
|
|
|
* switches to a different mode will cause the interrupt to
|
|
|
|
|
* be in the mode written outside of interrupt context.
|
|
|
|
|
*/
|
2003-03-06 23:58:34 +00:00
|
|
|
AHD_SET_MODE_BUG = 0x20000,
|
2002-12-01 08:13:37 +00:00
|
|
|
/* Non-packetized busfree revision does not work. */
|
2003-03-06 23:58:34 +00:00
|
|
|
AHD_BUSFREEREV_BUG = 0x40000,
|
2002-12-01 08:13:37 +00:00
|
|
|
/*
|
|
|
|
|
* Paced transfers are indicated with a non-standard PPR
|
|
|
|
|
* option bit in the neg table, 160MHz is indicated by
|
|
|
|
|
* sync factor 0x7, and the offset if off by a factor of 2.
|
|
|
|
|
*/
|
2003-03-06 23:58:34 +00:00
|
|
|
AHD_PACED_NEGTABLE_BUG = 0x80000,
|
2002-12-01 08:13:37 +00:00
|
|
|
/* LQOOVERRUN false positives. */
|
2003-03-06 23:58:34 +00:00
|
|
|
AHD_LQOOVERRUN_BUG = 0x100000,
|
2002-12-01 08:13:37 +00:00
|
|
|
/*
|
|
|
|
|
* Controller write to INTSTAT will lose to a host
|
|
|
|
|
* write to CLRINT.
|
|
|
|
|
*/
|
2003-03-06 23:58:34 +00:00
|
|
|
AHD_INTCOLLISION_BUG = 0x200000,
|
aic79xx.c:
Clear the LQICRC_NLQ status should it pop up after we have
already handled the SCSIPERR. During some streaming operations
this status can be delayed until the stream ends. Without this
change, the driver would complain about a "Missing case in
ahd_handle_scsiint".
In the LQOBUSFREE handler...
Don't return the LQOMGR back to the idle state until after
we have cleaned up ENSELO and any status related to this
selection. The last thing we need is the LQO manager starting
another select-out before we have updated the execution queue.
It is not clear whether the LQOMGR would, or would not
start a new selection early.
Make sure ENSELO is off prior to clearing SELDO by flushing
device writes.
Move assignment of the next target SCB pointer inside of
an if to make the code clearer. The effect is the same.
Dump card state in both "Unexpected PKT busfree" paths.
In ahd_reset(), set the chip to SCSI mode before reading SXFRCTL1.
That register only exists in the SCSI mode. Also set the mode
explicitly to the SCSI mode after chip reset due to paranoia.
Re-arrange code so that SXFRCTL1 is restored as quickly after the
chip reset as possible.
S/G structurs must be 8byte aligned. Make this official by saying
so in our DMA tag.
Disable CIO bus stretch on MDFFSTAT if SHVALID is about to come
true. This can cause a CIO bus lockup if a PCI or PCI-X error
occurs while the stretch is occurring - the host cannot service
the PCI-X error since the CIO bus is locked out and SHVALID will
never resolve. The stretch was added in the Rev B to simplify the
wait for SHVALID to resolve, but the code to do this in the open
source sequencer is so simple it was never removed.
Consistently use MAX_OFFSET for the user max syncrate set from
non-volatile storage. This ensures that the offset does not
conflict with AH?_OFFSET_UNKNOWN.
Have ahd_pause_and_flushwork set the mode to ensure that it has
access to the registers it checks. Also modify the checking of
intstat so that the check against 0xFF can actually succeed if
the INT_PEND mask is something other than 0xFF. Although there
are no cardbus U320 controllers, this check may be needed to
recover from a hot-plug PCI removal that occurs without informing
the driver.
Fix a typo. sg_prefetch_cnt -> sg_prefetch_align. This fixes
an infinite loop at card initialization if the cacheline size is 0.
aic79xx.h:
Add AHD_EARLY_REQ_BUG bug flag.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
Change AH?_OFFSET_UNKNOWN to 0xFF. This is a value that the
curr->offset can never be, unlike '0' which we previously used.
This fixes code that only checks for a non-zero offset to
determine if a sync negotiation is required since it will fire
in the unknown case even if the goal is async.
aic79xx.reg:
Add comments for LQISTAT bits indicating their names in the 7902
data book. We use slightly different and more descriptive names
in the firmware.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
aic79xx.seq:
Update comments regarding rundown of the GSFIFO to reflect reality.
Fix spelling errors.
Since we use an 8byte address and 1 byte length, shorten the size
of a block move for the legacy DMA'ed CDB case from 11 to 9 bytes.
Remove code that, assuming the abort pending feature worked, would
set MK_MESSAGE in the SCB's control byte on completion to catch
invalid reselections. Since we don't see interrupts for completed
selections, this status update could occur prior to us noticing the
SELDO. The "select-out" queue logic will get confused by the
MK_MESSAGE bit being set as this is used to catch packatized
connections where we select-out with ATN. Since the abort pending
feature doesn't work on any released controllers yet, this code was
never executed.
Add support for the AHD_EARLY_REQ_BUG. Don't ignore persistent REQ
assertions just because they were asserted within the bus settle delay
window. This allows us to tolerate devices like the GEM318 that
violate the SCSI spec.
Remove unintentional settnig of SG_CACHE_AVAIL. Writing this bit
should have no effect, but who knows...
On the Rev A, we must wait for HDMAENACK before loading additional
segments to avoid clobbering the address of the first segment in
the S/G FIFO. This resolves data-corruption issues with certain
IBM (now Hitachi) and Fujitsu U320 drives.
Rearrange calc_residual to avoid an extra jmp instruction.
On RevA Silicon, if the target returns us to data-out after we
have already trained for data-out, it is possible for us to
transition the free running clock to data-valid before the required
100ns P1 setup time (8 P1 assertions in fast-160 mode). This will
only happen if this L-Q is a continuation of a data transfer for
which we have already prefetched data into our FIFO (LQ/Data
followed by LQ/Data for the same write transaction). This can
cause some target implementations to miss the first few data
transfers on the bus. We detect this situation by noticing that
this is the first data transfer after an LQ (LQIWORKONLQ true),
that the data transfer is a continuation of a transfer already
setup in our FIFO (SAVEPTRS interrupt), and that the transaction
is a write (DIRECTION set in DFCNTRL). The delay is performed by
disabling SCSIEN until we see the first REQ from the target.
Only compile in snapshot savepointers handler for RevA silicon
where it is enabled.
Handle the cfg4icmd packetized interrupt. We just need to load
the address and count, start the DMA, and CLRCHN once the transfer
is complete.
Fix an oversight in the overrun handler for packetized status
operations. We need to wait for either CTXTDONE or an overrun
when checking for an overrun. The previous code did not wait
and thus could decide that no overrun had occurred even though
an overrun will occur on the next data-valid req. Add some
comment to this section for clarity.
Use LAST_SEG_DONE instead of LASTSDONE for testing transfer
completion in the packetized status case. LASTSDONE may come up
more quickly since it only records completion on the SCSI side,
but since LAST_SEG_DONE is used everywhere else (and needs to be),
this is less confusing.
Add a missing invalidation of the longjmp address in the non-pack
handler. This code needs additional review.
aic79xx_inline.h:
Fix spelling error.
aic79xx_osm.c:
Set the cdb length for CDBs dma'ed from host memory.
Add a comment indicating that, should CAM start supporting cdbs
larger than 16bytes, the driver could store the CDB in the status
buffer.
aic79xx_pci.c:
Add a table entry for the 39320A.
Added a missing comma to an error string table.
Fix spelling errors.
2003-02-27 23:23:16 +00:00
|
|
|
/*
|
|
|
|
|
* The GEM318 violates the SCSI spec by not waiting
|
|
|
|
|
* the mandated bus settle delay between phase changes
|
|
|
|
|
* in some situations. Some aic79xx chip revs. are more
|
|
|
|
|
* strict in this regard and will treat REQ assertions
|
|
|
|
|
* that fall within the bus settle delay window as
|
|
|
|
|
* glitches. This flag tells the firmware to tolerate
|
|
|
|
|
* early REQ assertions.
|
|
|
|
|
*/
|
Correct spelling errors.
Switch to handling bad SCSI status as a sequencer interrupt
instead of having the kernel proccess these failures via
the completion queue. This is done because:
o The old scheme required us to pause the sequencer and clear
critical sections for each SCB. It seems that these pause
actions, if coincident with a sequencer FIFO interrupt, would
result in a FIFO interrupt getting lost or directing to the
wrong FIFO. This caused hangs when the driver was stressed
under high "queue full" loads.
o The completion code assumed that it was always called with
the sequencer running. This may not be the case in timeout
processing where completions occur manually via
ahd_pause_and_flushwork().
o With this scheme, the extra expense of clearing critical
sections is avoided since the sequencer will only self pause
once all pending selections have cleared and it is not in
a critical section.
aic79xx.c
Add code to handle the new BAD_SCB_STATUS sequencer
interrupt code. This just redirects the SCB through
the already existing ahd_complete_scb() code path.
Remove code in ahd_handle_scsi_status() that paused
the sequencer, made sure that no selections where
pending, and cleared critical sections. Bad
status SCBs are now only processed when all of these
conditions are true.
aic79xx.reg:
Add the BAD_SCB_STATUS sequencer interrupt code.
aic79xx.seq:
When completing an SCB upload to the host, if
we are doing this because the SCB contains non-zero
SCSI status, defer completing the SCB until there
are no pending selection events. When completing
these SCBs, use the new BAD_SCB_STATUS sequencer
interrupt. For all other uploaded SCBs (currently
only for underruns), the SCB is completed via the
normal done queue. Additionally, keep the SCB that
is currently being uploaded on the COMPLETE_DMA_SCB
list until the dma is completed, not just until the
DMA is started. This ensures that the DMA is restarted
properly should the host disable the DMA transfer for
some reason.
In our RevA workaround for Maxtor drives, guard against
the host pausing us while trying to pause I/O until the
first data-valid REQ by clearing the current snapshot
so that we can tell if the transfer has completed prior
to us noticing the REQINIT status.
In cfg4data_intr, shave off an instruction before getting
the data path running by adding an entrypoint to the
overrun handler to also increment the FIFO use count.
In the overrun handler, be sure to clear our LONGJMP
address in both exit paths.
Perform a few sequencer optimizations.
aic79xx.c:
Print the full path from the SCB when a packetized
status overrun occurs.
Remove references to LONGJMP_SCB which is being
removed from firmware usage.
Print the new SCB_FIFO_USE_COUNT field in the
per-SCB section of ahd_dump_card_state(). The
SCB_TAG field is now re-used by the sequencer,
so it no longer makes sense to reference this
field in the kernel driver.
aic79xx.h:
Re-arrange fields in the hardware SCB from largest
size type to smallest. This makes it easier to
move fields without changing field alignment.
The hardware scb tag field is now down near the
"spare" portion of the SCB to facilitate reuse
by the sequencer.
aic79xx.reg:
Remove LONGJMP_ADDR.
Rearrange SCB fields to match aic79xx.h.
Add SCB_FIFO_USE_COUNT as the first byte
of the SCB_TAG field.
aic79xx.seq:
Add a per-SCB "Fifos in use count" field and use
it to determine when it is safe (all data posted)
to deliver status back to the host. The old method
involved polling one or both FIFOs to verify that
the current task did not have pending data. This
makes running down the GSFIFO very cheap, so we
will empty the GSFIFO in one idle loop pass in
all cases.
Use this simplification of the completion process
to prune down the data FIFO teardown sequencer for
packetized transfers. Much more code is now shared
between the data residual and transfer complete cases.
Correct some issues in the packetized status handler.
It used to be possible to CLRCHN our FIFO before status
had fully transferred to the host. We also failed to
handle NONPACKREQ phases that could occur should a CRC
error occur during transmission of the status data packet.
Correct a few big endian issues:
aic79xx.c:
aic79xx_inline.h:
aic79xx_pci.c:
aic79xx_osm.c:
o Always get the SCB's tag via the SCB_GET_TAG acccessor
o Add missing use of byte swapping macros when touching
hscb fields.
o Don't double swap SEEPROM data when it is printed.
Correct a big-endian bug. We cannot assign a
o When assigning a 32bit LE variable to a 64bit LE
variable, we must be explict about how the words
of the 64bit LE variable are initialized. Cast to
(uint32_t*) to do this.
aic79xx.c:
In ahd_clear_critical_section(), hit CRLSCSIINT
after restoring the interrupt masks to avoid what
appears to be a glitch on SCSIINT. Any real SCSIINT
status will be persistent and will immidiately
reset SCSIINT. This clear should only get rid of
spurious SCSIINTs.
This glitch was the cause of the "Unexpected PKT busfree"
status that occurred under high queue full loads
Call ahd_fini_scbdata() after shutdown so that
any ahd_chip_init() routine that might access
SCB data will not access free'd memory.
Reset the bus on an IOERR since the chip doesn't
seem to reset to the new voltage level without
this.
Change offset calculation for scatter gather maps
so that the calculation is correct if an integral
multiple of sg lists does not fit in the allocation
size.
Adjust bus dma tag for data buffers based on 39BIT
addressing flag in our softc.
Use the QFREEZE count to simplify ahd_pause_and_flushworkd().
We can thus rely on the sequencer eventually clearing ENSELO.
In ahd_abort_scbs(), fix a bug that could potentially
corrupt sequencer state. The saved SCB was being
restored in the SCSI mode instead of the saved mode.
It turns out that the SCB did not need to be saved at all
as the scbptr is already restored by all subroutines
called during this function that modify that register.
aic79xx.c:
aic79xx.h:
aic79xx_pci.c:
Add support for parsing the seeprom vital product
data. The VPD data are currently unused.
aic79xx.h:
aic79xx.seq:
aic79xx_pci.c:
Add a firmware workaround to make the LED blink
brighter during packetized operations on the H2A.
aic79xx_inline.h:
The host does not use timer interrupts, so don't
gate our decision on whether or not to unpause
the sequencer on whether or not a timer interrupt
is pending.
2003-05-04 00:20:07 +00:00
|
|
|
AHD_EARLY_REQ_BUG = 0x400000,
|
|
|
|
|
/*
|
|
|
|
|
* The LED does not stay on long enough in packetized modes.
|
|
|
|
|
*/
|
|
|
|
|
AHD_FAINT_LED_BUG = 0x800000
|
2002-06-05 19:52:45 +00:00
|
|
|
} ahd_bug;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Configuration specific settings.
|
|
|
|
|
* The driver determines these settings by probing the
|
|
|
|
|
* chip/controller's configuration.
|
|
|
|
|
*/
|
|
|
|
|
typedef enum {
|
|
|
|
|
AHD_FNONE = 0x00000,
|
Correct spelling errors.
Switch to handling bad SCSI status as a sequencer interrupt
instead of having the kernel proccess these failures via
the completion queue. This is done because:
o The old scheme required us to pause the sequencer and clear
critical sections for each SCB. It seems that these pause
actions, if coincident with a sequencer FIFO interrupt, would
result in a FIFO interrupt getting lost or directing to the
wrong FIFO. This caused hangs when the driver was stressed
under high "queue full" loads.
o The completion code assumed that it was always called with
the sequencer running. This may not be the case in timeout
processing where completions occur manually via
ahd_pause_and_flushwork().
o With this scheme, the extra expense of clearing critical
sections is avoided since the sequencer will only self pause
once all pending selections have cleared and it is not in
a critical section.
aic79xx.c
Add code to handle the new BAD_SCB_STATUS sequencer
interrupt code. This just redirects the SCB through
the already existing ahd_complete_scb() code path.
Remove code in ahd_handle_scsi_status() that paused
the sequencer, made sure that no selections where
pending, and cleared critical sections. Bad
status SCBs are now only processed when all of these
conditions are true.
aic79xx.reg:
Add the BAD_SCB_STATUS sequencer interrupt code.
aic79xx.seq:
When completing an SCB upload to the host, if
we are doing this because the SCB contains non-zero
SCSI status, defer completing the SCB until there
are no pending selection events. When completing
these SCBs, use the new BAD_SCB_STATUS sequencer
interrupt. For all other uploaded SCBs (currently
only for underruns), the SCB is completed via the
normal done queue. Additionally, keep the SCB that
is currently being uploaded on the COMPLETE_DMA_SCB
list until the dma is completed, not just until the
DMA is started. This ensures that the DMA is restarted
properly should the host disable the DMA transfer for
some reason.
In our RevA workaround for Maxtor drives, guard against
the host pausing us while trying to pause I/O until the
first data-valid REQ by clearing the current snapshot
so that we can tell if the transfer has completed prior
to us noticing the REQINIT status.
In cfg4data_intr, shave off an instruction before getting
the data path running by adding an entrypoint to the
overrun handler to also increment the FIFO use count.
In the overrun handler, be sure to clear our LONGJMP
address in both exit paths.
Perform a few sequencer optimizations.
aic79xx.c:
Print the full path from the SCB when a packetized
status overrun occurs.
Remove references to LONGJMP_SCB which is being
removed from firmware usage.
Print the new SCB_FIFO_USE_COUNT field in the
per-SCB section of ahd_dump_card_state(). The
SCB_TAG field is now re-used by the sequencer,
so it no longer makes sense to reference this
field in the kernel driver.
aic79xx.h:
Re-arrange fields in the hardware SCB from largest
size type to smallest. This makes it easier to
move fields without changing field alignment.
The hardware scb tag field is now down near the
"spare" portion of the SCB to facilitate reuse
by the sequencer.
aic79xx.reg:
Remove LONGJMP_ADDR.
Rearrange SCB fields to match aic79xx.h.
Add SCB_FIFO_USE_COUNT as the first byte
of the SCB_TAG field.
aic79xx.seq:
Add a per-SCB "Fifos in use count" field and use
it to determine when it is safe (all data posted)
to deliver status back to the host. The old method
involved polling one or both FIFOs to verify that
the current task did not have pending data. This
makes running down the GSFIFO very cheap, so we
will empty the GSFIFO in one idle loop pass in
all cases.
Use this simplification of the completion process
to prune down the data FIFO teardown sequencer for
packetized transfers. Much more code is now shared
between the data residual and transfer complete cases.
Correct some issues in the packetized status handler.
It used to be possible to CLRCHN our FIFO before status
had fully transferred to the host. We also failed to
handle NONPACKREQ phases that could occur should a CRC
error occur during transmission of the status data packet.
Correct a few big endian issues:
aic79xx.c:
aic79xx_inline.h:
aic79xx_pci.c:
aic79xx_osm.c:
o Always get the SCB's tag via the SCB_GET_TAG acccessor
o Add missing use of byte swapping macros when touching
hscb fields.
o Don't double swap SEEPROM data when it is printed.
Correct a big-endian bug. We cannot assign a
o When assigning a 32bit LE variable to a 64bit LE
variable, we must be explict about how the words
of the 64bit LE variable are initialized. Cast to
(uint32_t*) to do this.
aic79xx.c:
In ahd_clear_critical_section(), hit CRLSCSIINT
after restoring the interrupt masks to avoid what
appears to be a glitch on SCSIINT. Any real SCSIINT
status will be persistent and will immidiately
reset SCSIINT. This clear should only get rid of
spurious SCSIINTs.
This glitch was the cause of the "Unexpected PKT busfree"
status that occurred under high queue full loads
Call ahd_fini_scbdata() after shutdown so that
any ahd_chip_init() routine that might access
SCB data will not access free'd memory.
Reset the bus on an IOERR since the chip doesn't
seem to reset to the new voltage level without
this.
Change offset calculation for scatter gather maps
so that the calculation is correct if an integral
multiple of sg lists does not fit in the allocation
size.
Adjust bus dma tag for data buffers based on 39BIT
addressing flag in our softc.
Use the QFREEZE count to simplify ahd_pause_and_flushworkd().
We can thus rely on the sequencer eventually clearing ENSELO.
In ahd_abort_scbs(), fix a bug that could potentially
corrupt sequencer state. The saved SCB was being
restored in the SCSI mode instead of the saved mode.
It turns out that the SCB did not need to be saved at all
as the scbptr is already restored by all subroutines
called during this function that modify that register.
aic79xx.c:
aic79xx.h:
aic79xx_pci.c:
Add support for parsing the seeprom vital product
data. The VPD data are currently unused.
aic79xx.h:
aic79xx.seq:
aic79xx_pci.c:
Add a firmware workaround to make the LED blink
brighter during packetized operations on the H2A.
aic79xx_inline.h:
The host does not use timer interrupts, so don't
gate our decision on whether or not to unpause
the sequencer on whether or not a timer interrupt
is pending.
2003-05-04 00:20:07 +00:00
|
|
|
AHD_BOOT_CHANNEL = 0x00001,/* We were set as the boot channel. */
|
2002-06-05 19:52:45 +00:00
|
|
|
AHD_USEDEFAULTS = 0x00004,/*
|
|
|
|
|
* For cards without an seeprom
|
|
|
|
|
* or a BIOS to initialize the chip's
|
|
|
|
|
* SRAM, we use the default target
|
|
|
|
|
* settings.
|
|
|
|
|
*/
|
|
|
|
|
AHD_SEQUENCER_DEBUG = 0x00008,
|
|
|
|
|
AHD_RESET_BUS_A = 0x00010,
|
|
|
|
|
AHD_EXTENDED_TRANS_A = 0x00020,
|
|
|
|
|
AHD_TERM_ENB_A = 0x00040,
|
|
|
|
|
AHD_SPCHK_ENB_A = 0x00080,
|
|
|
|
|
AHD_STPWLEVEL_A = 0x00100,
|
|
|
|
|
AHD_INITIATORROLE = 0x00200,/*
|
|
|
|
|
* Allow initiator operations on
|
|
|
|
|
* this controller.
|
|
|
|
|
*/
|
|
|
|
|
AHD_TARGETROLE = 0x00400,/*
|
|
|
|
|
* Allow target operations on this
|
|
|
|
|
* controller.
|
|
|
|
|
*/
|
|
|
|
|
AHD_RESOURCE_SHORTAGE = 0x00800,
|
|
|
|
|
AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */
|
|
|
|
|
AHD_INT50_SPEEDFLEX = 0x02000,/*
|
|
|
|
|
* Internal 50pin connector
|
|
|
|
|
* sits behind an aic3860
|
|
|
|
|
*/
|
|
|
|
|
AHD_BIOS_ENABLED = 0x04000,
|
|
|
|
|
AHD_ALL_INTERRUPTS = 0x08000,
|
|
|
|
|
AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */
|
|
|
|
|
AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */
|
|
|
|
|
AHD_CURRENT_SENSING = 0x40000,
|
|
|
|
|
AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */
|
2002-12-01 08:13:37 +00:00
|
|
|
AHD_HP_BOARD = 0x100000,
|
aic79xx.c:
Implement the SCB_SILENT flag. This is useful for
hushing up the driver during DV or other operations
that we expect to cause transmission errors. The
messages will still print if the SHOW_MASKED_ERRORS
debug option is enabled.
Save and restore the NEGOADDR address when setting
new transfer settings. The sequencer performs lookups
in the negotiation table too and it expects NEGOADDR
to remain consistent across pause/unpause sessions.
Consistently use "offset" instead of "period" to determine
if we are running sync or not.
Add a SHOW_MESSAGES diagnostic for when we assert ATN
during message processing.
Print out IU, QAS, and RTI features when showing transfer options.
Limit the syncrate after all option conformance
changes have taken place in ahd_devlimited_syncrate.
Changes in options may change the final syncrate we
accept.
Keep a copy of the hs_mailbox in our softc so that
we can perform read/modify/write operations on the
hs_mailbox without having to pause the sequencer to
read the last written value. Use the ENINT_COALESS
flag in the hs_mailbox to toggle interrupt coalessing.
Add entrypoints for enabling interrupt coalessing and
setting both a timeout (how long to wait for commands
to be coalessed) and a maximum commands to coaless value.
Add a statistics timer that decides when to enable or
disable interrupt coalessing based on load.
Add a routine, ahd_reset_cmds_pending() which is used
to update the CMDS_PENDING sequencer variable whenever
error recovery compeltes SCBs without notifying the
sequencer. Since ahd_reset_cmds_pending is called
during ahd_unpause() only if we've aborted SCBs, its
call to ahd_flush_qoutfifo should not cause recursion
through ahd_run_qoutfifo(). A panic has been added to
ensure that this recursion does not occur.
In ahd_search_qinfifo, update the CMDS_PENDING sequencer
variable directly. ahd_search_qinififo can be called
in situations where using ahd_reset_cmds_pending() might
cause recursion. Since we can safely determine the
exact number to reduce CMDS_PENDING by in this scenario
without running the qoutfifo, the manual update is sufficient.
Clean up diagnostics.
Add ahd_flush_qoutfifo() which will run the qoutfifo
as well as complete any commands sitting on the
sequencer's COMPLETE_SCB lists or the good status FIFO.
Use this routine in several places that did similar
things in an add-hoc, but incomplete, fashion. A call
to this routine was also added to ahd_abort_scbs() to
close a race.
In ahd_pause_and_flushwork() only return once selections
are safely disabled. Flush all completed commands via
ahd_flush_qoutfifo().
Remove "Now packetized" diagnostic now that this
information is incorperated into the actual negotiation
messages that are displayed.
When forcing renegotiation, don't clober the current
ppr_options. Much of the driver uses this information
to determine if we are currently packetized or not.
Remove some stray spaces at column 1 in ahd_set_tags.
When complaining about getting a host message loop
request with no pending messages, print out the
SCB_CONTROL register down on the card.
Modify the ahd_sent_msg() routine to handle a search
for an outgoing identify message. Use this to detect
a msg reject on an identify message which typically
indicates that the target thought we were packetized.
Force a renegotiation in this case.
In ahd_search_qinfifo(), wait more effectively for SCB
DMA activities to cease. We also disable SCB fetch
operations since we are about to change the qinfifo
and any fetch in progress will likely be invalidated.
In ahd_qinfifo_count(), fix the qinfifo empty case.
In ahd_dump_card_state(), print out CCSCBCTL in the
correct mode.
If we are a narrow controller, don't set the current
width to unknown when forcing a future negotiation.
This just confuses the code into attempting a wide
negotiation on a narrow bus.
Add support for task management function completions.
Modify ahd_handle_devreset so that it can handle
lun resets in addition to target resets. Use
ahd_handle_devreset for lun and target reset task
management functions.
Handle the abort task TMF race case better. We now
wait until any current selections are over and then
set the TMF back to zero. This should cause the sequencer
to ignore the abort TMF completion should it occur.
Correct a bug in the illegal phase handler that
caused us to drop down to narrow when handling the
unexpected command phase case after 3rd party
reset of a packetized device.
Indicate the features, bugs, and flags set in the softc
that are used to control firmware patch download when
booting verbose.
aic79xx.h:
Add coalessing and HS_MAILBOX fields.
Add per-softc variables for the stats "daemon".
Add a debug option for interrupt coalessing activities.
Add two new softc flags:
o AHD_UPDATE_PEND_CMDS
Run ahd_reset_cmds_pending() on the next unpause.
o AHD_RUNNING_QOUTFIFO
Used to catch recursion through ahd_run_qoutfifo().
aic79xx.reg:
Correct register addresses related to the software timer
and the DFDBCTL register.
Add constants paramaterizing the software timer.
Add scratch ram locations for storing interrupt coalessing
tunables.
Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2.
In at least the REV A, these are writable bits. We make
use of that for a swtimer workaround in the sequencer.
Since HS_MAILBOX autoclears, provide a sequencer variable
to store its contents.
Add SEQINT codes for handling task management completions.
aic79xx.seq:
Correct ignore wide residue processing check for
a wide negotiation being in effect. We must be
in the SCSI register window in order to access the
negotiation table.
Use the software timer and a commands completed count to
implement interrupt coalessing. The command complete is
deferred until either the maximum command threshold or a
the expiration of a command deferral timer. If we have
more SCBs to complete to the host (sitting in COMPLETE_SCB
lists), always try to coaless them up to our coalessing limit.
If coalessing is enabled, but we have fewer commands oustanting
than the host's min coalessing limit, complete the command
immediately.
Add code to track the number of commands outstanding.
Commands are outstanding from the time they are placed
into the execution queue until the DMA to post completion
is setup.
Add a workaround for intvec_2 interrupts on the H2A4.
In H2A4, the mode pointer is not saved for intvec2, but
is restored on iret. This can lead to the restoration
of a bogus mode ptr. Manually clear the intmask bits and
do a normal return to compensate. We use intvec_2 to
track interrupt coalessing timeouts.
Since we cannot disable the swtimer's countdown, simply
mask its interrupt once we no longer care about it firing.
In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime
we are notified of an HS_MAILBOX update via the
HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a
local copy of persistant portions of the HS_MAILBOX as
the mailbox auto-clears on any read.
Move the test for the cfg4istat interrupt up an instruction
to hopefully close a race between the next outgoing selection
and our disabling of selections.
Add a missing ret to the last instruction in load_overrun_buf.
Add notifications to the host of task management
completions as well as the completions for commands
that completed successfully before their corresponding
TMF could be sent.
Hold a critical section during select-out processing
until we have a fully identified connection. This
removes a race condition with the legacy abort handler.
Correct a few spelling errors in some comments.
aic79xx_inline.h:
Call ahd_reset_cmds_pending() in ahd_unpause if required.
Update cmdcmplt interrupt statistics in our interrupt
handler.
Allow callers to ahd_send_scb() to set the task management
function.
aic79xx_pci.c:
Disable SERR and pause the controller prior to performing
our mmapped I/O test. The U320 controllers do not support
"auto-access-pause".
aic79xx_osm.c:
Set the task management function now that
ahd_send_scb() doesn't do it for us. We
also perform a lun reset in response to BDR
requests to packetized devices.
2003-01-20 20:17:35 +00:00
|
|
|
AHD_RESET_POLL_ACTIVE = 0x200000,
|
|
|
|
|
AHD_UPDATE_PEND_CMDS = 0x400000,
|
2003-06-28 04:45:25 +00:00
|
|
|
AHD_RUNNING_QOUTFIFO = 0x800000,
|
ahc_eisa.c:
ahc_pci.c:
ahd_pci.c:
aic7xxx.c:
aic79xx.c:
aic_osm_lib.c:
aic_osm_lib.h:
Use common OSM routines from aic_osm_lib for bus dma operations,
delay routines, accessing CCBs, byte swapping, etc.
aic7xxx_pci.c:
Provide a better description for the 2915/30LP on attach.
aic7xxx.c:
aic79xx.c:
aic7770.c:
aic79xx_pci.c:
aic7xxx_pci.c:
aic7xxx_93cx6.c:
Move FBSDID behind an ifdef so that these core files will
still compile under other OSes.
aic79xx.h:
aic79xx_pci.c:
aic79xx.seq:
To speed up non-packetized CDB delivery in Rev B, all CDB
acks are "released" to the output sync as soon as the
command phase starts. There is only one problem with this
approach. If the target changes phase before all data are
sent, we have left over acks that can go out on the bus in
a data phase. Due to other chip contraints, this only
happens if the target goes to data-in, but if the acks go
out before we can test SDONE, we'll think that the transfer
has completed successfully. Work around this by taking
advantage of the 400ns or 800ns dead time between command
phase and the REQ of the new phase. If the transfer has
completed successfully, SCSIEN should fall *long* before we
see a phase change. We thus treat any phasemiss that
occurs before SCSIEN falls as an incomplete transfer.
aic79xx.h:
Add the AHD_FAST_CDB_DELIVERY feature.
aic79xx_pci.c:
Set AHD_FAST_CDB_DELIVERY for all Rev. B parts.
aic79xx.seq:
Test for PHASEMIS in the command phase for
all AHD_FAST_CDB_DELIVERY controlelrs.
ahd_pci.c:
ahc_pci.c:
aic7xxx.h:
aic79xx.h:
Move definition of controller BAR offsets to core header files.
aic7xxx.c:
aic79xx.c:
In the softc free routine, leave removal of a softc from the
global list of softcs to the OSM (the caller of this routine).
This allows us to avoid holding the softc list_lock during device
destruction where we may have to sleep waiting for our recovery
thread to halt.
ahc_pci.c:
Use ahc_pci_test_register access to validate I/O mapped in
addition to the tests already performed for memory mapped
access.
Remove unused ahc_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
ahd_pci.c:
Remove reduntant definition of controller BAR offsets. These
are also defined in aic79xx.h.
Remove unused ahd_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
aic7xxx.c:
aic79xx.c:
aic79xx.h:
aic7xxx.h:
aic7xxx_osm.c:
aic79xx_osm.c:
Move timeout handling to the driver cores. In the case
of the aic79xx driver, the algorithm has been enhanced
to try target resets before performing a bus reset. For
the aic7xxx driver, the algorithm is unchanged. Although
the drivers do not currently sleep during recovery (recovery
is timeout driven), the cores do expect all processing to
be performed via a recovery thread. Our timeout handlers
are now little stubs that wakeup the recovery thread.
aic79xx.c:
aic79xx.h:
aic79xx_inline.h:
Change shared_data allocation to use a map_node so
that the sentinel hscb can use this map node in
ahd_swap_with_next_hscb. This routine now swaps
the hscb_map pointer in additon to the hscb
contents so that any sync operations occur on
the correct map.
physaddr -> busaddr
Pointed out by: Jason Thorpe <thorpej@wasabisystems.com>
aic79xx.c:
Make more use of the in/out/w/l/q macros for accessing
byte registers in the chip.
Correct some issues in the ahd_flush_qoutfifo() routine.
o Run the qoutfifo only once the command channel
DMA engine has been halted. This closes a window
where we might have missed some entries.
o Change ahd_run_data_fifo() to not loop to completion.
If we happen to start on the wrong FIFO and the other
FIFO has a snapshot savepointers, we might deadlock.
This required our delay between FIFO tests to be
moved to the ahd_flush_qoutfifo() routine.
o Update/add comments.
o Remove spurious test for COMPLETE_DMA list being empty
when completing transactions from the GSFIFO with
residuals. The SCB must be put on the COMPLETE_DMA
scb list unconditionally.
o When halting command channel DMA activity, we must
disable the DMA channel in all cases but an update
of the QOUTFIFO. The latter case is required so
that the sequencer will update its position in the
QOUTFIFO. Previously, we left the channel enabled
for all "push" DMAs. This left us vulnerable to
the sequencer handling an SCB push long after that
SCB was already processed manually by this routine.
o Correct the polarity of tests involving
ahd_scb_active_in_fifo(). This routine returns
non-zero for true.
Return to processing bad status completions through
the qoutfifo. This reduces the time that the sequencer
is kept paused when handling transactions with bad
status or underruns.
When waiting for the controller to quiece selections,
add a delay to our loop. Otherwise we may fail to wait
long enough for the sequencer to comply.
On H2A4 hardware, use the slow slewrate for non-paced
transfers. This mirrors what the Adaptec Windows
drivers do.
On the Rev B. only slow down the CRC timing for
older U160 devices that might need the slower timing.
We define "older" as devices that do not support
packetized protocol.
Wait up to 5000 * 5us for the SEEPROM to become unbusy.
Write ops seem to take much longer than read ops.
aic79xx.seq:
For controllers with the FAINT_LED bug, turn the diagnostic
led feature on during selection and reselection. This covers
the non-packetized case. The LED will be disabled for
non-packetized transfers once we return to the top level idle
loop. Add more comments about the busy LED workaround.
Extend a critical section around the entire
command channel idle loop process. Previously
the portion of this handler that directly manipulated
the linked list of completed SCBs was not protected.
This is the likely cause of the recent reports of
commands being completed twice by the driver.
Extend critical sections across the test for,
and the longjump to, longjump routines. This
prevents the firmware from trying to jump to
a longjmp handler that was just cleared by the
host.
Improve the locations of several critical section
begin and end points. Typically these changes
remove instructions that did not need to be
inside a critical section.
Close the "busfree after selection, but before busfree
interrupts can be enabled" race to just a single sequencer
instruction. We now test the BSY line explicitly before
clearing the busfree status and enabling the busfree
interrupt.
Close a race condition in the processing of HS_MAILBOX
updates. We now clear the "updated" status before the
copy. This ensures that we don't accidentally clear
the status incorrectly when the host sneaks in an update
just after our last copy, but before we clear the status.
This race has never been observed.
Don't re-enable SCSIEN if we lose the race to disable SCSIEN
in our interrupt handler's workaround for the RevA data-valid
too early issue.
aic79xx_inline.h:
Add comments indicating that the order in which bytes are
read or written in ahd_inw and ahd_outw is important. This
allows us to use these inlines when accessing registers with
side-effects.
aic79xx_pci.c:
The 29320 and the 29320B are 7902 not 7901 based products.
Correct the driver banner.
aic7xxx.h:
Enable the use of the auto-access pause feature
on the aic7870 and aic7880. It was disabled due
to an oversight.
aic7xxx.reg:
Move TARG_IMMEDIATE_SCB to alias LAST_MSG to
avoid leaving garbage in MWI_RESIDUAL. This
prevents spurious overflows whn operating target
mode on controllers that require the MWI_RESIDUAL
work-around.
aic7xxx.seq:
AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag.
Reference the correct softc field when testing
for its presence.
Set the NOT_IDENTIFIED and NO_CDB_SENT bits
in SEQ_FLAGS to indicate that the nexus is
invalid in await busfree.
aic7xxx_93cx6.c:
Add support for the C56/C66 versions of the EWEN and EWDS
commands.
aic7xxx.c:
aic7xxx_pci.c:
Move test for the validity of left over BIOS data
to ahc_test_register_access(). This guarantees that
any left over CHIPRST value is not clobbered by our
register access test and lost to the test that was
in ahc_reset.
2003-12-17 00:02:10 +00:00
|
|
|
AHD_HAD_FIRST_SEL = 0x1000000,
|
aic79xx.c:
aic79xx.seq:
Convert the COMPLETE_DMA_SCB list to an "stailq". This allows us to
safely keep the SCB that is currently being DMA'ed back the host on
the head of the list while processing completions off of the bus. The
newly completed SCBs are appended to the tail of the queue. In the
past, we just dequeued the SCB that was in flight from the list, but
this could result in a lost completion should the host perform certain
types of error recovery that must cancel all in-flight SCB DMA operations.
Switch from using a 16bit completion entry, holding just the tag and the
completion valid bit, to a 64bit completion entry that also contains a
"status packet valid" indicator. This solves two problems:
o The SCB DMA engine on at least Rev B. silicon does not properly deal
with a PCI disconnect that occurs at a non-64bit aligned offset in the
chips "source buffer". When the transfer is resumed, the DMA engine
continues at the correct offset, but may wrap to the head of the buffer
causing duplicate completions to be reported to the host. By using a
completion buffer in host memory that is 64bit aligned and using 64bit
completion entries, such disconnects should only occur at aligned addresses.
This assumes that the host bridge will only disconnect on cache-line
boundaries and that cache-lines are multpiles of 64bits.
o By embedding the status information in the completion entry we can avoid
an extra memory reference to the HSCB for commands that complete without
error.
Use the comparison of a "host freeze count" and a "sequencer freeze count"
to allow the host to process most SCBs that complete with non-zero status
without having to clear critical sections. Instead the host can just pause the
sequencer, performs any necessary cleanup in the waiting for selection list,
increments its freeze count on the controller, and unpauses. This is only
possible because the sequencer defers completions of SCBs with bad status
until after all pending selections have completed. The sequencer then avoids
referencing any data structures the host may touch during completion of the
SCB until the freeze counts match.
aic79xx.c:
Change the strategy for allocating our sentinal HSCB for the QINFIFO. In
the past, this allocation was tacked onto the QOUTFIFO allocation. Now that
the qoutfifo has grown to accomodate larger completion entries, the old
approach will result in a 64byte allocation that costs an extra page of
coherent memory. We now do this extra allocation via ahd_alloc_scbs()
where the "unused space" can be used to allocate "normal" HSCBs.
In our packetized busfree handler, use the ENSELO bit to differentiate
between packetized and non-packetized unexpected busfree events that
occur just after selection, but before the sequencer has had the oportunity
to service the selection.
When cleaning out the waiting for selection list, use the SCSI mode
instead of the command channel mode. The SCB pointer in the command
channel mode may be referenced by the SCB dma engine even while the
sequencer is paused, whereas the SCSI mode SCB pointer is only accessed
by the sequencer.
Print the "complete on qfreeze" sequencer SCB completion list in
ahd_dump_card_state(). This list holds all SCB completions that are deferred
until a pending select-out qfreeze event has taken effect.
aic79xx.h:
Add definitions and structures to handle the new SCB completion scheme.
Add a controller flag that indicates if the controller is in HostRAID
mode.
aic79xx.reg:
Remove macros used for toggling from one data fifo mode to the other.
They have not been in use for some time.
Add scratch ram fields for our new qfreeze count scheme, converting
the complete dma list into an "stailq", and providing for the "complete
on qfreeze" SCB completion list. Some other fields were moved to retain
proper field alignment (alignment >= field size in bytes).
aic79xx.seq:
Add code to our idle loop to:
o Process deferred completions once a qfreeze event has taken full
effect.
o Thaw the queue once the sequencer and host qfreeze counts match.
Generate 64bit completion entries passing the SCB_SGPTR field as the
"good status" indicator. The first bit in this field is only set if
we have a valid status packet to send to the host.
Convert the COMPLETE_DMA_SCB list to an "stailq".
When using "setjmp" to register an idle loop handler, do not combine
the "ret" with the block move to pop the stack address in the same
instruction. At least on the A, this results in a return to the setjmp
caller, not to the new address at the top of the stack. Since we want
the latter (we want the newly registered handler to only be invoked from
the idle loop), we must use a separate ret instruction.
Add a few missing critical sections.
Close a race condition that can occur on Rev A. silicon. If both FIFOs
happen to be allocated before the sequencer has a chance to service the
FIFO that was allocated first, we must take special care to service the
FIFO that is not active on the SCSI bus first. This guarantees that a
FIFO will be freed to handle any snapshot requests for the FIFO that is
still on the bus. Chosing the incorrect FIFO will result in deadlock.
Update comments.
aic79xx_inline.h
Correct the offset calculation for the syncing of our qoutfifo.
Update ahd_check_cmdcmpltqueues() for the larger completion entries.
aic79xx_pci.c:
Attach to HostRAID controllers by default. In the future I may add a
sysctl to modify the behavior, but since FreeBSD does not have any
HostRAID drivers, failing to attach just results in more email and
bug reports for the author.
MFC After: 1week
2004-02-04 16:38:38 +00:00
|
|
|
AHD_SHUTDOWN_RECOVERY = 0x2000000, /* Terminate recovery thread. */
|
|
|
|
|
AHD_HOSTRAID_BOARD = 0x4000000
|
2002-06-05 19:52:45 +00:00
|
|
|
} ahd_flag;
|
|
|
|
|
|
|
|
|
|
/************************* Hardware SCB Definition ***************************/
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The driver keeps up to MAX_SCB scb structures per card in memory. The SCB
|
Correct spelling errors.
Switch to handling bad SCSI status as a sequencer interrupt
instead of having the kernel proccess these failures via
the completion queue. This is done because:
o The old scheme required us to pause the sequencer and clear
critical sections for each SCB. It seems that these pause
actions, if coincident with a sequencer FIFO interrupt, would
result in a FIFO interrupt getting lost or directing to the
wrong FIFO. This caused hangs when the driver was stressed
under high "queue full" loads.
o The completion code assumed that it was always called with
the sequencer running. This may not be the case in timeout
processing where completions occur manually via
ahd_pause_and_flushwork().
o With this scheme, the extra expense of clearing critical
sections is avoided since the sequencer will only self pause
once all pending selections have cleared and it is not in
a critical section.
aic79xx.c
Add code to handle the new BAD_SCB_STATUS sequencer
interrupt code. This just redirects the SCB through
the already existing ahd_complete_scb() code path.
Remove code in ahd_handle_scsi_status() that paused
the sequencer, made sure that no selections where
pending, and cleared critical sections. Bad
status SCBs are now only processed when all of these
conditions are true.
aic79xx.reg:
Add the BAD_SCB_STATUS sequencer interrupt code.
aic79xx.seq:
When completing an SCB upload to the host, if
we are doing this because the SCB contains non-zero
SCSI status, defer completing the SCB until there
are no pending selection events. When completing
these SCBs, use the new BAD_SCB_STATUS sequencer
interrupt. For all other uploaded SCBs (currently
only for underruns), the SCB is completed via the
normal done queue. Additionally, keep the SCB that
is currently being uploaded on the COMPLETE_DMA_SCB
list until the dma is completed, not just until the
DMA is started. This ensures that the DMA is restarted
properly should the host disable the DMA transfer for
some reason.
In our RevA workaround for Maxtor drives, guard against
the host pausing us while trying to pause I/O until the
first data-valid REQ by clearing the current snapshot
so that we can tell if the transfer has completed prior
to us noticing the REQINIT status.
In cfg4data_intr, shave off an instruction before getting
the data path running by adding an entrypoint to the
overrun handler to also increment the FIFO use count.
In the overrun handler, be sure to clear our LONGJMP
address in both exit paths.
Perform a few sequencer optimizations.
aic79xx.c:
Print the full path from the SCB when a packetized
status overrun occurs.
Remove references to LONGJMP_SCB which is being
removed from firmware usage.
Print the new SCB_FIFO_USE_COUNT field in the
per-SCB section of ahd_dump_card_state(). The
SCB_TAG field is now re-used by the sequencer,
so it no longer makes sense to reference this
field in the kernel driver.
aic79xx.h:
Re-arrange fields in the hardware SCB from largest
size type to smallest. This makes it easier to
move fields without changing field alignment.
The hardware scb tag field is now down near the
"spare" portion of the SCB to facilitate reuse
by the sequencer.
aic79xx.reg:
Remove LONGJMP_ADDR.
Rearrange SCB fields to match aic79xx.h.
Add SCB_FIFO_USE_COUNT as the first byte
of the SCB_TAG field.
aic79xx.seq:
Add a per-SCB "Fifos in use count" field and use
it to determine when it is safe (all data posted)
to deliver status back to the host. The old method
involved polling one or both FIFOs to verify that
the current task did not have pending data. This
makes running down the GSFIFO very cheap, so we
will empty the GSFIFO in one idle loop pass in
all cases.
Use this simplification of the completion process
to prune down the data FIFO teardown sequencer for
packetized transfers. Much more code is now shared
between the data residual and transfer complete cases.
Correct some issues in the packetized status handler.
It used to be possible to CLRCHN our FIFO before status
had fully transferred to the host. We also failed to
handle NONPACKREQ phases that could occur should a CRC
error occur during transmission of the status data packet.
Correct a few big endian issues:
aic79xx.c:
aic79xx_inline.h:
aic79xx_pci.c:
aic79xx_osm.c:
o Always get the SCB's tag via the SCB_GET_TAG acccessor
o Add missing use of byte swapping macros when touching
hscb fields.
o Don't double swap SEEPROM data when it is printed.
Correct a big-endian bug. We cannot assign a
o When assigning a 32bit LE variable to a 64bit LE
variable, we must be explict about how the words
of the 64bit LE variable are initialized. Cast to
(uint32_t*) to do this.
aic79xx.c:
In ahd_clear_critical_section(), hit CRLSCSIINT
after restoring the interrupt masks to avoid what
appears to be a glitch on SCSIINT. Any real SCSIINT
status will be persistent and will immidiately
reset SCSIINT. This clear should only get rid of
spurious SCSIINTs.
This glitch was the cause of the "Unexpected PKT busfree"
status that occurred under high queue full loads
Call ahd_fini_scbdata() after shutdown so that
any ahd_chip_init() routine that might access
SCB data will not access free'd memory.
Reset the bus on an IOERR since the chip doesn't
seem to reset to the new voltage level without
this.
Change offset calculation for scatter gather maps
so that the calculation is correct if an integral
multiple of sg lists does not fit in the allocation
size.
Adjust bus dma tag for data buffers based on 39BIT
addressing flag in our softc.
Use the QFREEZE count to simplify ahd_pause_and_flushworkd().
We can thus rely on the sequencer eventually clearing ENSELO.
In ahd_abort_scbs(), fix a bug that could potentially
corrupt sequencer state. The saved SCB was being
restored in the SCSI mode instead of the saved mode.
It turns out that the SCB did not need to be saved at all
as the scbptr is already restored by all subroutines
called during this function that modify that register.
aic79xx.c:
aic79xx.h:
aic79xx_pci.c:
Add support for parsing the seeprom vital product
data. The VPD data are currently unused.
aic79xx.h:
aic79xx.seq:
aic79xx_pci.c:
Add a firmware workaround to make the LED blink
brighter during packetized operations on the H2A.
aic79xx_inline.h:
The host does not use timer interrupts, so don't
gate our decision on whether or not to unpause
the sequencer on whether or not a timer interrupt
is pending.
2003-05-04 00:20:07 +00:00
|
|
|
* consists of a "hardware SCB" mirroring the fields available on the card
|
2002-06-05 19:52:45 +00:00
|
|
|
* and additional information the kernel stores for each transaction.
|
|
|
|
|
*
|
|
|
|
|
* To minimize space utilization, a portion of the hardware scb stores
|
|
|
|
|
* different data during different portions of a SCSI transaction.
|
|
|
|
|
* As initialized by the host driver for the initiator role, this area
|
|
|
|
|
* contains the SCSI cdb (or a pointer to the cdb) to be executed. After
|
|
|
|
|
* the cdb has been presented to the target, this area serves to store
|
|
|
|
|
* residual transfer information and the SCSI status byte.
|
|
|
|
|
* For the target role, the contents of this area do not change, but
|
|
|
|
|
* still serve a different purpose than for the initiator role. See
|
|
|
|
|
* struct target_data for details.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Status information embedded in the shared poriton of
|
|
|
|
|
* an SCB after passing the cdb to the target. The kernel
|
|
|
|
|
* driver will only read this data for transactions that
|
|
|
|
|
* complete abnormally.
|
|
|
|
|
*/
|
|
|
|
|
struct initiator_status {
|
|
|
|
|
uint32_t residual_datacnt; /* Residual in the current S/G seg */
|
|
|
|
|
uint32_t residual_sgptr; /* The next S/G for this transfer */
|
|
|
|
|
uint8_t scsi_status; /* Standard SCSI status byte */
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct target_status {
|
|
|
|
|
uint32_t residual_datacnt; /* Residual in the current S/G seg */
|
|
|
|
|
uint32_t residual_sgptr; /* The next S/G for this transfer */
|
|
|
|
|
uint8_t scsi_status; /* SCSI status to give to initiator */
|
|
|
|
|
uint8_t target_phases; /* Bitmap of phases to execute */
|
|
|
|
|
uint8_t data_phase; /* Data-In or Data-Out */
|
|
|
|
|
uint8_t initiator_tag; /* Initiator's transaction tag */
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Initiator mode SCB shared data area.
|
|
|
|
|
* If the embedded CDB is 12 bytes or less, we embed
|
|
|
|
|
* the sense buffer address in the SCB. This allows
|
aic79xx.c:
Clear the LQICRC_NLQ status should it pop up after we have
already handled the SCSIPERR. During some streaming operations
this status can be delayed until the stream ends. Without this
change, the driver would complain about a "Missing case in
ahd_handle_scsiint".
In the LQOBUSFREE handler...
Don't return the LQOMGR back to the idle state until after
we have cleaned up ENSELO and any status related to this
selection. The last thing we need is the LQO manager starting
another select-out before we have updated the execution queue.
It is not clear whether the LQOMGR would, or would not
start a new selection early.
Make sure ENSELO is off prior to clearing SELDO by flushing
device writes.
Move assignment of the next target SCB pointer inside of
an if to make the code clearer. The effect is the same.
Dump card state in both "Unexpected PKT busfree" paths.
In ahd_reset(), set the chip to SCSI mode before reading SXFRCTL1.
That register only exists in the SCSI mode. Also set the mode
explicitly to the SCSI mode after chip reset due to paranoia.
Re-arrange code so that SXFRCTL1 is restored as quickly after the
chip reset as possible.
S/G structurs must be 8byte aligned. Make this official by saying
so in our DMA tag.
Disable CIO bus stretch on MDFFSTAT if SHVALID is about to come
true. This can cause a CIO bus lockup if a PCI or PCI-X error
occurs while the stretch is occurring - the host cannot service
the PCI-X error since the CIO bus is locked out and SHVALID will
never resolve. The stretch was added in the Rev B to simplify the
wait for SHVALID to resolve, but the code to do this in the open
source sequencer is so simple it was never removed.
Consistently use MAX_OFFSET for the user max syncrate set from
non-volatile storage. This ensures that the offset does not
conflict with AH?_OFFSET_UNKNOWN.
Have ahd_pause_and_flushwork set the mode to ensure that it has
access to the registers it checks. Also modify the checking of
intstat so that the check against 0xFF can actually succeed if
the INT_PEND mask is something other than 0xFF. Although there
are no cardbus U320 controllers, this check may be needed to
recover from a hot-plug PCI removal that occurs without informing
the driver.
Fix a typo. sg_prefetch_cnt -> sg_prefetch_align. This fixes
an infinite loop at card initialization if the cacheline size is 0.
aic79xx.h:
Add AHD_EARLY_REQ_BUG bug flag.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
Change AH?_OFFSET_UNKNOWN to 0xFF. This is a value that the
curr->offset can never be, unlike '0' which we previously used.
This fixes code that only checks for a non-zero offset to
determine if a sync negotiation is required since it will fire
in the unknown case even if the goal is async.
aic79xx.reg:
Add comments for LQISTAT bits indicating their names in the 7902
data book. We use slightly different and more descriptive names
in the firmware.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
aic79xx.seq:
Update comments regarding rundown of the GSFIFO to reflect reality.
Fix spelling errors.
Since we use an 8byte address and 1 byte length, shorten the size
of a block move for the legacy DMA'ed CDB case from 11 to 9 bytes.
Remove code that, assuming the abort pending feature worked, would
set MK_MESSAGE in the SCB's control byte on completion to catch
invalid reselections. Since we don't see interrupts for completed
selections, this status update could occur prior to us noticing the
SELDO. The "select-out" queue logic will get confused by the
MK_MESSAGE bit being set as this is used to catch packatized
connections where we select-out with ATN. Since the abort pending
feature doesn't work on any released controllers yet, this code was
never executed.
Add support for the AHD_EARLY_REQ_BUG. Don't ignore persistent REQ
assertions just because they were asserted within the bus settle delay
window. This allows us to tolerate devices like the GEM318 that
violate the SCSI spec.
Remove unintentional settnig of SG_CACHE_AVAIL. Writing this bit
should have no effect, but who knows...
On the Rev A, we must wait for HDMAENACK before loading additional
segments to avoid clobbering the address of the first segment in
the S/G FIFO. This resolves data-corruption issues with certain
IBM (now Hitachi) and Fujitsu U320 drives.
Rearrange calc_residual to avoid an extra jmp instruction.
On RevA Silicon, if the target returns us to data-out after we
have already trained for data-out, it is possible for us to
transition the free running clock to data-valid before the required
100ns P1 setup time (8 P1 assertions in fast-160 mode). This will
only happen if this L-Q is a continuation of a data transfer for
which we have already prefetched data into our FIFO (LQ/Data
followed by LQ/Data for the same write transaction). This can
cause some target implementations to miss the first few data
transfers on the bus. We detect this situation by noticing that
this is the first data transfer after an LQ (LQIWORKONLQ true),
that the data transfer is a continuation of a transfer already
setup in our FIFO (SAVEPTRS interrupt), and that the transaction
is a write (DIRECTION set in DFCNTRL). The delay is performed by
disabling SCSIEN until we see the first REQ from the target.
Only compile in snapshot savepointers handler for RevA silicon
where it is enabled.
Handle the cfg4icmd packetized interrupt. We just need to load
the address and count, start the DMA, and CLRCHN once the transfer
is complete.
Fix an oversight in the overrun handler for packetized status
operations. We need to wait for either CTXTDONE or an overrun
when checking for an overrun. The previous code did not wait
and thus could decide that no overrun had occurred even though
an overrun will occur on the next data-valid req. Add some
comment to this section for clarity.
Use LAST_SEG_DONE instead of LASTSDONE for testing transfer
completion in the packetized status case. LASTSDONE may come up
more quickly since it only records completion on the SCSI side,
but since LAST_SEG_DONE is used everywhere else (and needs to be),
this is less confusing.
Add a missing invalidation of the longjmp address in the non-pack
handler. This code needs additional review.
aic79xx_inline.h:
Fix spelling error.
aic79xx_osm.c:
Set the cdb length for CDBs dma'ed from host memory.
Add a comment indicating that, should CAM start supporting cdbs
larger than 16bytes, the driver could store the CDB in the status
buffer.
aic79xx_pci.c:
Add a table entry for the 39320A.
Added a missing comma to an error string table.
Fix spelling errors.
2003-02-27 23:23:16 +00:00
|
|
|
* us to retrieve sense information without interrupting
|
2002-06-05 19:52:45 +00:00
|
|
|
* the host in packetized mode.
|
|
|
|
|
*/
|
|
|
|
|
typedef uint32_t sense_addr_t;
|
|
|
|
|
#define MAX_CDB_LEN 16
|
|
|
|
|
#define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t))
|
|
|
|
|
union initiator_data {
|
aic79xx.c:
Clear the LQICRC_NLQ status should it pop up after we have
already handled the SCSIPERR. During some streaming operations
this status can be delayed until the stream ends. Without this
change, the driver would complain about a "Missing case in
ahd_handle_scsiint".
In the LQOBUSFREE handler...
Don't return the LQOMGR back to the idle state until after
we have cleaned up ENSELO and any status related to this
selection. The last thing we need is the LQO manager starting
another select-out before we have updated the execution queue.
It is not clear whether the LQOMGR would, or would not
start a new selection early.
Make sure ENSELO is off prior to clearing SELDO by flushing
device writes.
Move assignment of the next target SCB pointer inside of
an if to make the code clearer. The effect is the same.
Dump card state in both "Unexpected PKT busfree" paths.
In ahd_reset(), set the chip to SCSI mode before reading SXFRCTL1.
That register only exists in the SCSI mode. Also set the mode
explicitly to the SCSI mode after chip reset due to paranoia.
Re-arrange code so that SXFRCTL1 is restored as quickly after the
chip reset as possible.
S/G structurs must be 8byte aligned. Make this official by saying
so in our DMA tag.
Disable CIO bus stretch on MDFFSTAT if SHVALID is about to come
true. This can cause a CIO bus lockup if a PCI or PCI-X error
occurs while the stretch is occurring - the host cannot service
the PCI-X error since the CIO bus is locked out and SHVALID will
never resolve. The stretch was added in the Rev B to simplify the
wait for SHVALID to resolve, but the code to do this in the open
source sequencer is so simple it was never removed.
Consistently use MAX_OFFSET for the user max syncrate set from
non-volatile storage. This ensures that the offset does not
conflict with AH?_OFFSET_UNKNOWN.
Have ahd_pause_and_flushwork set the mode to ensure that it has
access to the registers it checks. Also modify the checking of
intstat so that the check against 0xFF can actually succeed if
the INT_PEND mask is something other than 0xFF. Although there
are no cardbus U320 controllers, this check may be needed to
recover from a hot-plug PCI removal that occurs without informing
the driver.
Fix a typo. sg_prefetch_cnt -> sg_prefetch_align. This fixes
an infinite loop at card initialization if the cacheline size is 0.
aic79xx.h:
Add AHD_EARLY_REQ_BUG bug flag.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
Change AH?_OFFSET_UNKNOWN to 0xFF. This is a value that the
curr->offset can never be, unlike '0' which we previously used.
This fixes code that only checks for a non-zero offset to
determine if a sync negotiation is required since it will fire
in the unknown case even if the goal is async.
aic79xx.reg:
Add comments for LQISTAT bits indicating their names in the 7902
data book. We use slightly different and more descriptive names
in the firmware.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
aic79xx.seq:
Update comments regarding rundown of the GSFIFO to reflect reality.
Fix spelling errors.
Since we use an 8byte address and 1 byte length, shorten the size
of a block move for the legacy DMA'ed CDB case from 11 to 9 bytes.
Remove code that, assuming the abort pending feature worked, would
set MK_MESSAGE in the SCB's control byte on completion to catch
invalid reselections. Since we don't see interrupts for completed
selections, this status update could occur prior to us noticing the
SELDO. The "select-out" queue logic will get confused by the
MK_MESSAGE bit being set as this is used to catch packatized
connections where we select-out with ATN. Since the abort pending
feature doesn't work on any released controllers yet, this code was
never executed.
Add support for the AHD_EARLY_REQ_BUG. Don't ignore persistent REQ
assertions just because they were asserted within the bus settle delay
window. This allows us to tolerate devices like the GEM318 that
violate the SCSI spec.
Remove unintentional settnig of SG_CACHE_AVAIL. Writing this bit
should have no effect, but who knows...
On the Rev A, we must wait for HDMAENACK before loading additional
segments to avoid clobbering the address of the first segment in
the S/G FIFO. This resolves data-corruption issues with certain
IBM (now Hitachi) and Fujitsu U320 drives.
Rearrange calc_residual to avoid an extra jmp instruction.
On RevA Silicon, if the target returns us to data-out after we
have already trained for data-out, it is possible for us to
transition the free running clock to data-valid before the required
100ns P1 setup time (8 P1 assertions in fast-160 mode). This will
only happen if this L-Q is a continuation of a data transfer for
which we have already prefetched data into our FIFO (LQ/Data
followed by LQ/Data for the same write transaction). This can
cause some target implementations to miss the first few data
transfers on the bus. We detect this situation by noticing that
this is the first data transfer after an LQ (LQIWORKONLQ true),
that the data transfer is a continuation of a transfer already
setup in our FIFO (SAVEPTRS interrupt), and that the transaction
is a write (DIRECTION set in DFCNTRL). The delay is performed by
disabling SCSIEN until we see the first REQ from the target.
Only compile in snapshot savepointers handler for RevA silicon
where it is enabled.
Handle the cfg4icmd packetized interrupt. We just need to load
the address and count, start the DMA, and CLRCHN once the transfer
is complete.
Fix an oversight in the overrun handler for packetized status
operations. We need to wait for either CTXTDONE or an overrun
when checking for an overrun. The previous code did not wait
and thus could decide that no overrun had occurred even though
an overrun will occur on the next data-valid req. Add some
comment to this section for clarity.
Use LAST_SEG_DONE instead of LASTSDONE for testing transfer
completion in the packetized status case. LASTSDONE may come up
more quickly since it only records completion on the SCSI side,
but since LAST_SEG_DONE is used everywhere else (and needs to be),
this is less confusing.
Add a missing invalidation of the longjmp address in the non-pack
handler. This code needs additional review.
aic79xx_inline.h:
Fix spelling error.
aic79xx_osm.c:
Set the cdb length for CDBs dma'ed from host memory.
Add a comment indicating that, should CAM start supporting cdbs
larger than 16bytes, the driver could store the CDB in the status
buffer.
aic79xx_pci.c:
Add a table entry for the 39320A.
Added a missing comma to an error string table.
Fix spelling errors.
2003-02-27 23:23:16 +00:00
|
|
|
struct {
|
|
|
|
|
uint64_t cdbptr;
|
|
|
|
|
uint8_t cdblen;
|
|
|
|
|
} cdb_from_host;
|
2002-06-05 19:52:45 +00:00
|
|
|
uint8_t cdb[MAX_CDB_LEN];
|
|
|
|
|
struct {
|
|
|
|
|
uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR];
|
|
|
|
|
sense_addr_t sense_addr;
|
|
|
|
|
} cdb_plus_saddr;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Target mode version of the shared data SCB segment.
|
|
|
|
|
*/
|
|
|
|
|
struct target_data {
|
|
|
|
|
uint32_t spare[2];
|
|
|
|
|
uint8_t scsi_status; /* SCSI status to give to initiator */
|
|
|
|
|
uint8_t target_phases; /* Bitmap of phases to execute */
|
|
|
|
|
uint8_t data_phase; /* Data-In or Data-Out */
|
|
|
|
|
uint8_t initiator_tag; /* Initiator's transaction tag */
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct hardware_scb {
|
|
|
|
|
/*0*/ union {
|
|
|
|
|
union initiator_data idata;
|
|
|
|
|
struct target_data tdata;
|
|
|
|
|
struct initiator_status istatus;
|
|
|
|
|
struct target_status tstatus;
|
|
|
|
|
} shared_data;
|
|
|
|
|
/*
|
|
|
|
|
* A word about residuals.
|
|
|
|
|
* The scb is presented to the sequencer with the dataptr and datacnt
|
|
|
|
|
* fields initialized to the contents of the first S/G element to
|
|
|
|
|
* transfer. The sgptr field is initialized to the bus address for
|
|
|
|
|
* the S/G element that follows the first in the in core S/G array
|
|
|
|
|
* or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid
|
|
|
|
|
* S/G entry for this transfer (single S/G element transfer with the
|
|
|
|
|
* first elements address and length preloaded in the dataptr/datacnt
|
|
|
|
|
* fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL.
|
|
|
|
|
* The SG_FULL_RESID flag ensures that the residual will be correctly
|
|
|
|
|
* noted even if no data transfers occur. Once the data phase is entered,
|
|
|
|
|
* the residual sgptr and datacnt are loaded from the sgptr and the
|
|
|
|
|
* datacnt fields. After each S/G element's dataptr and length are
|
|
|
|
|
* loaded into the hardware, the residual sgptr is advanced. After
|
|
|
|
|
* each S/G element is expired, its datacnt field is checked to see
|
|
|
|
|
* if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the
|
|
|
|
|
* residual sg ptr and the transfer is considered complete. If the
|
|
|
|
|
* sequencer determines that there is a residual in the tranfer, or
|
|
|
|
|
* there is non-zero status, it will set the SG_STATUS_VALID flag in
|
|
|
|
|
* sgptr and dma the scb back into host memory. To sumarize:
|
|
|
|
|
*
|
|
|
|
|
* Sequencer:
|
|
|
|
|
* o A residual has occurred if SG_FULL_RESID is set in sgptr,
|
|
|
|
|
* or residual_sgptr does not have SG_LIST_NULL set.
|
|
|
|
|
*
|
|
|
|
|
* o We are transfering the last segment if residual_datacnt has
|
|
|
|
|
* the SG_LAST_SEG flag set.
|
|
|
|
|
*
|
|
|
|
|
* Host:
|
|
|
|
|
* o A residual can only have occurred if a completed scb has the
|
|
|
|
|
* SG_STATUS_VALID flag set. Inspection of the SCSI status field,
|
|
|
|
|
* the residual_datacnt, and the residual_sgptr field will tell
|
|
|
|
|
* for sure.
|
|
|
|
|
*
|
|
|
|
|
* o residual_sgptr and sgptr refer to the "next" sg entry
|
|
|
|
|
* and so may point beyond the last valid sg entry for the
|
|
|
|
|
* transfer.
|
|
|
|
|
*/
|
|
|
|
|
#define SG_PTR_MASK 0xFFFFFFF8
|
2003-05-30 02:14:22 +00:00
|
|
|
/*16*/ uint16_t tag; /* Reused by Sequencer. */
|
|
|
|
|
/*18*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */
|
|
|
|
|
/*19*/ uint8_t scsiid; /*
|
2002-06-05 19:52:45 +00:00
|
|
|
* Selection out Id
|
|
|
|
|
* Our Id (bits 0-3) Their ID (bits 4-7)
|
|
|
|
|
*/
|
2003-05-30 02:14:22 +00:00
|
|
|
/*20*/ uint8_t lun;
|
|
|
|
|
/*21*/ uint8_t task_attribute;
|
|
|
|
|
/*22*/ uint8_t cdb_len;
|
|
|
|
|
/*23*/ uint8_t task_management;
|
|
|
|
|
/*24*/ uint64_t dataptr;
|
|
|
|
|
/*32*/ uint32_t datacnt; /* Byte 3 is spare. */
|
|
|
|
|
/*36*/ uint32_t sgptr;
|
|
|
|
|
/*40*/ uint32_t hscb_busaddr;
|
|
|
|
|
/*44*/ uint32_t next_hscb_busaddr;
|
Correct spelling errors.
Switch to handling bad SCSI status as a sequencer interrupt
instead of having the kernel proccess these failures via
the completion queue. This is done because:
o The old scheme required us to pause the sequencer and clear
critical sections for each SCB. It seems that these pause
actions, if coincident with a sequencer FIFO interrupt, would
result in a FIFO interrupt getting lost or directing to the
wrong FIFO. This caused hangs when the driver was stressed
under high "queue full" loads.
o The completion code assumed that it was always called with
the sequencer running. This may not be the case in timeout
processing where completions occur manually via
ahd_pause_and_flushwork().
o With this scheme, the extra expense of clearing critical
sections is avoided since the sequencer will only self pause
once all pending selections have cleared and it is not in
a critical section.
aic79xx.c
Add code to handle the new BAD_SCB_STATUS sequencer
interrupt code. This just redirects the SCB through
the already existing ahd_complete_scb() code path.
Remove code in ahd_handle_scsi_status() that paused
the sequencer, made sure that no selections where
pending, and cleared critical sections. Bad
status SCBs are now only processed when all of these
conditions are true.
aic79xx.reg:
Add the BAD_SCB_STATUS sequencer interrupt code.
aic79xx.seq:
When completing an SCB upload to the host, if
we are doing this because the SCB contains non-zero
SCSI status, defer completing the SCB until there
are no pending selection events. When completing
these SCBs, use the new BAD_SCB_STATUS sequencer
interrupt. For all other uploaded SCBs (currently
only for underruns), the SCB is completed via the
normal done queue. Additionally, keep the SCB that
is currently being uploaded on the COMPLETE_DMA_SCB
list until the dma is completed, not just until the
DMA is started. This ensures that the DMA is restarted
properly should the host disable the DMA transfer for
some reason.
In our RevA workaround for Maxtor drives, guard against
the host pausing us while trying to pause I/O until the
first data-valid REQ by clearing the current snapshot
so that we can tell if the transfer has completed prior
to us noticing the REQINIT status.
In cfg4data_intr, shave off an instruction before getting
the data path running by adding an entrypoint to the
overrun handler to also increment the FIFO use count.
In the overrun handler, be sure to clear our LONGJMP
address in both exit paths.
Perform a few sequencer optimizations.
aic79xx.c:
Print the full path from the SCB when a packetized
status overrun occurs.
Remove references to LONGJMP_SCB which is being
removed from firmware usage.
Print the new SCB_FIFO_USE_COUNT field in the
per-SCB section of ahd_dump_card_state(). The
SCB_TAG field is now re-used by the sequencer,
so it no longer makes sense to reference this
field in the kernel driver.
aic79xx.h:
Re-arrange fields in the hardware SCB from largest
size type to smallest. This makes it easier to
move fields without changing field alignment.
The hardware scb tag field is now down near the
"spare" portion of the SCB to facilitate reuse
by the sequencer.
aic79xx.reg:
Remove LONGJMP_ADDR.
Rearrange SCB fields to match aic79xx.h.
Add SCB_FIFO_USE_COUNT as the first byte
of the SCB_TAG field.
aic79xx.seq:
Add a per-SCB "Fifos in use count" field and use
it to determine when it is safe (all data posted)
to deliver status back to the host. The old method
involved polling one or both FIFOs to verify that
the current task did not have pending data. This
makes running down the GSFIFO very cheap, so we
will empty the GSFIFO in one idle loop pass in
all cases.
Use this simplification of the completion process
to prune down the data FIFO teardown sequencer for
packetized transfers. Much more code is now shared
between the data residual and transfer complete cases.
Correct some issues in the packetized status handler.
It used to be possible to CLRCHN our FIFO before status
had fully transferred to the host. We also failed to
handle NONPACKREQ phases that could occur should a CRC
error occur during transmission of the status data packet.
Correct a few big endian issues:
aic79xx.c:
aic79xx_inline.h:
aic79xx_pci.c:
aic79xx_osm.c:
o Always get the SCB's tag via the SCB_GET_TAG acccessor
o Add missing use of byte swapping macros when touching
hscb fields.
o Don't double swap SEEPROM data when it is printed.
Correct a big-endian bug. We cannot assign a
o When assigning a 32bit LE variable to a 64bit LE
variable, we must be explict about how the words
of the 64bit LE variable are initialized. Cast to
(uint32_t*) to do this.
aic79xx.c:
In ahd_clear_critical_section(), hit CRLSCSIINT
after restoring the interrupt masks to avoid what
appears to be a glitch on SCSIINT. Any real SCSIINT
status will be persistent and will immidiately
reset SCSIINT. This clear should only get rid of
spurious SCSIINTs.
This glitch was the cause of the "Unexpected PKT busfree"
status that occurred under high queue full loads
Call ahd_fini_scbdata() after shutdown so that
any ahd_chip_init() routine that might access
SCB data will not access free'd memory.
Reset the bus on an IOERR since the chip doesn't
seem to reset to the new voltage level without
this.
Change offset calculation for scatter gather maps
so that the calculation is correct if an integral
multiple of sg lists does not fit in the allocation
size.
Adjust bus dma tag for data buffers based on 39BIT
addressing flag in our softc.
Use the QFREEZE count to simplify ahd_pause_and_flushworkd().
We can thus rely on the sequencer eventually clearing ENSELO.
In ahd_abort_scbs(), fix a bug that could potentially
corrupt sequencer state. The saved SCB was being
restored in the SCSI mode instead of the saved mode.
It turns out that the SCB did not need to be saved at all
as the scbptr is already restored by all subroutines
called during this function that modify that register.
aic79xx.c:
aic79xx.h:
aic79xx_pci.c:
Add support for parsing the seeprom vital product
data. The VPD data are currently unused.
aic79xx.h:
aic79xx.seq:
aic79xx_pci.c:
Add a firmware workaround to make the LED blink
brighter during packetized operations on the H2A.
aic79xx_inline.h:
The host does not use timer interrupts, so don't
gate our decision on whether or not to unpause
the sequencer on whether or not a timer interrupt
is pending.
2003-05-04 00:20:07 +00:00
|
|
|
/********** Long lun field only downloaded for full 8 byte lun support ********/
|
2002-08-31 06:48:42 +00:00
|
|
|
/*48*/ uint8_t pkt_long_lun[8];
|
2002-06-05 19:52:45 +00:00
|
|
|
/******* Fields below are not Downloaded (Sequencer may use for scratch) ******/
|
2002-08-31 06:48:42 +00:00
|
|
|
/*56*/ uint8_t spare[8];
|
2002-06-05 19:52:45 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/************************ Kernel SCB Definitions ******************************/
|
|
|
|
|
/*
|
|
|
|
|
* Some fields of the SCB are OS dependent. Here we collect the
|
|
|
|
|
* definitions for elements that all OS platforms need to include
|
|
|
|
|
* in there SCB definition.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Definition of a scatter/gather element as transfered to the controller.
|
|
|
|
|
* The aic7xxx chips only support a 24bit length. We use the top byte of
|
|
|
|
|
* the length to store additional address bits and a flag to indicate
|
|
|
|
|
* that a given segment terminates the transfer. This gives us an
|
|
|
|
|
* addressable range of 512GB on machines with 64bit PCI or with chips
|
|
|
|
|
* that can support dual address cycles on 32bit PCI busses.
|
|
|
|
|
*/
|
|
|
|
|
struct ahd_dma_seg {
|
|
|
|
|
uint32_t addr;
|
|
|
|
|
uint32_t len;
|
|
|
|
|
#define AHD_DMA_LAST_SEG 0x80000000
|
|
|
|
|
#define AHD_SG_HIGH_ADDR_MASK 0x7F000000
|
|
|
|
|
#define AHD_SG_LEN_MASK 0x00FFFFFF
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct ahd_dma64_seg {
|
|
|
|
|
uint64_t addr;
|
|
|
|
|
uint32_t len;
|
|
|
|
|
uint32_t pad;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct map_node {
|
|
|
|
|
bus_dmamap_t dmamap;
|
ahc_eisa.c:
ahc_pci.c:
ahd_pci.c:
aic7xxx.c:
aic79xx.c:
aic_osm_lib.c:
aic_osm_lib.h:
Use common OSM routines from aic_osm_lib for bus dma operations,
delay routines, accessing CCBs, byte swapping, etc.
aic7xxx_pci.c:
Provide a better description for the 2915/30LP on attach.
aic7xxx.c:
aic79xx.c:
aic7770.c:
aic79xx_pci.c:
aic7xxx_pci.c:
aic7xxx_93cx6.c:
Move FBSDID behind an ifdef so that these core files will
still compile under other OSes.
aic79xx.h:
aic79xx_pci.c:
aic79xx.seq:
To speed up non-packetized CDB delivery in Rev B, all CDB
acks are "released" to the output sync as soon as the
command phase starts. There is only one problem with this
approach. If the target changes phase before all data are
sent, we have left over acks that can go out on the bus in
a data phase. Due to other chip contraints, this only
happens if the target goes to data-in, but if the acks go
out before we can test SDONE, we'll think that the transfer
has completed successfully. Work around this by taking
advantage of the 400ns or 800ns dead time between command
phase and the REQ of the new phase. If the transfer has
completed successfully, SCSIEN should fall *long* before we
see a phase change. We thus treat any phasemiss that
occurs before SCSIEN falls as an incomplete transfer.
aic79xx.h:
Add the AHD_FAST_CDB_DELIVERY feature.
aic79xx_pci.c:
Set AHD_FAST_CDB_DELIVERY for all Rev. B parts.
aic79xx.seq:
Test for PHASEMIS in the command phase for
all AHD_FAST_CDB_DELIVERY controlelrs.
ahd_pci.c:
ahc_pci.c:
aic7xxx.h:
aic79xx.h:
Move definition of controller BAR offsets to core header files.
aic7xxx.c:
aic79xx.c:
In the softc free routine, leave removal of a softc from the
global list of softcs to the OSM (the caller of this routine).
This allows us to avoid holding the softc list_lock during device
destruction where we may have to sleep waiting for our recovery
thread to halt.
ahc_pci.c:
Use ahc_pci_test_register access to validate I/O mapped in
addition to the tests already performed for memory mapped
access.
Remove unused ahc_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
ahd_pci.c:
Remove reduntant definition of controller BAR offsets. These
are also defined in aic79xx.h.
Remove unused ahd_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
aic7xxx.c:
aic79xx.c:
aic79xx.h:
aic7xxx.h:
aic7xxx_osm.c:
aic79xx_osm.c:
Move timeout handling to the driver cores. In the case
of the aic79xx driver, the algorithm has been enhanced
to try target resets before performing a bus reset. For
the aic7xxx driver, the algorithm is unchanged. Although
the drivers do not currently sleep during recovery (recovery
is timeout driven), the cores do expect all processing to
be performed via a recovery thread. Our timeout handlers
are now little stubs that wakeup the recovery thread.
aic79xx.c:
aic79xx.h:
aic79xx_inline.h:
Change shared_data allocation to use a map_node so
that the sentinel hscb can use this map node in
ahd_swap_with_next_hscb. This routine now swaps
the hscb_map pointer in additon to the hscb
contents so that any sync operations occur on
the correct map.
physaddr -> busaddr
Pointed out by: Jason Thorpe <thorpej@wasabisystems.com>
aic79xx.c:
Make more use of the in/out/w/l/q macros for accessing
byte registers in the chip.
Correct some issues in the ahd_flush_qoutfifo() routine.
o Run the qoutfifo only once the command channel
DMA engine has been halted. This closes a window
where we might have missed some entries.
o Change ahd_run_data_fifo() to not loop to completion.
If we happen to start on the wrong FIFO and the other
FIFO has a snapshot savepointers, we might deadlock.
This required our delay between FIFO tests to be
moved to the ahd_flush_qoutfifo() routine.
o Update/add comments.
o Remove spurious test for COMPLETE_DMA list being empty
when completing transactions from the GSFIFO with
residuals. The SCB must be put on the COMPLETE_DMA
scb list unconditionally.
o When halting command channel DMA activity, we must
disable the DMA channel in all cases but an update
of the QOUTFIFO. The latter case is required so
that the sequencer will update its position in the
QOUTFIFO. Previously, we left the channel enabled
for all "push" DMAs. This left us vulnerable to
the sequencer handling an SCB push long after that
SCB was already processed manually by this routine.
o Correct the polarity of tests involving
ahd_scb_active_in_fifo(). This routine returns
non-zero for true.
Return to processing bad status completions through
the qoutfifo. This reduces the time that the sequencer
is kept paused when handling transactions with bad
status or underruns.
When waiting for the controller to quiece selections,
add a delay to our loop. Otherwise we may fail to wait
long enough for the sequencer to comply.
On H2A4 hardware, use the slow slewrate for non-paced
transfers. This mirrors what the Adaptec Windows
drivers do.
On the Rev B. only slow down the CRC timing for
older U160 devices that might need the slower timing.
We define "older" as devices that do not support
packetized protocol.
Wait up to 5000 * 5us for the SEEPROM to become unbusy.
Write ops seem to take much longer than read ops.
aic79xx.seq:
For controllers with the FAINT_LED bug, turn the diagnostic
led feature on during selection and reselection. This covers
the non-packetized case. The LED will be disabled for
non-packetized transfers once we return to the top level idle
loop. Add more comments about the busy LED workaround.
Extend a critical section around the entire
command channel idle loop process. Previously
the portion of this handler that directly manipulated
the linked list of completed SCBs was not protected.
This is the likely cause of the recent reports of
commands being completed twice by the driver.
Extend critical sections across the test for,
and the longjump to, longjump routines. This
prevents the firmware from trying to jump to
a longjmp handler that was just cleared by the
host.
Improve the locations of several critical section
begin and end points. Typically these changes
remove instructions that did not need to be
inside a critical section.
Close the "busfree after selection, but before busfree
interrupts can be enabled" race to just a single sequencer
instruction. We now test the BSY line explicitly before
clearing the busfree status and enabling the busfree
interrupt.
Close a race condition in the processing of HS_MAILBOX
updates. We now clear the "updated" status before the
copy. This ensures that we don't accidentally clear
the status incorrectly when the host sneaks in an update
just after our last copy, but before we clear the status.
This race has never been observed.
Don't re-enable SCSIEN if we lose the race to disable SCSIEN
in our interrupt handler's workaround for the RevA data-valid
too early issue.
aic79xx_inline.h:
Add comments indicating that the order in which bytes are
read or written in ahd_inw and ahd_outw is important. This
allows us to use these inlines when accessing registers with
side-effects.
aic79xx_pci.c:
The 29320 and the 29320B are 7902 not 7901 based products.
Correct the driver banner.
aic7xxx.h:
Enable the use of the auto-access pause feature
on the aic7870 and aic7880. It was disabled due
to an oversight.
aic7xxx.reg:
Move TARG_IMMEDIATE_SCB to alias LAST_MSG to
avoid leaving garbage in MWI_RESIDUAL. This
prevents spurious overflows whn operating target
mode on controllers that require the MWI_RESIDUAL
work-around.
aic7xxx.seq:
AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag.
Reference the correct softc field when testing
for its presence.
Set the NOT_IDENTIFIED and NO_CDB_SENT bits
in SEQ_FLAGS to indicate that the nexus is
invalid in await busfree.
aic7xxx_93cx6.c:
Add support for the C56/C66 versions of the EWEN and EWDS
commands.
aic7xxx.c:
aic7xxx_pci.c:
Move test for the validity of left over BIOS data
to ahc_test_register_access(). This guarantees that
any left over CHIPRST value is not clobbered by our
register access test and lost to the test that was
in ahc_reset.
2003-12-17 00:02:10 +00:00
|
|
|
bus_addr_t busaddr;
|
2002-06-05 19:52:45 +00:00
|
|
|
uint8_t *vaddr;
|
|
|
|
|
SLIST_ENTRY(map_node) links;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The current state of this SCB.
|
|
|
|
|
*/
|
|
|
|
|
typedef enum {
|
2002-08-31 06:48:42 +00:00
|
|
|
SCB_FLAG_NONE = 0x00000,
|
|
|
|
|
SCB_TRANSMISSION_ERROR = 0x00001,/*
|
|
|
|
|
* We detected a parity or CRC
|
|
|
|
|
* error that has effected the
|
|
|
|
|
* payload of the command. This
|
|
|
|
|
* flag is checked when normal
|
|
|
|
|
* status is returned to catch
|
|
|
|
|
* the case of a target not
|
|
|
|
|
* responding to our attempt
|
|
|
|
|
* to report the error.
|
|
|
|
|
*/
|
|
|
|
|
SCB_OTHERTCL_TIMEOUT = 0x00002,/*
|
|
|
|
|
* Another device was active
|
|
|
|
|
* during the first timeout for
|
|
|
|
|
* this SCB so we gave ourselves
|
|
|
|
|
* an additional timeout period
|
|
|
|
|
* in case it was hogging the
|
|
|
|
|
* bus.
|
|
|
|
|
*/
|
|
|
|
|
SCB_DEVICE_RESET = 0x00004,
|
|
|
|
|
SCB_SENSE = 0x00008,
|
|
|
|
|
SCB_CDB32_PTR = 0x00010,
|
|
|
|
|
SCB_RECOVERY_SCB = 0x00020,
|
|
|
|
|
SCB_AUTO_NEGOTIATE = 0x00040,/* Negotiate to achieve goal. */
|
|
|
|
|
SCB_NEGOTIATE = 0x00080,/* Negotiation forced for command. */
|
|
|
|
|
SCB_ABORT = 0x00100,
|
2002-12-01 08:13:37 +00:00
|
|
|
SCB_ACTIVE = 0x00200,
|
|
|
|
|
SCB_TARGET_IMMEDIATE = 0x00400,
|
|
|
|
|
SCB_PACKETIZED = 0x00800,
|
|
|
|
|
SCB_EXPECT_PPR_BUSFREE = 0x01000,
|
|
|
|
|
SCB_PKT_SENSE = 0x02000,
|
|
|
|
|
SCB_CMDPHASE_ABORT = 0x04000,
|
aic79xx.c:
Implement the SCB_SILENT flag. This is useful for
hushing up the driver during DV or other operations
that we expect to cause transmission errors. The
messages will still print if the SHOW_MASKED_ERRORS
debug option is enabled.
Save and restore the NEGOADDR address when setting
new transfer settings. The sequencer performs lookups
in the negotiation table too and it expects NEGOADDR
to remain consistent across pause/unpause sessions.
Consistently use "offset" instead of "period" to determine
if we are running sync or not.
Add a SHOW_MESSAGES diagnostic for when we assert ATN
during message processing.
Print out IU, QAS, and RTI features when showing transfer options.
Limit the syncrate after all option conformance
changes have taken place in ahd_devlimited_syncrate.
Changes in options may change the final syncrate we
accept.
Keep a copy of the hs_mailbox in our softc so that
we can perform read/modify/write operations on the
hs_mailbox without having to pause the sequencer to
read the last written value. Use the ENINT_COALESS
flag in the hs_mailbox to toggle interrupt coalessing.
Add entrypoints for enabling interrupt coalessing and
setting both a timeout (how long to wait for commands
to be coalessed) and a maximum commands to coaless value.
Add a statistics timer that decides when to enable or
disable interrupt coalessing based on load.
Add a routine, ahd_reset_cmds_pending() which is used
to update the CMDS_PENDING sequencer variable whenever
error recovery compeltes SCBs without notifying the
sequencer. Since ahd_reset_cmds_pending is called
during ahd_unpause() only if we've aborted SCBs, its
call to ahd_flush_qoutfifo should not cause recursion
through ahd_run_qoutfifo(). A panic has been added to
ensure that this recursion does not occur.
In ahd_search_qinfifo, update the CMDS_PENDING sequencer
variable directly. ahd_search_qinififo can be called
in situations where using ahd_reset_cmds_pending() might
cause recursion. Since we can safely determine the
exact number to reduce CMDS_PENDING by in this scenario
without running the qoutfifo, the manual update is sufficient.
Clean up diagnostics.
Add ahd_flush_qoutfifo() which will run the qoutfifo
as well as complete any commands sitting on the
sequencer's COMPLETE_SCB lists or the good status FIFO.
Use this routine in several places that did similar
things in an add-hoc, but incomplete, fashion. A call
to this routine was also added to ahd_abort_scbs() to
close a race.
In ahd_pause_and_flushwork() only return once selections
are safely disabled. Flush all completed commands via
ahd_flush_qoutfifo().
Remove "Now packetized" diagnostic now that this
information is incorperated into the actual negotiation
messages that are displayed.
When forcing renegotiation, don't clober the current
ppr_options. Much of the driver uses this information
to determine if we are currently packetized or not.
Remove some stray spaces at column 1 in ahd_set_tags.
When complaining about getting a host message loop
request with no pending messages, print out the
SCB_CONTROL register down on the card.
Modify the ahd_sent_msg() routine to handle a search
for an outgoing identify message. Use this to detect
a msg reject on an identify message which typically
indicates that the target thought we were packetized.
Force a renegotiation in this case.
In ahd_search_qinfifo(), wait more effectively for SCB
DMA activities to cease. We also disable SCB fetch
operations since we are about to change the qinfifo
and any fetch in progress will likely be invalidated.
In ahd_qinfifo_count(), fix the qinfifo empty case.
In ahd_dump_card_state(), print out CCSCBCTL in the
correct mode.
If we are a narrow controller, don't set the current
width to unknown when forcing a future negotiation.
This just confuses the code into attempting a wide
negotiation on a narrow bus.
Add support for task management function completions.
Modify ahd_handle_devreset so that it can handle
lun resets in addition to target resets. Use
ahd_handle_devreset for lun and target reset task
management functions.
Handle the abort task TMF race case better. We now
wait until any current selections are over and then
set the TMF back to zero. This should cause the sequencer
to ignore the abort TMF completion should it occur.
Correct a bug in the illegal phase handler that
caused us to drop down to narrow when handling the
unexpected command phase case after 3rd party
reset of a packetized device.
Indicate the features, bugs, and flags set in the softc
that are used to control firmware patch download when
booting verbose.
aic79xx.h:
Add coalessing and HS_MAILBOX fields.
Add per-softc variables for the stats "daemon".
Add a debug option for interrupt coalessing activities.
Add two new softc flags:
o AHD_UPDATE_PEND_CMDS
Run ahd_reset_cmds_pending() on the next unpause.
o AHD_RUNNING_QOUTFIFO
Used to catch recursion through ahd_run_qoutfifo().
aic79xx.reg:
Correct register addresses related to the software timer
and the DFDBCTL register.
Add constants paramaterizing the software timer.
Add scratch ram locations for storing interrupt coalessing
tunables.
Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2.
In at least the REV A, these are writable bits. We make
use of that for a swtimer workaround in the sequencer.
Since HS_MAILBOX autoclears, provide a sequencer variable
to store its contents.
Add SEQINT codes for handling task management completions.
aic79xx.seq:
Correct ignore wide residue processing check for
a wide negotiation being in effect. We must be
in the SCSI register window in order to access the
negotiation table.
Use the software timer and a commands completed count to
implement interrupt coalessing. The command complete is
deferred until either the maximum command threshold or a
the expiration of a command deferral timer. If we have
more SCBs to complete to the host (sitting in COMPLETE_SCB
lists), always try to coaless them up to our coalessing limit.
If coalessing is enabled, but we have fewer commands oustanting
than the host's min coalessing limit, complete the command
immediately.
Add code to track the number of commands outstanding.
Commands are outstanding from the time they are placed
into the execution queue until the DMA to post completion
is setup.
Add a workaround for intvec_2 interrupts on the H2A4.
In H2A4, the mode pointer is not saved for intvec2, but
is restored on iret. This can lead to the restoration
of a bogus mode ptr. Manually clear the intmask bits and
do a normal return to compensate. We use intvec_2 to
track interrupt coalessing timeouts.
Since we cannot disable the swtimer's countdown, simply
mask its interrupt once we no longer care about it firing.
In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime
we are notified of an HS_MAILBOX update via the
HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a
local copy of persistant portions of the HS_MAILBOX as
the mailbox auto-clears on any read.
Move the test for the cfg4istat interrupt up an instruction
to hopefully close a race between the next outgoing selection
and our disabling of selections.
Add a missing ret to the last instruction in load_overrun_buf.
Add notifications to the host of task management
completions as well as the completions for commands
that completed successfully before their corresponding
TMF could be sent.
Hold a critical section during select-out processing
until we have a fully identified connection. This
removes a race condition with the legacy abort handler.
Correct a few spelling errors in some comments.
aic79xx_inline.h:
Call ahd_reset_cmds_pending() in ahd_unpause if required.
Update cmdcmplt interrupt statistics in our interrupt
handler.
Allow callers to ahd_send_scb() to set the task management
function.
aic79xx_pci.c:
Disable SERR and pause the controller prior to performing
our mmapped I/O test. The U320 controllers do not support
"auto-access-pause".
aic79xx_osm.c:
Set the task management function now that
ahd_send_scb() doesn't do it for us. We
also perform a lun reset in response to BDR
requests to packetized devices.
2003-01-20 20:17:35 +00:00
|
|
|
SCB_ON_COL_LIST = 0x08000,
|
ahc_eisa.c:
ahc_pci.c:
ahd_pci.c:
aic7xxx.c:
aic79xx.c:
aic_osm_lib.c:
aic_osm_lib.h:
Use common OSM routines from aic_osm_lib for bus dma operations,
delay routines, accessing CCBs, byte swapping, etc.
aic7xxx_pci.c:
Provide a better description for the 2915/30LP on attach.
aic7xxx.c:
aic79xx.c:
aic7770.c:
aic79xx_pci.c:
aic7xxx_pci.c:
aic7xxx_93cx6.c:
Move FBSDID behind an ifdef so that these core files will
still compile under other OSes.
aic79xx.h:
aic79xx_pci.c:
aic79xx.seq:
To speed up non-packetized CDB delivery in Rev B, all CDB
acks are "released" to the output sync as soon as the
command phase starts. There is only one problem with this
approach. If the target changes phase before all data are
sent, we have left over acks that can go out on the bus in
a data phase. Due to other chip contraints, this only
happens if the target goes to data-in, but if the acks go
out before we can test SDONE, we'll think that the transfer
has completed successfully. Work around this by taking
advantage of the 400ns or 800ns dead time between command
phase and the REQ of the new phase. If the transfer has
completed successfully, SCSIEN should fall *long* before we
see a phase change. We thus treat any phasemiss that
occurs before SCSIEN falls as an incomplete transfer.
aic79xx.h:
Add the AHD_FAST_CDB_DELIVERY feature.
aic79xx_pci.c:
Set AHD_FAST_CDB_DELIVERY for all Rev. B parts.
aic79xx.seq:
Test for PHASEMIS in the command phase for
all AHD_FAST_CDB_DELIVERY controlelrs.
ahd_pci.c:
ahc_pci.c:
aic7xxx.h:
aic79xx.h:
Move definition of controller BAR offsets to core header files.
aic7xxx.c:
aic79xx.c:
In the softc free routine, leave removal of a softc from the
global list of softcs to the OSM (the caller of this routine).
This allows us to avoid holding the softc list_lock during device
destruction where we may have to sleep waiting for our recovery
thread to halt.
ahc_pci.c:
Use ahc_pci_test_register access to validate I/O mapped in
addition to the tests already performed for memory mapped
access.
Remove unused ahc_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
ahd_pci.c:
Remove reduntant definition of controller BAR offsets. These
are also defined in aic79xx.h.
Remove unused ahd_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
aic7xxx.c:
aic79xx.c:
aic79xx.h:
aic7xxx.h:
aic7xxx_osm.c:
aic79xx_osm.c:
Move timeout handling to the driver cores. In the case
of the aic79xx driver, the algorithm has been enhanced
to try target resets before performing a bus reset. For
the aic7xxx driver, the algorithm is unchanged. Although
the drivers do not currently sleep during recovery (recovery
is timeout driven), the cores do expect all processing to
be performed via a recovery thread. Our timeout handlers
are now little stubs that wakeup the recovery thread.
aic79xx.c:
aic79xx.h:
aic79xx_inline.h:
Change shared_data allocation to use a map_node so
that the sentinel hscb can use this map node in
ahd_swap_with_next_hscb. This routine now swaps
the hscb_map pointer in additon to the hscb
contents so that any sync operations occur on
the correct map.
physaddr -> busaddr
Pointed out by: Jason Thorpe <thorpej@wasabisystems.com>
aic79xx.c:
Make more use of the in/out/w/l/q macros for accessing
byte registers in the chip.
Correct some issues in the ahd_flush_qoutfifo() routine.
o Run the qoutfifo only once the command channel
DMA engine has been halted. This closes a window
where we might have missed some entries.
o Change ahd_run_data_fifo() to not loop to completion.
If we happen to start on the wrong FIFO and the other
FIFO has a snapshot savepointers, we might deadlock.
This required our delay between FIFO tests to be
moved to the ahd_flush_qoutfifo() routine.
o Update/add comments.
o Remove spurious test for COMPLETE_DMA list being empty
when completing transactions from the GSFIFO with
residuals. The SCB must be put on the COMPLETE_DMA
scb list unconditionally.
o When halting command channel DMA activity, we must
disable the DMA channel in all cases but an update
of the QOUTFIFO. The latter case is required so
that the sequencer will update its position in the
QOUTFIFO. Previously, we left the channel enabled
for all "push" DMAs. This left us vulnerable to
the sequencer handling an SCB push long after that
SCB was already processed manually by this routine.
o Correct the polarity of tests involving
ahd_scb_active_in_fifo(). This routine returns
non-zero for true.
Return to processing bad status completions through
the qoutfifo. This reduces the time that the sequencer
is kept paused when handling transactions with bad
status or underruns.
When waiting for the controller to quiece selections,
add a delay to our loop. Otherwise we may fail to wait
long enough for the sequencer to comply.
On H2A4 hardware, use the slow slewrate for non-paced
transfers. This mirrors what the Adaptec Windows
drivers do.
On the Rev B. only slow down the CRC timing for
older U160 devices that might need the slower timing.
We define "older" as devices that do not support
packetized protocol.
Wait up to 5000 * 5us for the SEEPROM to become unbusy.
Write ops seem to take much longer than read ops.
aic79xx.seq:
For controllers with the FAINT_LED bug, turn the diagnostic
led feature on during selection and reselection. This covers
the non-packetized case. The LED will be disabled for
non-packetized transfers once we return to the top level idle
loop. Add more comments about the busy LED workaround.
Extend a critical section around the entire
command channel idle loop process. Previously
the portion of this handler that directly manipulated
the linked list of completed SCBs was not protected.
This is the likely cause of the recent reports of
commands being completed twice by the driver.
Extend critical sections across the test for,
and the longjump to, longjump routines. This
prevents the firmware from trying to jump to
a longjmp handler that was just cleared by the
host.
Improve the locations of several critical section
begin and end points. Typically these changes
remove instructions that did not need to be
inside a critical section.
Close the "busfree after selection, but before busfree
interrupts can be enabled" race to just a single sequencer
instruction. We now test the BSY line explicitly before
clearing the busfree status and enabling the busfree
interrupt.
Close a race condition in the processing of HS_MAILBOX
updates. We now clear the "updated" status before the
copy. This ensures that we don't accidentally clear
the status incorrectly when the host sneaks in an update
just after our last copy, but before we clear the status.
This race has never been observed.
Don't re-enable SCSIEN if we lose the race to disable SCSIEN
in our interrupt handler's workaround for the RevA data-valid
too early issue.
aic79xx_inline.h:
Add comments indicating that the order in which bytes are
read or written in ahd_inw and ahd_outw is important. This
allows us to use these inlines when accessing registers with
side-effects.
aic79xx_pci.c:
The 29320 and the 29320B are 7902 not 7901 based products.
Correct the driver banner.
aic7xxx.h:
Enable the use of the auto-access pause feature
on the aic7870 and aic7880. It was disabled due
to an oversight.
aic7xxx.reg:
Move TARG_IMMEDIATE_SCB to alias LAST_MSG to
avoid leaving garbage in MWI_RESIDUAL. This
prevents spurious overflows whn operating target
mode on controllers that require the MWI_RESIDUAL
work-around.
aic7xxx.seq:
AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag.
Reference the correct softc field when testing
for its presence.
Set the NOT_IDENTIFIED and NO_CDB_SENT bits
in SEQ_FLAGS to indicate that the nexus is
invalid in await busfree.
aic7xxx_93cx6.c:
Add support for the C56/C66 versions of the EWEN and EWDS
commands.
aic7xxx.c:
aic7xxx_pci.c:
Move test for the validity of left over BIOS data
to ahc_test_register_access(). This guarantees that
any left over CHIPRST value is not clobbered by our
register access test and lost to the test that was
in ahc_reset.
2003-12-17 00:02:10 +00:00
|
|
|
SCB_SILENT = 0x10000,/*
|
aic79xx.c:
Implement the SCB_SILENT flag. This is useful for
hushing up the driver during DV or other operations
that we expect to cause transmission errors. The
messages will still print if the SHOW_MASKED_ERRORS
debug option is enabled.
Save and restore the NEGOADDR address when setting
new transfer settings. The sequencer performs lookups
in the negotiation table too and it expects NEGOADDR
to remain consistent across pause/unpause sessions.
Consistently use "offset" instead of "period" to determine
if we are running sync or not.
Add a SHOW_MESSAGES diagnostic for when we assert ATN
during message processing.
Print out IU, QAS, and RTI features when showing transfer options.
Limit the syncrate after all option conformance
changes have taken place in ahd_devlimited_syncrate.
Changes in options may change the final syncrate we
accept.
Keep a copy of the hs_mailbox in our softc so that
we can perform read/modify/write operations on the
hs_mailbox without having to pause the sequencer to
read the last written value. Use the ENINT_COALESS
flag in the hs_mailbox to toggle interrupt coalessing.
Add entrypoints for enabling interrupt coalessing and
setting both a timeout (how long to wait for commands
to be coalessed) and a maximum commands to coaless value.
Add a statistics timer that decides when to enable or
disable interrupt coalessing based on load.
Add a routine, ahd_reset_cmds_pending() which is used
to update the CMDS_PENDING sequencer variable whenever
error recovery compeltes SCBs without notifying the
sequencer. Since ahd_reset_cmds_pending is called
during ahd_unpause() only if we've aborted SCBs, its
call to ahd_flush_qoutfifo should not cause recursion
through ahd_run_qoutfifo(). A panic has been added to
ensure that this recursion does not occur.
In ahd_search_qinfifo, update the CMDS_PENDING sequencer
variable directly. ahd_search_qinififo can be called
in situations where using ahd_reset_cmds_pending() might
cause recursion. Since we can safely determine the
exact number to reduce CMDS_PENDING by in this scenario
without running the qoutfifo, the manual update is sufficient.
Clean up diagnostics.
Add ahd_flush_qoutfifo() which will run the qoutfifo
as well as complete any commands sitting on the
sequencer's COMPLETE_SCB lists or the good status FIFO.
Use this routine in several places that did similar
things in an add-hoc, but incomplete, fashion. A call
to this routine was also added to ahd_abort_scbs() to
close a race.
In ahd_pause_and_flushwork() only return once selections
are safely disabled. Flush all completed commands via
ahd_flush_qoutfifo().
Remove "Now packetized" diagnostic now that this
information is incorperated into the actual negotiation
messages that are displayed.
When forcing renegotiation, don't clober the current
ppr_options. Much of the driver uses this information
to determine if we are currently packetized or not.
Remove some stray spaces at column 1 in ahd_set_tags.
When complaining about getting a host message loop
request with no pending messages, print out the
SCB_CONTROL register down on the card.
Modify the ahd_sent_msg() routine to handle a search
for an outgoing identify message. Use this to detect
a msg reject on an identify message which typically
indicates that the target thought we were packetized.
Force a renegotiation in this case.
In ahd_search_qinfifo(), wait more effectively for SCB
DMA activities to cease. We also disable SCB fetch
operations since we are about to change the qinfifo
and any fetch in progress will likely be invalidated.
In ahd_qinfifo_count(), fix the qinfifo empty case.
In ahd_dump_card_state(), print out CCSCBCTL in the
correct mode.
If we are a narrow controller, don't set the current
width to unknown when forcing a future negotiation.
This just confuses the code into attempting a wide
negotiation on a narrow bus.
Add support for task management function completions.
Modify ahd_handle_devreset so that it can handle
lun resets in addition to target resets. Use
ahd_handle_devreset for lun and target reset task
management functions.
Handle the abort task TMF race case better. We now
wait until any current selections are over and then
set the TMF back to zero. This should cause the sequencer
to ignore the abort TMF completion should it occur.
Correct a bug in the illegal phase handler that
caused us to drop down to narrow when handling the
unexpected command phase case after 3rd party
reset of a packetized device.
Indicate the features, bugs, and flags set in the softc
that are used to control firmware patch download when
booting verbose.
aic79xx.h:
Add coalessing and HS_MAILBOX fields.
Add per-softc variables for the stats "daemon".
Add a debug option for interrupt coalessing activities.
Add two new softc flags:
o AHD_UPDATE_PEND_CMDS
Run ahd_reset_cmds_pending() on the next unpause.
o AHD_RUNNING_QOUTFIFO
Used to catch recursion through ahd_run_qoutfifo().
aic79xx.reg:
Correct register addresses related to the software timer
and the DFDBCTL register.
Add constants paramaterizing the software timer.
Add scratch ram locations for storing interrupt coalessing
tunables.
Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2.
In at least the REV A, these are writable bits. We make
use of that for a swtimer workaround in the sequencer.
Since HS_MAILBOX autoclears, provide a sequencer variable
to store its contents.
Add SEQINT codes for handling task management completions.
aic79xx.seq:
Correct ignore wide residue processing check for
a wide negotiation being in effect. We must be
in the SCSI register window in order to access the
negotiation table.
Use the software timer and a commands completed count to
implement interrupt coalessing. The command complete is
deferred until either the maximum command threshold or a
the expiration of a command deferral timer. If we have
more SCBs to complete to the host (sitting in COMPLETE_SCB
lists), always try to coaless them up to our coalessing limit.
If coalessing is enabled, but we have fewer commands oustanting
than the host's min coalessing limit, complete the command
immediately.
Add code to track the number of commands outstanding.
Commands are outstanding from the time they are placed
into the execution queue until the DMA to post completion
is setup.
Add a workaround for intvec_2 interrupts on the H2A4.
In H2A4, the mode pointer is not saved for intvec2, but
is restored on iret. This can lead to the restoration
of a bogus mode ptr. Manually clear the intmask bits and
do a normal return to compensate. We use intvec_2 to
track interrupt coalessing timeouts.
Since we cannot disable the swtimer's countdown, simply
mask its interrupt once we no longer care about it firing.
In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime
we are notified of an HS_MAILBOX update via the
HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a
local copy of persistant portions of the HS_MAILBOX as
the mailbox auto-clears on any read.
Move the test for the cfg4istat interrupt up an instruction
to hopefully close a race between the next outgoing selection
and our disabling of selections.
Add a missing ret to the last instruction in load_overrun_buf.
Add notifications to the host of task management
completions as well as the completions for commands
that completed successfully before their corresponding
TMF could be sent.
Hold a critical section during select-out processing
until we have a fully identified connection. This
removes a race condition with the legacy abort handler.
Correct a few spelling errors in some comments.
aic79xx_inline.h:
Call ahd_reset_cmds_pending() in ahd_unpause if required.
Update cmdcmplt interrupt statistics in our interrupt
handler.
Allow callers to ahd_send_scb() to set the task management
function.
aic79xx_pci.c:
Disable SERR and pause the controller prior to performing
our mmapped I/O test. The U320 controllers do not support
"auto-access-pause".
aic79xx_osm.c:
Set the task management function now that
ahd_send_scb() doesn't do it for us. We
also perform a lun reset in response to BDR
requests to packetized devices.
2003-01-20 20:17:35 +00:00
|
|
|
* Be quiet about transmission type
|
|
|
|
|
* errors. They are expected and we
|
|
|
|
|
* don't want to upset the user. This
|
|
|
|
|
* flag is typically used during DV.
|
|
|
|
|
*/
|
ahc_eisa.c:
ahc_pci.c:
ahd_pci.c:
aic7xxx.c:
aic79xx.c:
aic_osm_lib.c:
aic_osm_lib.h:
Use common OSM routines from aic_osm_lib for bus dma operations,
delay routines, accessing CCBs, byte swapping, etc.
aic7xxx_pci.c:
Provide a better description for the 2915/30LP on attach.
aic7xxx.c:
aic79xx.c:
aic7770.c:
aic79xx_pci.c:
aic7xxx_pci.c:
aic7xxx_93cx6.c:
Move FBSDID behind an ifdef so that these core files will
still compile under other OSes.
aic79xx.h:
aic79xx_pci.c:
aic79xx.seq:
To speed up non-packetized CDB delivery in Rev B, all CDB
acks are "released" to the output sync as soon as the
command phase starts. There is only one problem with this
approach. If the target changes phase before all data are
sent, we have left over acks that can go out on the bus in
a data phase. Due to other chip contraints, this only
happens if the target goes to data-in, but if the acks go
out before we can test SDONE, we'll think that the transfer
has completed successfully. Work around this by taking
advantage of the 400ns or 800ns dead time between command
phase and the REQ of the new phase. If the transfer has
completed successfully, SCSIEN should fall *long* before we
see a phase change. We thus treat any phasemiss that
occurs before SCSIEN falls as an incomplete transfer.
aic79xx.h:
Add the AHD_FAST_CDB_DELIVERY feature.
aic79xx_pci.c:
Set AHD_FAST_CDB_DELIVERY for all Rev. B parts.
aic79xx.seq:
Test for PHASEMIS in the command phase for
all AHD_FAST_CDB_DELIVERY controlelrs.
ahd_pci.c:
ahc_pci.c:
aic7xxx.h:
aic79xx.h:
Move definition of controller BAR offsets to core header files.
aic7xxx.c:
aic79xx.c:
In the softc free routine, leave removal of a softc from the
global list of softcs to the OSM (the caller of this routine).
This allows us to avoid holding the softc list_lock during device
destruction where we may have to sleep waiting for our recovery
thread to halt.
ahc_pci.c:
Use ahc_pci_test_register access to validate I/O mapped in
addition to the tests already performed for memory mapped
access.
Remove unused ahc_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
ahd_pci.c:
Remove reduntant definition of controller BAR offsets. These
are also defined in aic79xx.h.
Remove unused ahd_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
aic7xxx.c:
aic79xx.c:
aic79xx.h:
aic7xxx.h:
aic7xxx_osm.c:
aic79xx_osm.c:
Move timeout handling to the driver cores. In the case
of the aic79xx driver, the algorithm has been enhanced
to try target resets before performing a bus reset. For
the aic7xxx driver, the algorithm is unchanged. Although
the drivers do not currently sleep during recovery (recovery
is timeout driven), the cores do expect all processing to
be performed via a recovery thread. Our timeout handlers
are now little stubs that wakeup the recovery thread.
aic79xx.c:
aic79xx.h:
aic79xx_inline.h:
Change shared_data allocation to use a map_node so
that the sentinel hscb can use this map node in
ahd_swap_with_next_hscb. This routine now swaps
the hscb_map pointer in additon to the hscb
contents so that any sync operations occur on
the correct map.
physaddr -> busaddr
Pointed out by: Jason Thorpe <thorpej@wasabisystems.com>
aic79xx.c:
Make more use of the in/out/w/l/q macros for accessing
byte registers in the chip.
Correct some issues in the ahd_flush_qoutfifo() routine.
o Run the qoutfifo only once the command channel
DMA engine has been halted. This closes a window
where we might have missed some entries.
o Change ahd_run_data_fifo() to not loop to completion.
If we happen to start on the wrong FIFO and the other
FIFO has a snapshot savepointers, we might deadlock.
This required our delay between FIFO tests to be
moved to the ahd_flush_qoutfifo() routine.
o Update/add comments.
o Remove spurious test for COMPLETE_DMA list being empty
when completing transactions from the GSFIFO with
residuals. The SCB must be put on the COMPLETE_DMA
scb list unconditionally.
o When halting command channel DMA activity, we must
disable the DMA channel in all cases but an update
of the QOUTFIFO. The latter case is required so
that the sequencer will update its position in the
QOUTFIFO. Previously, we left the channel enabled
for all "push" DMAs. This left us vulnerable to
the sequencer handling an SCB push long after that
SCB was already processed manually by this routine.
o Correct the polarity of tests involving
ahd_scb_active_in_fifo(). This routine returns
non-zero for true.
Return to processing bad status completions through
the qoutfifo. This reduces the time that the sequencer
is kept paused when handling transactions with bad
status or underruns.
When waiting for the controller to quiece selections,
add a delay to our loop. Otherwise we may fail to wait
long enough for the sequencer to comply.
On H2A4 hardware, use the slow slewrate for non-paced
transfers. This mirrors what the Adaptec Windows
drivers do.
On the Rev B. only slow down the CRC timing for
older U160 devices that might need the slower timing.
We define "older" as devices that do not support
packetized protocol.
Wait up to 5000 * 5us for the SEEPROM to become unbusy.
Write ops seem to take much longer than read ops.
aic79xx.seq:
For controllers with the FAINT_LED bug, turn the diagnostic
led feature on during selection and reselection. This covers
the non-packetized case. The LED will be disabled for
non-packetized transfers once we return to the top level idle
loop. Add more comments about the busy LED workaround.
Extend a critical section around the entire
command channel idle loop process. Previously
the portion of this handler that directly manipulated
the linked list of completed SCBs was not protected.
This is the likely cause of the recent reports of
commands being completed twice by the driver.
Extend critical sections across the test for,
and the longjump to, longjump routines. This
prevents the firmware from trying to jump to
a longjmp handler that was just cleared by the
host.
Improve the locations of several critical section
begin and end points. Typically these changes
remove instructions that did not need to be
inside a critical section.
Close the "busfree after selection, but before busfree
interrupts can be enabled" race to just a single sequencer
instruction. We now test the BSY line explicitly before
clearing the busfree status and enabling the busfree
interrupt.
Close a race condition in the processing of HS_MAILBOX
updates. We now clear the "updated" status before the
copy. This ensures that we don't accidentally clear
the status incorrectly when the host sneaks in an update
just after our last copy, but before we clear the status.
This race has never been observed.
Don't re-enable SCSIEN if we lose the race to disable SCSIEN
in our interrupt handler's workaround for the RevA data-valid
too early issue.
aic79xx_inline.h:
Add comments indicating that the order in which bytes are
read or written in ahd_inw and ahd_outw is important. This
allows us to use these inlines when accessing registers with
side-effects.
aic79xx_pci.c:
The 29320 and the 29320B are 7902 not 7901 based products.
Correct the driver banner.
aic7xxx.h:
Enable the use of the auto-access pause feature
on the aic7870 and aic7880. It was disabled due
to an oversight.
aic7xxx.reg:
Move TARG_IMMEDIATE_SCB to alias LAST_MSG to
avoid leaving garbage in MWI_RESIDUAL. This
prevents spurious overflows whn operating target
mode on controllers that require the MWI_RESIDUAL
work-around.
aic7xxx.seq:
AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag.
Reference the correct softc field when testing
for its presence.
Set the NOT_IDENTIFIED and NO_CDB_SENT bits
in SEQ_FLAGS to indicate that the nexus is
invalid in await busfree.
aic7xxx_93cx6.c:
Add support for the C56/C66 versions of the EWEN and EWDS
commands.
aic7xxx.c:
aic7xxx_pci.c:
Move test for the validity of left over BIOS data
to ahc_test_register_access(). This guarantees that
any left over CHIPRST value is not clobbered by our
register access test and lost to the test that was
in ahc_reset.
2003-12-17 00:02:10 +00:00
|
|
|
SCB_TIMEDOUT = 0x20000/*
|
|
|
|
|
* SCB has timed out and is on the
|
|
|
|
|
* timedout list.
|
|
|
|
|
*/
|
2002-06-05 19:52:45 +00:00
|
|
|
} scb_flag;
|
|
|
|
|
|
|
|
|
|
struct scb {
|
|
|
|
|
struct hardware_scb *hscb;
|
|
|
|
|
union {
|
|
|
|
|
SLIST_ENTRY(scb) sle;
|
2002-08-31 06:48:42 +00:00
|
|
|
LIST_ENTRY(scb) le;
|
2002-06-05 19:52:45 +00:00
|
|
|
TAILQ_ENTRY(scb) tqe;
|
|
|
|
|
} links;
|
2002-08-31 06:48:42 +00:00
|
|
|
union {
|
|
|
|
|
SLIST_ENTRY(scb) sle;
|
|
|
|
|
LIST_ENTRY(scb) le;
|
|
|
|
|
TAILQ_ENTRY(scb) tqe;
|
|
|
|
|
} links2;
|
|
|
|
|
#define pending_links links2.le
|
|
|
|
|
#define collision_links links2.le
|
ahc_eisa.c:
ahc_pci.c:
ahd_pci.c:
aic7xxx.c:
aic79xx.c:
aic_osm_lib.c:
aic_osm_lib.h:
Use common OSM routines from aic_osm_lib for bus dma operations,
delay routines, accessing CCBs, byte swapping, etc.
aic7xxx_pci.c:
Provide a better description for the 2915/30LP on attach.
aic7xxx.c:
aic79xx.c:
aic7770.c:
aic79xx_pci.c:
aic7xxx_pci.c:
aic7xxx_93cx6.c:
Move FBSDID behind an ifdef so that these core files will
still compile under other OSes.
aic79xx.h:
aic79xx_pci.c:
aic79xx.seq:
To speed up non-packetized CDB delivery in Rev B, all CDB
acks are "released" to the output sync as soon as the
command phase starts. There is only one problem with this
approach. If the target changes phase before all data are
sent, we have left over acks that can go out on the bus in
a data phase. Due to other chip contraints, this only
happens if the target goes to data-in, but if the acks go
out before we can test SDONE, we'll think that the transfer
has completed successfully. Work around this by taking
advantage of the 400ns or 800ns dead time between command
phase and the REQ of the new phase. If the transfer has
completed successfully, SCSIEN should fall *long* before we
see a phase change. We thus treat any phasemiss that
occurs before SCSIEN falls as an incomplete transfer.
aic79xx.h:
Add the AHD_FAST_CDB_DELIVERY feature.
aic79xx_pci.c:
Set AHD_FAST_CDB_DELIVERY for all Rev. B parts.
aic79xx.seq:
Test for PHASEMIS in the command phase for
all AHD_FAST_CDB_DELIVERY controlelrs.
ahd_pci.c:
ahc_pci.c:
aic7xxx.h:
aic79xx.h:
Move definition of controller BAR offsets to core header files.
aic7xxx.c:
aic79xx.c:
In the softc free routine, leave removal of a softc from the
global list of softcs to the OSM (the caller of this routine).
This allows us to avoid holding the softc list_lock during device
destruction where we may have to sleep waiting for our recovery
thread to halt.
ahc_pci.c:
Use ahc_pci_test_register access to validate I/O mapped in
addition to the tests already performed for memory mapped
access.
Remove unused ahc_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
ahd_pci.c:
Remove reduntant definition of controller BAR offsets. These
are also defined in aic79xx.h.
Remove unused ahd_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
aic7xxx.c:
aic79xx.c:
aic79xx.h:
aic7xxx.h:
aic7xxx_osm.c:
aic79xx_osm.c:
Move timeout handling to the driver cores. In the case
of the aic79xx driver, the algorithm has been enhanced
to try target resets before performing a bus reset. For
the aic7xxx driver, the algorithm is unchanged. Although
the drivers do not currently sleep during recovery (recovery
is timeout driven), the cores do expect all processing to
be performed via a recovery thread. Our timeout handlers
are now little stubs that wakeup the recovery thread.
aic79xx.c:
aic79xx.h:
aic79xx_inline.h:
Change shared_data allocation to use a map_node so
that the sentinel hscb can use this map node in
ahd_swap_with_next_hscb. This routine now swaps
the hscb_map pointer in additon to the hscb
contents so that any sync operations occur on
the correct map.
physaddr -> busaddr
Pointed out by: Jason Thorpe <thorpej@wasabisystems.com>
aic79xx.c:
Make more use of the in/out/w/l/q macros for accessing
byte registers in the chip.
Correct some issues in the ahd_flush_qoutfifo() routine.
o Run the qoutfifo only once the command channel
DMA engine has been halted. This closes a window
where we might have missed some entries.
o Change ahd_run_data_fifo() to not loop to completion.
If we happen to start on the wrong FIFO and the other
FIFO has a snapshot savepointers, we might deadlock.
This required our delay between FIFO tests to be
moved to the ahd_flush_qoutfifo() routine.
o Update/add comments.
o Remove spurious test for COMPLETE_DMA list being empty
when completing transactions from the GSFIFO with
residuals. The SCB must be put on the COMPLETE_DMA
scb list unconditionally.
o When halting command channel DMA activity, we must
disable the DMA channel in all cases but an update
of the QOUTFIFO. The latter case is required so
that the sequencer will update its position in the
QOUTFIFO. Previously, we left the channel enabled
for all "push" DMAs. This left us vulnerable to
the sequencer handling an SCB push long after that
SCB was already processed manually by this routine.
o Correct the polarity of tests involving
ahd_scb_active_in_fifo(). This routine returns
non-zero for true.
Return to processing bad status completions through
the qoutfifo. This reduces the time that the sequencer
is kept paused when handling transactions with bad
status or underruns.
When waiting for the controller to quiece selections,
add a delay to our loop. Otherwise we may fail to wait
long enough for the sequencer to comply.
On H2A4 hardware, use the slow slewrate for non-paced
transfers. This mirrors what the Adaptec Windows
drivers do.
On the Rev B. only slow down the CRC timing for
older U160 devices that might need the slower timing.
We define "older" as devices that do not support
packetized protocol.
Wait up to 5000 * 5us for the SEEPROM to become unbusy.
Write ops seem to take much longer than read ops.
aic79xx.seq:
For controllers with the FAINT_LED bug, turn the diagnostic
led feature on during selection and reselection. This covers
the non-packetized case. The LED will be disabled for
non-packetized transfers once we return to the top level idle
loop. Add more comments about the busy LED workaround.
Extend a critical section around the entire
command channel idle loop process. Previously
the portion of this handler that directly manipulated
the linked list of completed SCBs was not protected.
This is the likely cause of the recent reports of
commands being completed twice by the driver.
Extend critical sections across the test for,
and the longjump to, longjump routines. This
prevents the firmware from trying to jump to
a longjmp handler that was just cleared by the
host.
Improve the locations of several critical section
begin and end points. Typically these changes
remove instructions that did not need to be
inside a critical section.
Close the "busfree after selection, but before busfree
interrupts can be enabled" race to just a single sequencer
instruction. We now test the BSY line explicitly before
clearing the busfree status and enabling the busfree
interrupt.
Close a race condition in the processing of HS_MAILBOX
updates. We now clear the "updated" status before the
copy. This ensures that we don't accidentally clear
the status incorrectly when the host sneaks in an update
just after our last copy, but before we clear the status.
This race has never been observed.
Don't re-enable SCSIEN if we lose the race to disable SCSIEN
in our interrupt handler's workaround for the RevA data-valid
too early issue.
aic79xx_inline.h:
Add comments indicating that the order in which bytes are
read or written in ahd_inw and ahd_outw is important. This
allows us to use these inlines when accessing registers with
side-effects.
aic79xx_pci.c:
The 29320 and the 29320B are 7902 not 7901 based products.
Correct the driver banner.
aic7xxx.h:
Enable the use of the auto-access pause feature
on the aic7870 and aic7880. It was disabled due
to an oversight.
aic7xxx.reg:
Move TARG_IMMEDIATE_SCB to alias LAST_MSG to
avoid leaving garbage in MWI_RESIDUAL. This
prevents spurious overflows whn operating target
mode on controllers that require the MWI_RESIDUAL
work-around.
aic7xxx.seq:
AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag.
Reference the correct softc field when testing
for its presence.
Set the NOT_IDENTIFIED and NO_CDB_SENT bits
in SEQ_FLAGS to indicate that the nexus is
invalid in await busfree.
aic7xxx_93cx6.c:
Add support for the C56/C66 versions of the EWEN and EWDS
commands.
aic7xxx.c:
aic7xxx_pci.c:
Move test for the validity of left over BIOS data
to ahc_test_register_access(). This guarantees that
any left over CHIPRST value is not clobbered by our
register access test and lost to the test that was
in ahc_reset.
2003-12-17 00:02:10 +00:00
|
|
|
LIST_ENTRY(scb) timedout_links;
|
2002-08-31 06:48:42 +00:00
|
|
|
struct scb *col_scb;
|
ahc_eisa.c:
ahc_pci.c:
ahd_pci.c:
aic7xxx.c:
aic79xx.c:
aic_osm_lib.c:
aic_osm_lib.h:
Use common OSM routines from aic_osm_lib for bus dma operations,
delay routines, accessing CCBs, byte swapping, etc.
aic7xxx_pci.c:
Provide a better description for the 2915/30LP on attach.
aic7xxx.c:
aic79xx.c:
aic7770.c:
aic79xx_pci.c:
aic7xxx_pci.c:
aic7xxx_93cx6.c:
Move FBSDID behind an ifdef so that these core files will
still compile under other OSes.
aic79xx.h:
aic79xx_pci.c:
aic79xx.seq:
To speed up non-packetized CDB delivery in Rev B, all CDB
acks are "released" to the output sync as soon as the
command phase starts. There is only one problem with this
approach. If the target changes phase before all data are
sent, we have left over acks that can go out on the bus in
a data phase. Due to other chip contraints, this only
happens if the target goes to data-in, but if the acks go
out before we can test SDONE, we'll think that the transfer
has completed successfully. Work around this by taking
advantage of the 400ns or 800ns dead time between command
phase and the REQ of the new phase. If the transfer has
completed successfully, SCSIEN should fall *long* before we
see a phase change. We thus treat any phasemiss that
occurs before SCSIEN falls as an incomplete transfer.
aic79xx.h:
Add the AHD_FAST_CDB_DELIVERY feature.
aic79xx_pci.c:
Set AHD_FAST_CDB_DELIVERY for all Rev. B parts.
aic79xx.seq:
Test for PHASEMIS in the command phase for
all AHD_FAST_CDB_DELIVERY controlelrs.
ahd_pci.c:
ahc_pci.c:
aic7xxx.h:
aic79xx.h:
Move definition of controller BAR offsets to core header files.
aic7xxx.c:
aic79xx.c:
In the softc free routine, leave removal of a softc from the
global list of softcs to the OSM (the caller of this routine).
This allows us to avoid holding the softc list_lock during device
destruction where we may have to sleep waiting for our recovery
thread to halt.
ahc_pci.c:
Use ahc_pci_test_register access to validate I/O mapped in
addition to the tests already performed for memory mapped
access.
Remove unused ahc_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
ahd_pci.c:
Remove reduntant definition of controller BAR offsets. These
are also defined in aic79xx.h.
Remove unused ahd_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
aic7xxx.c:
aic79xx.c:
aic79xx.h:
aic7xxx.h:
aic7xxx_osm.c:
aic79xx_osm.c:
Move timeout handling to the driver cores. In the case
of the aic79xx driver, the algorithm has been enhanced
to try target resets before performing a bus reset. For
the aic7xxx driver, the algorithm is unchanged. Although
the drivers do not currently sleep during recovery (recovery
is timeout driven), the cores do expect all processing to
be performed via a recovery thread. Our timeout handlers
are now little stubs that wakeup the recovery thread.
aic79xx.c:
aic79xx.h:
aic79xx_inline.h:
Change shared_data allocation to use a map_node so
that the sentinel hscb can use this map node in
ahd_swap_with_next_hscb. This routine now swaps
the hscb_map pointer in additon to the hscb
contents so that any sync operations occur on
the correct map.
physaddr -> busaddr
Pointed out by: Jason Thorpe <thorpej@wasabisystems.com>
aic79xx.c:
Make more use of the in/out/w/l/q macros for accessing
byte registers in the chip.
Correct some issues in the ahd_flush_qoutfifo() routine.
o Run the qoutfifo only once the command channel
DMA engine has been halted. This closes a window
where we might have missed some entries.
o Change ahd_run_data_fifo() to not loop to completion.
If we happen to start on the wrong FIFO and the other
FIFO has a snapshot savepointers, we might deadlock.
This required our delay between FIFO tests to be
moved to the ahd_flush_qoutfifo() routine.
o Update/add comments.
o Remove spurious test for COMPLETE_DMA list being empty
when completing transactions from the GSFIFO with
residuals. The SCB must be put on the COMPLETE_DMA
scb list unconditionally.
o When halting command channel DMA activity, we must
disable the DMA channel in all cases but an update
of the QOUTFIFO. The latter case is required so
that the sequencer will update its position in the
QOUTFIFO. Previously, we left the channel enabled
for all "push" DMAs. This left us vulnerable to
the sequencer handling an SCB push long after that
SCB was already processed manually by this routine.
o Correct the polarity of tests involving
ahd_scb_active_in_fifo(). This routine returns
non-zero for true.
Return to processing bad status completions through
the qoutfifo. This reduces the time that the sequencer
is kept paused when handling transactions with bad
status or underruns.
When waiting for the controller to quiece selections,
add a delay to our loop. Otherwise we may fail to wait
long enough for the sequencer to comply.
On H2A4 hardware, use the slow slewrate for non-paced
transfers. This mirrors what the Adaptec Windows
drivers do.
On the Rev B. only slow down the CRC timing for
older U160 devices that might need the slower timing.
We define "older" as devices that do not support
packetized protocol.
Wait up to 5000 * 5us for the SEEPROM to become unbusy.
Write ops seem to take much longer than read ops.
aic79xx.seq:
For controllers with the FAINT_LED bug, turn the diagnostic
led feature on during selection and reselection. This covers
the non-packetized case. The LED will be disabled for
non-packetized transfers once we return to the top level idle
loop. Add more comments about the busy LED workaround.
Extend a critical section around the entire
command channel idle loop process. Previously
the portion of this handler that directly manipulated
the linked list of completed SCBs was not protected.
This is the likely cause of the recent reports of
commands being completed twice by the driver.
Extend critical sections across the test for,
and the longjump to, longjump routines. This
prevents the firmware from trying to jump to
a longjmp handler that was just cleared by the
host.
Improve the locations of several critical section
begin and end points. Typically these changes
remove instructions that did not need to be
inside a critical section.
Close the "busfree after selection, but before busfree
interrupts can be enabled" race to just a single sequencer
instruction. We now test the BSY line explicitly before
clearing the busfree status and enabling the busfree
interrupt.
Close a race condition in the processing of HS_MAILBOX
updates. We now clear the "updated" status before the
copy. This ensures that we don't accidentally clear
the status incorrectly when the host sneaks in an update
just after our last copy, but before we clear the status.
This race has never been observed.
Don't re-enable SCSIEN if we lose the race to disable SCSIEN
in our interrupt handler's workaround for the RevA data-valid
too early issue.
aic79xx_inline.h:
Add comments indicating that the order in which bytes are
read or written in ahd_inw and ahd_outw is important. This
allows us to use these inlines when accessing registers with
side-effects.
aic79xx_pci.c:
The 29320 and the 29320B are 7902 not 7901 based products.
Correct the driver banner.
aic7xxx.h:
Enable the use of the auto-access pause feature
on the aic7870 and aic7880. It was disabled due
to an oversight.
aic7xxx.reg:
Move TARG_IMMEDIATE_SCB to alias LAST_MSG to
avoid leaving garbage in MWI_RESIDUAL. This
prevents spurious overflows whn operating target
mode on controllers that require the MWI_RESIDUAL
work-around.
aic7xxx.seq:
AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag.
Reference the correct softc field when testing
for its presence.
Set the NOT_IDENTIFIED and NO_CDB_SENT bits
in SEQ_FLAGS to indicate that the nexus is
invalid in await busfree.
aic7xxx_93cx6.c:
Add support for the C56/C66 versions of the EWEN and EWDS
commands.
aic7xxx.c:
aic7xxx_pci.c:
Move test for the validity of left over BIOS data
to ahc_test_register_access(). This guarantees that
any left over CHIPRST value is not clobbered by our
register access test and lost to the test that was
in ahc_reset.
2003-12-17 00:02:10 +00:00
|
|
|
aic_io_ctx_t io_ctx;
|
2002-06-05 19:52:45 +00:00
|
|
|
struct ahd_softc *ahd_softc;
|
|
|
|
|
scb_flag flags;
|
|
|
|
|
#ifndef __linux__
|
|
|
|
|
bus_dmamap_t dmamap;
|
|
|
|
|
#endif
|
|
|
|
|
struct scb_platform_data *platform_data;
|
|
|
|
|
struct map_node *hscb_map;
|
|
|
|
|
struct map_node *sg_map;
|
|
|
|
|
struct map_node *sense_map;
|
|
|
|
|
void *sg_list;
|
|
|
|
|
uint8_t *sense_data;
|
|
|
|
|
bus_addr_t sg_list_busaddr;
|
|
|
|
|
bus_addr_t sense_busaddr;
|
|
|
|
|
u_int sg_count;/* How full ahd_dma_seg is */
|
2002-12-01 08:13:37 +00:00
|
|
|
#define AHD_MAX_LQ_CRC_ERRORS 5
|
|
|
|
|
u_int crc_retry_count;
|
2002-06-05 19:52:45 +00:00
|
|
|
};
|
|
|
|
|
|
2002-08-31 06:48:42 +00:00
|
|
|
TAILQ_HEAD(scb_tailq, scb);
|
|
|
|
|
LIST_HEAD(scb_list, scb);
|
|
|
|
|
|
2002-06-05 19:52:45 +00:00
|
|
|
struct scb_data {
|
2002-08-31 06:48:42 +00:00
|
|
|
/*
|
|
|
|
|
* TAILQ of lists of free SCBs grouped by device
|
|
|
|
|
* collision domains.
|
|
|
|
|
*/
|
|
|
|
|
struct scb_tailq free_scbs;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Per-device lists of SCBs whose tag ID would collide
|
|
|
|
|
* with an already active tag on the device.
|
|
|
|
|
*/
|
|
|
|
|
struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT];
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* SCBs that will not collide with any active device.
|
|
|
|
|
*/
|
|
|
|
|
struct scb_list any_dev_free_scb_list;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Mapping from tag to SCB.
|
|
|
|
|
*/
|
2002-06-05 19:52:45 +00:00
|
|
|
struct scb *scbindex[AHD_SCB_MAX];
|
2002-08-31 06:48:42 +00:00
|
|
|
|
2002-06-05 19:52:45 +00:00
|
|
|
/*
|
|
|
|
|
* "Bus" addresses of our data structures.
|
|
|
|
|
*/
|
|
|
|
|
bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */
|
|
|
|
|
bus_dma_tag_t sg_dmat; /* dmat for our sg segments */
|
|
|
|
|
bus_dma_tag_t sense_dmat; /* dmat for our sense buffers */
|
|
|
|
|
SLIST_HEAD(, map_node) hscb_maps;
|
|
|
|
|
SLIST_HEAD(, map_node) sg_maps;
|
|
|
|
|
SLIST_HEAD(, map_node) sense_maps;
|
|
|
|
|
int scbs_left; /* unallocated scbs in head map_node */
|
|
|
|
|
int sgs_left; /* unallocated sgs in head map_node */
|
|
|
|
|
int sense_left; /* unallocated sense in head map_node */
|
|
|
|
|
uint16_t numscbs;
|
|
|
|
|
uint16_t maxhscbs; /* Number of SCBs on the card */
|
|
|
|
|
uint8_t init_level; /*
|
|
|
|
|
* How far we've initialized
|
|
|
|
|
* this structure.
|
|
|
|
|
*/
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/************************ Target Mode Definitions *****************************/
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Connection desciptor for select-in requests in target mode.
|
|
|
|
|
*/
|
|
|
|
|
struct target_cmd {
|
|
|
|
|
uint8_t scsiid; /* Our ID and the initiator's ID */
|
|
|
|
|
uint8_t identify; /* Identify message */
|
|
|
|
|
uint8_t bytes[22]; /*
|
|
|
|
|
* Bytes contains any additional message
|
|
|
|
|
* bytes terminated by 0xFF. The remainder
|
|
|
|
|
* is the cdb to execute.
|
|
|
|
|
*/
|
|
|
|
|
uint8_t cmd_valid; /*
|
|
|
|
|
* When a command is complete, the firmware
|
|
|
|
|
* will set cmd_valid to all bits set.
|
|
|
|
|
* After the host has seen the command,
|
|
|
|
|
* the bits are cleared. This allows us
|
|
|
|
|
* to just peek at host memory to determine
|
|
|
|
|
* if more work is complete. cmd_valid is on
|
|
|
|
|
* an 8 byte boundary to simplify setting
|
|
|
|
|
* it on aic7880 hardware which only has
|
|
|
|
|
* limited direct access to the DMA FIFO.
|
|
|
|
|
*/
|
|
|
|
|
uint8_t pad[7];
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Number of events we can buffer up if we run out
|
|
|
|
|
* of immediate notify ccbs.
|
|
|
|
|
*/
|
|
|
|
|
#define AHD_TMODE_EVENT_BUFFER_SIZE 8
|
|
|
|
|
struct ahd_tmode_event {
|
|
|
|
|
uint8_t initiator_id;
|
|
|
|
|
uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */
|
|
|
|
|
#define EVENT_TYPE_BUS_RESET 0xFF
|
|
|
|
|
uint8_t event_arg;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Per enabled lun target mode state.
|
|
|
|
|
* As this state is directly influenced by the host OS'es target mode
|
|
|
|
|
* environment, we let the OS module define it. Forward declare the
|
|
|
|
|
* structure here so we can store arrays of them, etc. in OS neutral
|
|
|
|
|
* data structures.
|
|
|
|
|
*/
|
|
|
|
|
#ifdef AHD_TARGET_MODE
|
|
|
|
|
struct ahd_tmode_lstate {
|
|
|
|
|
struct cam_path *path;
|
|
|
|
|
struct ccb_hdr_slist accept_tios;
|
|
|
|
|
struct ccb_hdr_slist immed_notifies;
|
|
|
|
|
struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE];
|
|
|
|
|
uint8_t event_r_idx;
|
|
|
|
|
uint8_t event_w_idx;
|
|
|
|
|
};
|
|
|
|
|
#else
|
|
|
|
|
struct ahd_tmode_lstate;
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/******************** Transfer Negotiation Datastructures *********************/
|
|
|
|
|
#define AHD_TRANS_CUR 0x01 /* Modify current neogtiation status */
|
|
|
|
|
#define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */
|
|
|
|
|
#define AHD_TRANS_GOAL 0x04 /* Modify negotiation goal */
|
|
|
|
|
#define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */
|
|
|
|
|
#define AHD_PERIOD_10MHz 0x19
|
|
|
|
|
|
2002-12-01 08:13:37 +00:00
|
|
|
#define AHD_WIDTH_UNKNOWN 0xFF
|
|
|
|
|
#define AHD_PERIOD_UNKNOWN 0xFF
|
aic79xx.c:
Clear the LQICRC_NLQ status should it pop up after we have
already handled the SCSIPERR. During some streaming operations
this status can be delayed until the stream ends. Without this
change, the driver would complain about a "Missing case in
ahd_handle_scsiint".
In the LQOBUSFREE handler...
Don't return the LQOMGR back to the idle state until after
we have cleaned up ENSELO and any status related to this
selection. The last thing we need is the LQO manager starting
another select-out before we have updated the execution queue.
It is not clear whether the LQOMGR would, or would not
start a new selection early.
Make sure ENSELO is off prior to clearing SELDO by flushing
device writes.
Move assignment of the next target SCB pointer inside of
an if to make the code clearer. The effect is the same.
Dump card state in both "Unexpected PKT busfree" paths.
In ahd_reset(), set the chip to SCSI mode before reading SXFRCTL1.
That register only exists in the SCSI mode. Also set the mode
explicitly to the SCSI mode after chip reset due to paranoia.
Re-arrange code so that SXFRCTL1 is restored as quickly after the
chip reset as possible.
S/G structurs must be 8byte aligned. Make this official by saying
so in our DMA tag.
Disable CIO bus stretch on MDFFSTAT if SHVALID is about to come
true. This can cause a CIO bus lockup if a PCI or PCI-X error
occurs while the stretch is occurring - the host cannot service
the PCI-X error since the CIO bus is locked out and SHVALID will
never resolve. The stretch was added in the Rev B to simplify the
wait for SHVALID to resolve, but the code to do this in the open
source sequencer is so simple it was never removed.
Consistently use MAX_OFFSET for the user max syncrate set from
non-volatile storage. This ensures that the offset does not
conflict with AH?_OFFSET_UNKNOWN.
Have ahd_pause_and_flushwork set the mode to ensure that it has
access to the registers it checks. Also modify the checking of
intstat so that the check against 0xFF can actually succeed if
the INT_PEND mask is something other than 0xFF. Although there
are no cardbus U320 controllers, this check may be needed to
recover from a hot-plug PCI removal that occurs without informing
the driver.
Fix a typo. sg_prefetch_cnt -> sg_prefetch_align. This fixes
an infinite loop at card initialization if the cacheline size is 0.
aic79xx.h:
Add AHD_EARLY_REQ_BUG bug flag.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
Change AH?_OFFSET_UNKNOWN to 0xFF. This is a value that the
curr->offset can never be, unlike '0' which we previously used.
This fixes code that only checks for a non-zero offset to
determine if a sync negotiation is required since it will fire
in the unknown case even if the goal is async.
aic79xx.reg:
Add comments for LQISTAT bits indicating their names in the 7902
data book. We use slightly different and more descriptive names
in the firmware.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
aic79xx.seq:
Update comments regarding rundown of the GSFIFO to reflect reality.
Fix spelling errors.
Since we use an 8byte address and 1 byte length, shorten the size
of a block move for the legacy DMA'ed CDB case from 11 to 9 bytes.
Remove code that, assuming the abort pending feature worked, would
set MK_MESSAGE in the SCB's control byte on completion to catch
invalid reselections. Since we don't see interrupts for completed
selections, this status update could occur prior to us noticing the
SELDO. The "select-out" queue logic will get confused by the
MK_MESSAGE bit being set as this is used to catch packatized
connections where we select-out with ATN. Since the abort pending
feature doesn't work on any released controllers yet, this code was
never executed.
Add support for the AHD_EARLY_REQ_BUG. Don't ignore persistent REQ
assertions just because they were asserted within the bus settle delay
window. This allows us to tolerate devices like the GEM318 that
violate the SCSI spec.
Remove unintentional settnig of SG_CACHE_AVAIL. Writing this bit
should have no effect, but who knows...
On the Rev A, we must wait for HDMAENACK before loading additional
segments to avoid clobbering the address of the first segment in
the S/G FIFO. This resolves data-corruption issues with certain
IBM (now Hitachi) and Fujitsu U320 drives.
Rearrange calc_residual to avoid an extra jmp instruction.
On RevA Silicon, if the target returns us to data-out after we
have already trained for data-out, it is possible for us to
transition the free running clock to data-valid before the required
100ns P1 setup time (8 P1 assertions in fast-160 mode). This will
only happen if this L-Q is a continuation of a data transfer for
which we have already prefetched data into our FIFO (LQ/Data
followed by LQ/Data for the same write transaction). This can
cause some target implementations to miss the first few data
transfers on the bus. We detect this situation by noticing that
this is the first data transfer after an LQ (LQIWORKONLQ true),
that the data transfer is a continuation of a transfer already
setup in our FIFO (SAVEPTRS interrupt), and that the transaction
is a write (DIRECTION set in DFCNTRL). The delay is performed by
disabling SCSIEN until we see the first REQ from the target.
Only compile in snapshot savepointers handler for RevA silicon
where it is enabled.
Handle the cfg4icmd packetized interrupt. We just need to load
the address and count, start the DMA, and CLRCHN once the transfer
is complete.
Fix an oversight in the overrun handler for packetized status
operations. We need to wait for either CTXTDONE or an overrun
when checking for an overrun. The previous code did not wait
and thus could decide that no overrun had occurred even though
an overrun will occur on the next data-valid req. Add some
comment to this section for clarity.
Use LAST_SEG_DONE instead of LASTSDONE for testing transfer
completion in the packetized status case. LASTSDONE may come up
more quickly since it only records completion on the SCSI side,
but since LAST_SEG_DONE is used everywhere else (and needs to be),
this is less confusing.
Add a missing invalidation of the longjmp address in the non-pack
handler. This code needs additional review.
aic79xx_inline.h:
Fix spelling error.
aic79xx_osm.c:
Set the cdb length for CDBs dma'ed from host memory.
Add a comment indicating that, should CAM start supporting cdbs
larger than 16bytes, the driver could store the CDB in the status
buffer.
aic79xx_pci.c:
Add a table entry for the 39320A.
Added a missing comma to an error string table.
Fix spelling errors.
2003-02-27 23:23:16 +00:00
|
|
|
#define AHD_OFFSET_UNKNOWN 0xFF
|
2002-12-01 08:13:37 +00:00
|
|
|
#define AHD_PPR_OPTS_UNKNOWN 0xFF
|
|
|
|
|
|
2002-06-05 19:52:45 +00:00
|
|
|
/*
|
|
|
|
|
* Transfer Negotiation Information.
|
|
|
|
|
*/
|
|
|
|
|
struct ahd_transinfo {
|
|
|
|
|
uint8_t protocol_version; /* SCSI Revision level */
|
|
|
|
|
uint8_t transport_version; /* SPI Revision level */
|
|
|
|
|
uint8_t width; /* Bus width */
|
|
|
|
|
uint8_t period; /* Sync rate factor */
|
|
|
|
|
uint8_t offset; /* Sync offset */
|
|
|
|
|
uint8_t ppr_options; /* Parallel Protocol Request options */
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Per-initiator current, goal and user transfer negotiation information. */
|
|
|
|
|
struct ahd_initiator_tinfo {
|
|
|
|
|
struct ahd_transinfo curr;
|
|
|
|
|
struct ahd_transinfo goal;
|
|
|
|
|
struct ahd_transinfo user;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Per enabled target ID state.
|
|
|
|
|
* Pointers to lun target state as well as sync/wide negotiation information
|
|
|
|
|
* for each initiator<->target mapping. For the initiator role we pretend
|
|
|
|
|
* that we are the target and the targets are the initiators since the
|
|
|
|
|
* negotiation is the same regardless of role.
|
|
|
|
|
*/
|
|
|
|
|
struct ahd_tmode_tstate {
|
|
|
|
|
struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS];
|
|
|
|
|
struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS];
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Per initiator state bitmasks.
|
|
|
|
|
*/
|
|
|
|
|
uint16_t auto_negotiate;/* Auto Negotiation Required */
|
|
|
|
|
uint16_t discenable; /* Disconnection allowed */
|
|
|
|
|
uint16_t tagenable; /* Tagged Queuing allowed */
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Points of interest along the negotiated transfer scale.
|
|
|
|
|
*/
|
|
|
|
|
#define AHD_SYNCRATE_160 0x8
|
|
|
|
|
#define AHD_SYNCRATE_PACED 0x8
|
|
|
|
|
#define AHD_SYNCRATE_DT 0x9
|
|
|
|
|
#define AHD_SYNCRATE_ULTRA2 0xa
|
|
|
|
|
#define AHD_SYNCRATE_ULTRA 0xc
|
|
|
|
|
#define AHD_SYNCRATE_FAST 0x19
|
|
|
|
|
#define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST
|
|
|
|
|
#define AHD_SYNCRATE_SYNC 0x32
|
|
|
|
|
#define AHD_SYNCRATE_MIN 0x60
|
|
|
|
|
#define AHD_SYNCRATE_ASYNC 0xFF
|
aic79xx.c:
Implement the SCB_SILENT flag. This is useful for
hushing up the driver during DV or other operations
that we expect to cause transmission errors. The
messages will still print if the SHOW_MASKED_ERRORS
debug option is enabled.
Save and restore the NEGOADDR address when setting
new transfer settings. The sequencer performs lookups
in the negotiation table too and it expects NEGOADDR
to remain consistent across pause/unpause sessions.
Consistently use "offset" instead of "period" to determine
if we are running sync or not.
Add a SHOW_MESSAGES diagnostic for when we assert ATN
during message processing.
Print out IU, QAS, and RTI features when showing transfer options.
Limit the syncrate after all option conformance
changes have taken place in ahd_devlimited_syncrate.
Changes in options may change the final syncrate we
accept.
Keep a copy of the hs_mailbox in our softc so that
we can perform read/modify/write operations on the
hs_mailbox without having to pause the sequencer to
read the last written value. Use the ENINT_COALESS
flag in the hs_mailbox to toggle interrupt coalessing.
Add entrypoints for enabling interrupt coalessing and
setting both a timeout (how long to wait for commands
to be coalessed) and a maximum commands to coaless value.
Add a statistics timer that decides when to enable or
disable interrupt coalessing based on load.
Add a routine, ahd_reset_cmds_pending() which is used
to update the CMDS_PENDING sequencer variable whenever
error recovery compeltes SCBs without notifying the
sequencer. Since ahd_reset_cmds_pending is called
during ahd_unpause() only if we've aborted SCBs, its
call to ahd_flush_qoutfifo should not cause recursion
through ahd_run_qoutfifo(). A panic has been added to
ensure that this recursion does not occur.
In ahd_search_qinfifo, update the CMDS_PENDING sequencer
variable directly. ahd_search_qinififo can be called
in situations where using ahd_reset_cmds_pending() might
cause recursion. Since we can safely determine the
exact number to reduce CMDS_PENDING by in this scenario
without running the qoutfifo, the manual update is sufficient.
Clean up diagnostics.
Add ahd_flush_qoutfifo() which will run the qoutfifo
as well as complete any commands sitting on the
sequencer's COMPLETE_SCB lists or the good status FIFO.
Use this routine in several places that did similar
things in an add-hoc, but incomplete, fashion. A call
to this routine was also added to ahd_abort_scbs() to
close a race.
In ahd_pause_and_flushwork() only return once selections
are safely disabled. Flush all completed commands via
ahd_flush_qoutfifo().
Remove "Now packetized" diagnostic now that this
information is incorperated into the actual negotiation
messages that are displayed.
When forcing renegotiation, don't clober the current
ppr_options. Much of the driver uses this information
to determine if we are currently packetized or not.
Remove some stray spaces at column 1 in ahd_set_tags.
When complaining about getting a host message loop
request with no pending messages, print out the
SCB_CONTROL register down on the card.
Modify the ahd_sent_msg() routine to handle a search
for an outgoing identify message. Use this to detect
a msg reject on an identify message which typically
indicates that the target thought we were packetized.
Force a renegotiation in this case.
In ahd_search_qinfifo(), wait more effectively for SCB
DMA activities to cease. We also disable SCB fetch
operations since we are about to change the qinfifo
and any fetch in progress will likely be invalidated.
In ahd_qinfifo_count(), fix the qinfifo empty case.
In ahd_dump_card_state(), print out CCSCBCTL in the
correct mode.
If we are a narrow controller, don't set the current
width to unknown when forcing a future negotiation.
This just confuses the code into attempting a wide
negotiation on a narrow bus.
Add support for task management function completions.
Modify ahd_handle_devreset so that it can handle
lun resets in addition to target resets. Use
ahd_handle_devreset for lun and target reset task
management functions.
Handle the abort task TMF race case better. We now
wait until any current selections are over and then
set the TMF back to zero. This should cause the sequencer
to ignore the abort TMF completion should it occur.
Correct a bug in the illegal phase handler that
caused us to drop down to narrow when handling the
unexpected command phase case after 3rd party
reset of a packetized device.
Indicate the features, bugs, and flags set in the softc
that are used to control firmware patch download when
booting verbose.
aic79xx.h:
Add coalessing and HS_MAILBOX fields.
Add per-softc variables for the stats "daemon".
Add a debug option for interrupt coalessing activities.
Add two new softc flags:
o AHD_UPDATE_PEND_CMDS
Run ahd_reset_cmds_pending() on the next unpause.
o AHD_RUNNING_QOUTFIFO
Used to catch recursion through ahd_run_qoutfifo().
aic79xx.reg:
Correct register addresses related to the software timer
and the DFDBCTL register.
Add constants paramaterizing the software timer.
Add scratch ram locations for storing interrupt coalessing
tunables.
Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2.
In at least the REV A, these are writable bits. We make
use of that for a swtimer workaround in the sequencer.
Since HS_MAILBOX autoclears, provide a sequencer variable
to store its contents.
Add SEQINT codes for handling task management completions.
aic79xx.seq:
Correct ignore wide residue processing check for
a wide negotiation being in effect. We must be
in the SCSI register window in order to access the
negotiation table.
Use the software timer and a commands completed count to
implement interrupt coalessing. The command complete is
deferred until either the maximum command threshold or a
the expiration of a command deferral timer. If we have
more SCBs to complete to the host (sitting in COMPLETE_SCB
lists), always try to coaless them up to our coalessing limit.
If coalessing is enabled, but we have fewer commands oustanting
than the host's min coalessing limit, complete the command
immediately.
Add code to track the number of commands outstanding.
Commands are outstanding from the time they are placed
into the execution queue until the DMA to post completion
is setup.
Add a workaround for intvec_2 interrupts on the H2A4.
In H2A4, the mode pointer is not saved for intvec2, but
is restored on iret. This can lead to the restoration
of a bogus mode ptr. Manually clear the intmask bits and
do a normal return to compensate. We use intvec_2 to
track interrupt coalessing timeouts.
Since we cannot disable the swtimer's countdown, simply
mask its interrupt once we no longer care about it firing.
In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime
we are notified of an HS_MAILBOX update via the
HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a
local copy of persistant portions of the HS_MAILBOX as
the mailbox auto-clears on any read.
Move the test for the cfg4istat interrupt up an instruction
to hopefully close a race between the next outgoing selection
and our disabling of selections.
Add a missing ret to the last instruction in load_overrun_buf.
Add notifications to the host of task management
completions as well as the completions for commands
that completed successfully before their corresponding
TMF could be sent.
Hold a critical section during select-out processing
until we have a fully identified connection. This
removes a race condition with the legacy abort handler.
Correct a few spelling errors in some comments.
aic79xx_inline.h:
Call ahd_reset_cmds_pending() in ahd_unpause if required.
Update cmdcmplt interrupt statistics in our interrupt
handler.
Allow callers to ahd_send_scb() to set the task management
function.
aic79xx_pci.c:
Disable SERR and pause the controller prior to performing
our mmapped I/O test. The U320 controllers do not support
"auto-access-pause".
aic79xx_osm.c:
Set the task management function now that
ahd_send_scb() doesn't do it for us. We
also perform a lun reset in response to BDR
requests to packetized devices.
2003-01-20 20:17:35 +00:00
|
|
|
#define AHD_SYNCRATE_MAX AHD_SYNCRATE_160
|
2002-06-05 19:52:45 +00:00
|
|
|
|
2002-12-01 08:13:37 +00:00
|
|
|
/* Safe and valid period for async negotiations. */
|
|
|
|
|
#define AHD_ASYNC_XFER_PERIOD 0x44
|
|
|
|
|
|
2002-06-05 19:52:45 +00:00
|
|
|
/*
|
|
|
|
|
* In RevA, the synctable uses a 120MHz rate for the period
|
|
|
|
|
* factor 8 and 160MHz for the period factor 7. The 120MHz
|
|
|
|
|
* rate never made it into the official SCSI spec, so we must
|
|
|
|
|
* compensate when setting the negotiation table for Rev A
|
|
|
|
|
* parts.
|
|
|
|
|
*/
|
|
|
|
|
#define AHD_SYNCRATE_REVA_120 0x8
|
|
|
|
|
#define AHD_SYNCRATE_REVA_160 0x7
|
|
|
|
|
|
|
|
|
|
/***************************** Lookup Tables **********************************/
|
|
|
|
|
/*
|
|
|
|
|
* Phase -> name and message out response
|
|
|
|
|
* to parity errors in each phase table.
|
|
|
|
|
*/
|
|
|
|
|
struct ahd_phase_table_entry {
|
|
|
|
|
uint8_t phase;
|
|
|
|
|
uint8_t mesg_out; /* Message response to parity errors */
|
|
|
|
|
char *phasemsg;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/************************** Serial EEPROM Format ******************************/
|
|
|
|
|
|
|
|
|
|
struct seeprom_config {
|
|
|
|
|
/*
|
|
|
|
|
* Per SCSI ID Configuration Flags
|
|
|
|
|
*/
|
|
|
|
|
uint16_t device_flags[16]; /* words 0-15 */
|
|
|
|
|
#define CFXFER 0x003F /* synchronous transfer rate */
|
|
|
|
|
#define CFXFER_ASYNC 0x3F
|
|
|
|
|
#define CFQAS 0x0040 /* Negotiate QAS */
|
|
|
|
|
#define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */
|
|
|
|
|
#define CFSTART 0x0100 /* send start unit SCSI command */
|
|
|
|
|
#define CFINCBIOS 0x0200 /* include in BIOS scan */
|
|
|
|
|
#define CFDISC 0x0400 /* enable disconnection */
|
|
|
|
|
#define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */
|
|
|
|
|
#define CFWIDEB 0x1000 /* wide bus device */
|
|
|
|
|
#define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* BIOS Control Bits
|
|
|
|
|
*/
|
|
|
|
|
uint16_t bios_control; /* word 16 */
|
|
|
|
|
#define CFSUPREM 0x0001 /* support all removeable drives */
|
|
|
|
|
#define CFSUPREMB 0x0002 /* support removeable boot drives */
|
|
|
|
|
#define CFBIOSSTATE 0x000C /* BIOS Action State */
|
|
|
|
|
#define CFBS_DISABLED 0x00
|
|
|
|
|
#define CFBS_ENABLED 0x04
|
|
|
|
|
#define CFBS_DISABLED_SCAN 0x08
|
|
|
|
|
#define CFENABLEDV 0x0010 /* Perform Domain Validation */
|
|
|
|
|
#define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */
|
|
|
|
|
#define CFSPARITY 0x0040 /* SCSI parity */
|
|
|
|
|
#define CFEXTEND 0x0080 /* extended translation enabled */
|
|
|
|
|
#define CFBOOTCD 0x0100 /* Support Bootable CD-ROM */
|
|
|
|
|
#define CFMSG_LEVEL 0x0600 /* BIOS Message Level */
|
|
|
|
|
#define CFMSG_VERBOSE 0x0000
|
|
|
|
|
#define CFMSG_SILENT 0x0200
|
|
|
|
|
#define CFMSG_DIAG 0x0400
|
|
|
|
|
#define CFRESETB 0x0800 /* reset SCSI bus at boot */
|
|
|
|
|
/* UNUSED 0xf000 */
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Host Adapter Control Bits
|
|
|
|
|
*/
|
|
|
|
|
uint16_t adapter_control; /* word 17 */
|
|
|
|
|
#define CFAUTOTERM 0x0001 /* Perform Auto termination */
|
|
|
|
|
#define CFSTERM 0x0002 /* SCSI low byte termination */
|
|
|
|
|
#define CFWSTERM 0x0004 /* SCSI high byte termination */
|
|
|
|
|
#define CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/
|
|
|
|
|
#define CFSELOWTERM 0x0010 /* Ultra2 secondary low term */
|
|
|
|
|
#define CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */
|
|
|
|
|
#define CFSTPWLEVEL 0x0040 /* Termination level control */
|
|
|
|
|
#define CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */
|
|
|
|
|
#define CFTERM_MENU 0x0100 /* BIOS displays termination menu */
|
|
|
|
|
#define CFCLUSTERENB 0x8000 /* Cluster Enable */
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Bus Release Time, Host Adapter ID
|
|
|
|
|
*/
|
|
|
|
|
uint16_t brtime_id; /* word 18 */
|
|
|
|
|
#define CFSCSIID 0x000f /* host adapter SCSI ID */
|
|
|
|
|
/* UNUSED 0x00f0 */
|
|
|
|
|
#define CFBRTIME 0xff00 /* bus release time/PCI Latency Time */
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Maximum targets
|
|
|
|
|
*/
|
|
|
|
|
uint16_t max_targets; /* word 19 */
|
|
|
|
|
#define CFMAXTARG 0x00ff /* maximum targets */
|
|
|
|
|
#define CFBOOTLUN 0x0f00 /* Lun to boot from */
|
|
|
|
|
#define CFBOOTID 0xf000 /* Target to boot from */
|
|
|
|
|
uint16_t res_1[10]; /* words 20-29 */
|
|
|
|
|
uint16_t signature; /* BIOS Signature */
|
|
|
|
|
#define CFSIGNATURE 0x400
|
|
|
|
|
uint16_t checksum; /* word 31 */
|
|
|
|
|
};
|
|
|
|
|
|
Correct spelling errors.
Switch to handling bad SCSI status as a sequencer interrupt
instead of having the kernel proccess these failures via
the completion queue. This is done because:
o The old scheme required us to pause the sequencer and clear
critical sections for each SCB. It seems that these pause
actions, if coincident with a sequencer FIFO interrupt, would
result in a FIFO interrupt getting lost or directing to the
wrong FIFO. This caused hangs when the driver was stressed
under high "queue full" loads.
o The completion code assumed that it was always called with
the sequencer running. This may not be the case in timeout
processing where completions occur manually via
ahd_pause_and_flushwork().
o With this scheme, the extra expense of clearing critical
sections is avoided since the sequencer will only self pause
once all pending selections have cleared and it is not in
a critical section.
aic79xx.c
Add code to handle the new BAD_SCB_STATUS sequencer
interrupt code. This just redirects the SCB through
the already existing ahd_complete_scb() code path.
Remove code in ahd_handle_scsi_status() that paused
the sequencer, made sure that no selections where
pending, and cleared critical sections. Bad
status SCBs are now only processed when all of these
conditions are true.
aic79xx.reg:
Add the BAD_SCB_STATUS sequencer interrupt code.
aic79xx.seq:
When completing an SCB upload to the host, if
we are doing this because the SCB contains non-zero
SCSI status, defer completing the SCB until there
are no pending selection events. When completing
these SCBs, use the new BAD_SCB_STATUS sequencer
interrupt. For all other uploaded SCBs (currently
only for underruns), the SCB is completed via the
normal done queue. Additionally, keep the SCB that
is currently being uploaded on the COMPLETE_DMA_SCB
list until the dma is completed, not just until the
DMA is started. This ensures that the DMA is restarted
properly should the host disable the DMA transfer for
some reason.
In our RevA workaround for Maxtor drives, guard against
the host pausing us while trying to pause I/O until the
first data-valid REQ by clearing the current snapshot
so that we can tell if the transfer has completed prior
to us noticing the REQINIT status.
In cfg4data_intr, shave off an instruction before getting
the data path running by adding an entrypoint to the
overrun handler to also increment the FIFO use count.
In the overrun handler, be sure to clear our LONGJMP
address in both exit paths.
Perform a few sequencer optimizations.
aic79xx.c:
Print the full path from the SCB when a packetized
status overrun occurs.
Remove references to LONGJMP_SCB which is being
removed from firmware usage.
Print the new SCB_FIFO_USE_COUNT field in the
per-SCB section of ahd_dump_card_state(). The
SCB_TAG field is now re-used by the sequencer,
so it no longer makes sense to reference this
field in the kernel driver.
aic79xx.h:
Re-arrange fields in the hardware SCB from largest
size type to smallest. This makes it easier to
move fields without changing field alignment.
The hardware scb tag field is now down near the
"spare" portion of the SCB to facilitate reuse
by the sequencer.
aic79xx.reg:
Remove LONGJMP_ADDR.
Rearrange SCB fields to match aic79xx.h.
Add SCB_FIFO_USE_COUNT as the first byte
of the SCB_TAG field.
aic79xx.seq:
Add a per-SCB "Fifos in use count" field and use
it to determine when it is safe (all data posted)
to deliver status back to the host. The old method
involved polling one or both FIFOs to verify that
the current task did not have pending data. This
makes running down the GSFIFO very cheap, so we
will empty the GSFIFO in one idle loop pass in
all cases.
Use this simplification of the completion process
to prune down the data FIFO teardown sequencer for
packetized transfers. Much more code is now shared
between the data residual and transfer complete cases.
Correct some issues in the packetized status handler.
It used to be possible to CLRCHN our FIFO before status
had fully transferred to the host. We also failed to
handle NONPACKREQ phases that could occur should a CRC
error occur during transmission of the status data packet.
Correct a few big endian issues:
aic79xx.c:
aic79xx_inline.h:
aic79xx_pci.c:
aic79xx_osm.c:
o Always get the SCB's tag via the SCB_GET_TAG acccessor
o Add missing use of byte swapping macros when touching
hscb fields.
o Don't double swap SEEPROM data when it is printed.
Correct a big-endian bug. We cannot assign a
o When assigning a 32bit LE variable to a 64bit LE
variable, we must be explict about how the words
of the 64bit LE variable are initialized. Cast to
(uint32_t*) to do this.
aic79xx.c:
In ahd_clear_critical_section(), hit CRLSCSIINT
after restoring the interrupt masks to avoid what
appears to be a glitch on SCSIINT. Any real SCSIINT
status will be persistent and will immidiately
reset SCSIINT. This clear should only get rid of
spurious SCSIINTs.
This glitch was the cause of the "Unexpected PKT busfree"
status that occurred under high queue full loads
Call ahd_fini_scbdata() after shutdown so that
any ahd_chip_init() routine that might access
SCB data will not access free'd memory.
Reset the bus on an IOERR since the chip doesn't
seem to reset to the new voltage level without
this.
Change offset calculation for scatter gather maps
so that the calculation is correct if an integral
multiple of sg lists does not fit in the allocation
size.
Adjust bus dma tag for data buffers based on 39BIT
addressing flag in our softc.
Use the QFREEZE count to simplify ahd_pause_and_flushworkd().
We can thus rely on the sequencer eventually clearing ENSELO.
In ahd_abort_scbs(), fix a bug that could potentially
corrupt sequencer state. The saved SCB was being
restored in the SCSI mode instead of the saved mode.
It turns out that the SCB did not need to be saved at all
as the scbptr is already restored by all subroutines
called during this function that modify that register.
aic79xx.c:
aic79xx.h:
aic79xx_pci.c:
Add support for parsing the seeprom vital product
data. The VPD data are currently unused.
aic79xx.h:
aic79xx.seq:
aic79xx_pci.c:
Add a firmware workaround to make the LED blink
brighter during packetized operations on the H2A.
aic79xx_inline.h:
The host does not use timer interrupts, so don't
gate our decision on whether or not to unpause
the sequencer on whether or not a timer interrupt
is pending.
2003-05-04 00:20:07 +00:00
|
|
|
/*
|
|
|
|
|
* Vital Product Data used during POST and by the BIOS.
|
|
|
|
|
*/
|
|
|
|
|
struct vpd_config {
|
|
|
|
|
uint8_t bios_flags;
|
|
|
|
|
#define VPDMASTERBIOS 0x0001
|
|
|
|
|
#define VPDBOOTHOST 0x0002
|
|
|
|
|
uint8_t reserved_1[21];
|
|
|
|
|
uint8_t resource_type;
|
|
|
|
|
uint8_t resource_len[2];
|
|
|
|
|
uint8_t resource_data[8];
|
|
|
|
|
uint8_t vpd_tag;
|
|
|
|
|
uint16_t vpd_len;
|
|
|
|
|
uint8_t vpd_keyword[2];
|
|
|
|
|
uint8_t length;
|
|
|
|
|
uint8_t revision;
|
|
|
|
|
uint8_t device_flags;
|
|
|
|
|
uint8_t termnation_menus[2];
|
|
|
|
|
uint8_t fifo_threshold;
|
|
|
|
|
uint8_t end_tag;
|
|
|
|
|
uint8_t vpd_checksum;
|
|
|
|
|
uint16_t default_target_flags;
|
|
|
|
|
uint16_t default_bios_flags;
|
|
|
|
|
uint16_t default_ctrl_flags;
|
|
|
|
|
uint8_t default_irq;
|
|
|
|
|
uint8_t pci_lattime;
|
|
|
|
|
uint8_t max_target;
|
|
|
|
|
uint8_t boot_lun;
|
|
|
|
|
uint16_t signature;
|
|
|
|
|
uint8_t reserved_2;
|
|
|
|
|
uint8_t checksum;
|
|
|
|
|
uint8_t reserved_3[4];
|
|
|
|
|
};
|
|
|
|
|
|
2002-06-05 19:52:45 +00:00
|
|
|
/****************************** Flexport Logic ********************************/
|
|
|
|
|
#define FLXADDR_TERMCTL 0x0
|
|
|
|
|
#define FLX_TERMCTL_ENSECHIGH 0x8
|
|
|
|
|
#define FLX_TERMCTL_ENSECLOW 0x4
|
|
|
|
|
#define FLX_TERMCTL_ENPRIHIGH 0x2
|
|
|
|
|
#define FLX_TERMCTL_ENPRILOW 0x1
|
|
|
|
|
#define FLXADDR_ROMSTAT_CURSENSECTL 0x1
|
|
|
|
|
#define FLX_ROMSTAT_SEECFG 0xF0
|
|
|
|
|
#define FLX_ROMSTAT_EECFG 0x0F
|
|
|
|
|
#define FLX_ROMSTAT_SEE_93C66 0x00
|
|
|
|
|
#define FLX_ROMSTAT_SEE_NONE 0xF0
|
|
|
|
|
#define FLX_ROMSTAT_EE_512x8 0x0
|
|
|
|
|
#define FLX_ROMSTAT_EE_1MBx8 0x1
|
|
|
|
|
#define FLX_ROMSTAT_EE_2MBx8 0x2
|
|
|
|
|
#define FLX_ROMSTAT_EE_4MBx8 0x3
|
|
|
|
|
#define FLX_ROMSTAT_EE_16MBx8 0x4
|
|
|
|
|
#define CURSENSE_ENB 0x1
|
|
|
|
|
#define FLXADDR_FLEXSTAT 0x2
|
|
|
|
|
#define FLX_FSTAT_BUSY 0x1
|
|
|
|
|
#define FLXADDR_CURRENT_STAT 0x4
|
|
|
|
|
#define FLX_CSTAT_SEC_HIGH 0xC0
|
|
|
|
|
#define FLX_CSTAT_SEC_LOW 0x30
|
|
|
|
|
#define FLX_CSTAT_PRI_HIGH 0x0C
|
|
|
|
|
#define FLX_CSTAT_PRI_LOW 0x03
|
|
|
|
|
#define FLX_CSTAT_MASK 0x03
|
|
|
|
|
#define FLX_CSTAT_SHIFT 2
|
|
|
|
|
#define FLX_CSTAT_OKAY 0x0
|
|
|
|
|
#define FLX_CSTAT_OVER 0x1
|
|
|
|
|
#define FLX_CSTAT_UNDER 0x2
|
|
|
|
|
#define FLX_CSTAT_INVALID 0x3
|
|
|
|
|
|
|
|
|
|
int ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf,
|
Correct spelling errors.
Switch to handling bad SCSI status as a sequencer interrupt
instead of having the kernel proccess these failures via
the completion queue. This is done because:
o The old scheme required us to pause the sequencer and clear
critical sections for each SCB. It seems that these pause
actions, if coincident with a sequencer FIFO interrupt, would
result in a FIFO interrupt getting lost or directing to the
wrong FIFO. This caused hangs when the driver was stressed
under high "queue full" loads.
o The completion code assumed that it was always called with
the sequencer running. This may not be the case in timeout
processing where completions occur manually via
ahd_pause_and_flushwork().
o With this scheme, the extra expense of clearing critical
sections is avoided since the sequencer will only self pause
once all pending selections have cleared and it is not in
a critical section.
aic79xx.c
Add code to handle the new BAD_SCB_STATUS sequencer
interrupt code. This just redirects the SCB through
the already existing ahd_complete_scb() code path.
Remove code in ahd_handle_scsi_status() that paused
the sequencer, made sure that no selections where
pending, and cleared critical sections. Bad
status SCBs are now only processed when all of these
conditions are true.
aic79xx.reg:
Add the BAD_SCB_STATUS sequencer interrupt code.
aic79xx.seq:
When completing an SCB upload to the host, if
we are doing this because the SCB contains non-zero
SCSI status, defer completing the SCB until there
are no pending selection events. When completing
these SCBs, use the new BAD_SCB_STATUS sequencer
interrupt. For all other uploaded SCBs (currently
only for underruns), the SCB is completed via the
normal done queue. Additionally, keep the SCB that
is currently being uploaded on the COMPLETE_DMA_SCB
list until the dma is completed, not just until the
DMA is started. This ensures that the DMA is restarted
properly should the host disable the DMA transfer for
some reason.
In our RevA workaround for Maxtor drives, guard against
the host pausing us while trying to pause I/O until the
first data-valid REQ by clearing the current snapshot
so that we can tell if the transfer has completed prior
to us noticing the REQINIT status.
In cfg4data_intr, shave off an instruction before getting
the data path running by adding an entrypoint to the
overrun handler to also increment the FIFO use count.
In the overrun handler, be sure to clear our LONGJMP
address in both exit paths.
Perform a few sequencer optimizations.
aic79xx.c:
Print the full path from the SCB when a packetized
status overrun occurs.
Remove references to LONGJMP_SCB which is being
removed from firmware usage.
Print the new SCB_FIFO_USE_COUNT field in the
per-SCB section of ahd_dump_card_state(). The
SCB_TAG field is now re-used by the sequencer,
so it no longer makes sense to reference this
field in the kernel driver.
aic79xx.h:
Re-arrange fields in the hardware SCB from largest
size type to smallest. This makes it easier to
move fields without changing field alignment.
The hardware scb tag field is now down near the
"spare" portion of the SCB to facilitate reuse
by the sequencer.
aic79xx.reg:
Remove LONGJMP_ADDR.
Rearrange SCB fields to match aic79xx.h.
Add SCB_FIFO_USE_COUNT as the first byte
of the SCB_TAG field.
aic79xx.seq:
Add a per-SCB "Fifos in use count" field and use
it to determine when it is safe (all data posted)
to deliver status back to the host. The old method
involved polling one or both FIFOs to verify that
the current task did not have pending data. This
makes running down the GSFIFO very cheap, so we
will empty the GSFIFO in one idle loop pass in
all cases.
Use this simplification of the completion process
to prune down the data FIFO teardown sequencer for
packetized transfers. Much more code is now shared
between the data residual and transfer complete cases.
Correct some issues in the packetized status handler.
It used to be possible to CLRCHN our FIFO before status
had fully transferred to the host. We also failed to
handle NONPACKREQ phases that could occur should a CRC
error occur during transmission of the status data packet.
Correct a few big endian issues:
aic79xx.c:
aic79xx_inline.h:
aic79xx_pci.c:
aic79xx_osm.c:
o Always get the SCB's tag via the SCB_GET_TAG acccessor
o Add missing use of byte swapping macros when touching
hscb fields.
o Don't double swap SEEPROM data when it is printed.
Correct a big-endian bug. We cannot assign a
o When assigning a 32bit LE variable to a 64bit LE
variable, we must be explict about how the words
of the 64bit LE variable are initialized. Cast to
(uint32_t*) to do this.
aic79xx.c:
In ahd_clear_critical_section(), hit CRLSCSIINT
after restoring the interrupt masks to avoid what
appears to be a glitch on SCSIINT. Any real SCSIINT
status will be persistent and will immidiately
reset SCSIINT. This clear should only get rid of
spurious SCSIINTs.
This glitch was the cause of the "Unexpected PKT busfree"
status that occurred under high queue full loads
Call ahd_fini_scbdata() after shutdown so that
any ahd_chip_init() routine that might access
SCB data will not access free'd memory.
Reset the bus on an IOERR since the chip doesn't
seem to reset to the new voltage level without
this.
Change offset calculation for scatter gather maps
so that the calculation is correct if an integral
multiple of sg lists does not fit in the allocation
size.
Adjust bus dma tag for data buffers based on 39BIT
addressing flag in our softc.
Use the QFREEZE count to simplify ahd_pause_and_flushworkd().
We can thus rely on the sequencer eventually clearing ENSELO.
In ahd_abort_scbs(), fix a bug that could potentially
corrupt sequencer state. The saved SCB was being
restored in the SCSI mode instead of the saved mode.
It turns out that the SCB did not need to be saved at all
as the scbptr is already restored by all subroutines
called during this function that modify that register.
aic79xx.c:
aic79xx.h:
aic79xx_pci.c:
Add support for parsing the seeprom vital product
data. The VPD data are currently unused.
aic79xx.h:
aic79xx.seq:
aic79xx_pci.c:
Add a firmware workaround to make the LED blink
brighter during packetized operations on the H2A.
aic79xx_inline.h:
The host does not use timer interrupts, so don't
gate our decision on whether or not to unpause
the sequencer on whether or not a timer interrupt
is pending.
2003-05-04 00:20:07 +00:00
|
|
|
u_int start_addr, u_int count, int bstream);
|
2002-06-05 19:52:45 +00:00
|
|
|
|
|
|
|
|
int ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf,
|
|
|
|
|
u_int start_addr, u_int count);
|
|
|
|
|
int ahd_wait_seeprom(struct ahd_softc *ahd);
|
Correct spelling errors.
Switch to handling bad SCSI status as a sequencer interrupt
instead of having the kernel proccess these failures via
the completion queue. This is done because:
o The old scheme required us to pause the sequencer and clear
critical sections for each SCB. It seems that these pause
actions, if coincident with a sequencer FIFO interrupt, would
result in a FIFO interrupt getting lost or directing to the
wrong FIFO. This caused hangs when the driver was stressed
under high "queue full" loads.
o The completion code assumed that it was always called with
the sequencer running. This may not be the case in timeout
processing where completions occur manually via
ahd_pause_and_flushwork().
o With this scheme, the extra expense of clearing critical
sections is avoided since the sequencer will only self pause
once all pending selections have cleared and it is not in
a critical section.
aic79xx.c
Add code to handle the new BAD_SCB_STATUS sequencer
interrupt code. This just redirects the SCB through
the already existing ahd_complete_scb() code path.
Remove code in ahd_handle_scsi_status() that paused
the sequencer, made sure that no selections where
pending, and cleared critical sections. Bad
status SCBs are now only processed when all of these
conditions are true.
aic79xx.reg:
Add the BAD_SCB_STATUS sequencer interrupt code.
aic79xx.seq:
When completing an SCB upload to the host, if
we are doing this because the SCB contains non-zero
SCSI status, defer completing the SCB until there
are no pending selection events. When completing
these SCBs, use the new BAD_SCB_STATUS sequencer
interrupt. For all other uploaded SCBs (currently
only for underruns), the SCB is completed via the
normal done queue. Additionally, keep the SCB that
is currently being uploaded on the COMPLETE_DMA_SCB
list until the dma is completed, not just until the
DMA is started. This ensures that the DMA is restarted
properly should the host disable the DMA transfer for
some reason.
In our RevA workaround for Maxtor drives, guard against
the host pausing us while trying to pause I/O until the
first data-valid REQ by clearing the current snapshot
so that we can tell if the transfer has completed prior
to us noticing the REQINIT status.
In cfg4data_intr, shave off an instruction before getting
the data path running by adding an entrypoint to the
overrun handler to also increment the FIFO use count.
In the overrun handler, be sure to clear our LONGJMP
address in both exit paths.
Perform a few sequencer optimizations.
aic79xx.c:
Print the full path from the SCB when a packetized
status overrun occurs.
Remove references to LONGJMP_SCB which is being
removed from firmware usage.
Print the new SCB_FIFO_USE_COUNT field in the
per-SCB section of ahd_dump_card_state(). The
SCB_TAG field is now re-used by the sequencer,
so it no longer makes sense to reference this
field in the kernel driver.
aic79xx.h:
Re-arrange fields in the hardware SCB from largest
size type to smallest. This makes it easier to
move fields without changing field alignment.
The hardware scb tag field is now down near the
"spare" portion of the SCB to facilitate reuse
by the sequencer.
aic79xx.reg:
Remove LONGJMP_ADDR.
Rearrange SCB fields to match aic79xx.h.
Add SCB_FIFO_USE_COUNT as the first byte
of the SCB_TAG field.
aic79xx.seq:
Add a per-SCB "Fifos in use count" field and use
it to determine when it is safe (all data posted)
to deliver status back to the host. The old method
involved polling one or both FIFOs to verify that
the current task did not have pending data. This
makes running down the GSFIFO very cheap, so we
will empty the GSFIFO in one idle loop pass in
all cases.
Use this simplification of the completion process
to prune down the data FIFO teardown sequencer for
packetized transfers. Much more code is now shared
between the data residual and transfer complete cases.
Correct some issues in the packetized status handler.
It used to be possible to CLRCHN our FIFO before status
had fully transferred to the host. We also failed to
handle NONPACKREQ phases that could occur should a CRC
error occur during transmission of the status data packet.
Correct a few big endian issues:
aic79xx.c:
aic79xx_inline.h:
aic79xx_pci.c:
aic79xx_osm.c:
o Always get the SCB's tag via the SCB_GET_TAG acccessor
o Add missing use of byte swapping macros when touching
hscb fields.
o Don't double swap SEEPROM data when it is printed.
Correct a big-endian bug. We cannot assign a
o When assigning a 32bit LE variable to a 64bit LE
variable, we must be explict about how the words
of the 64bit LE variable are initialized. Cast to
(uint32_t*) to do this.
aic79xx.c:
In ahd_clear_critical_section(), hit CRLSCSIINT
after restoring the interrupt masks to avoid what
appears to be a glitch on SCSIINT. Any real SCSIINT
status will be persistent and will immidiately
reset SCSIINT. This clear should only get rid of
spurious SCSIINTs.
This glitch was the cause of the "Unexpected PKT busfree"
status that occurred under high queue full loads
Call ahd_fini_scbdata() after shutdown so that
any ahd_chip_init() routine that might access
SCB data will not access free'd memory.
Reset the bus on an IOERR since the chip doesn't
seem to reset to the new voltage level without
this.
Change offset calculation for scatter gather maps
so that the calculation is correct if an integral
multiple of sg lists does not fit in the allocation
size.
Adjust bus dma tag for data buffers based on 39BIT
addressing flag in our softc.
Use the QFREEZE count to simplify ahd_pause_and_flushworkd().
We can thus rely on the sequencer eventually clearing ENSELO.
In ahd_abort_scbs(), fix a bug that could potentially
corrupt sequencer state. The saved SCB was being
restored in the SCSI mode instead of the saved mode.
It turns out that the SCB did not need to be saved at all
as the scbptr is already restored by all subroutines
called during this function that modify that register.
aic79xx.c:
aic79xx.h:
aic79xx_pci.c:
Add support for parsing the seeprom vital product
data. The VPD data are currently unused.
aic79xx.h:
aic79xx.seq:
aic79xx_pci.c:
Add a firmware workaround to make the LED blink
brighter during packetized operations on the H2A.
aic79xx_inline.h:
The host does not use timer interrupts, so don't
gate our decision on whether or not to unpause
the sequencer on whether or not a timer interrupt
is pending.
2003-05-04 00:20:07 +00:00
|
|
|
int ahd_verify_vpd_cksum(struct vpd_config *vpd);
|
2002-06-05 19:52:45 +00:00
|
|
|
int ahd_verify_cksum(struct seeprom_config *sc);
|
|
|
|
|
int ahd_acquire_seeprom(struct ahd_softc *ahd);
|
|
|
|
|
void ahd_release_seeprom(struct ahd_softc *ahd);
|
|
|
|
|
|
|
|
|
|
/**************************** Message Buffer *********************************/
|
|
|
|
|
typedef enum {
|
|
|
|
|
MSG_FLAG_NONE = 0x00,
|
|
|
|
|
MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01,
|
|
|
|
|
MSG_FLAG_IU_REQ_CHANGED = 0x02,
|
|
|
|
|
MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04,
|
2002-12-01 08:13:37 +00:00
|
|
|
MSG_FLAG_EXPECT_QASREJ_BUSFREE = 0x08,
|
|
|
|
|
MSG_FLAG_PACKETIZED = 0x10
|
2002-06-05 19:52:45 +00:00
|
|
|
} ahd_msg_flags;
|
|
|
|
|
|
|
|
|
|
typedef enum {
|
|
|
|
|
MSG_TYPE_NONE = 0x00,
|
|
|
|
|
MSG_TYPE_INITIATOR_MSGOUT = 0x01,
|
|
|
|
|
MSG_TYPE_INITIATOR_MSGIN = 0x02,
|
|
|
|
|
MSG_TYPE_TARGET_MSGOUT = 0x03,
|
|
|
|
|
MSG_TYPE_TARGET_MSGIN = 0x04
|
|
|
|
|
} ahd_msg_type;
|
|
|
|
|
|
|
|
|
|
typedef enum {
|
|
|
|
|
MSGLOOP_IN_PROG,
|
|
|
|
|
MSGLOOP_MSGCOMPLETE,
|
|
|
|
|
MSGLOOP_TERMINATED
|
|
|
|
|
} msg_loop_stat;
|
|
|
|
|
|
|
|
|
|
/*********************** Software Configuration Structure *********************/
|
|
|
|
|
struct ahd_suspend_channel_state {
|
|
|
|
|
uint8_t scsiseq;
|
|
|
|
|
uint8_t sxfrctl0;
|
|
|
|
|
uint8_t sxfrctl1;
|
|
|
|
|
uint8_t simode0;
|
|
|
|
|
uint8_t simode1;
|
|
|
|
|
uint8_t seltimer;
|
|
|
|
|
uint8_t seqctl;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct ahd_suspend_state {
|
|
|
|
|
struct ahd_suspend_channel_state channel[2];
|
|
|
|
|
uint8_t optionmode;
|
|
|
|
|
uint8_t dscommand0;
|
|
|
|
|
uint8_t dspcistatus;
|
|
|
|
|
/* hsmailbox */
|
|
|
|
|
uint8_t crccontrol1;
|
|
|
|
|
uint8_t scbbaddr;
|
|
|
|
|
/* Host and sequencer SCB counts */
|
|
|
|
|
uint8_t dff_thrsh;
|
|
|
|
|
uint8_t *scratch_ram;
|
|
|
|
|
uint8_t *btt;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
typedef void (*ahd_bus_intr_t)(struct ahd_softc *);
|
|
|
|
|
|
|
|
|
|
typedef enum {
|
|
|
|
|
AHD_MODE_DFF0,
|
|
|
|
|
AHD_MODE_DFF1,
|
|
|
|
|
AHD_MODE_CCHAN,
|
|
|
|
|
AHD_MODE_SCSI,
|
|
|
|
|
AHD_MODE_CFG,
|
|
|
|
|
AHD_MODE_UNKNOWN
|
|
|
|
|
} ahd_mode;
|
|
|
|
|
|
|
|
|
|
#define AHD_MK_MSK(x) (0x01 << (x))
|
|
|
|
|
#define AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0)
|
|
|
|
|
#define AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1)
|
|
|
|
|
#define AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN)
|
|
|
|
|
#define AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI)
|
|
|
|
|
#define AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG)
|
|
|
|
|
#define AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN)
|
|
|
|
|
#define AHD_MODE_ANY_MSK (~0)
|
|
|
|
|
|
|
|
|
|
typedef uint8_t ahd_mode_state;
|
|
|
|
|
|
|
|
|
|
typedef void ahd_callback_t (void *);
|
|
|
|
|
|
aic79xx.c:
aic79xx.seq:
Convert the COMPLETE_DMA_SCB list to an "stailq". This allows us to
safely keep the SCB that is currently being DMA'ed back the host on
the head of the list while processing completions off of the bus. The
newly completed SCBs are appended to the tail of the queue. In the
past, we just dequeued the SCB that was in flight from the list, but
this could result in a lost completion should the host perform certain
types of error recovery that must cancel all in-flight SCB DMA operations.
Switch from using a 16bit completion entry, holding just the tag and the
completion valid bit, to a 64bit completion entry that also contains a
"status packet valid" indicator. This solves two problems:
o The SCB DMA engine on at least Rev B. silicon does not properly deal
with a PCI disconnect that occurs at a non-64bit aligned offset in the
chips "source buffer". When the transfer is resumed, the DMA engine
continues at the correct offset, but may wrap to the head of the buffer
causing duplicate completions to be reported to the host. By using a
completion buffer in host memory that is 64bit aligned and using 64bit
completion entries, such disconnects should only occur at aligned addresses.
This assumes that the host bridge will only disconnect on cache-line
boundaries and that cache-lines are multpiles of 64bits.
o By embedding the status information in the completion entry we can avoid
an extra memory reference to the HSCB for commands that complete without
error.
Use the comparison of a "host freeze count" and a "sequencer freeze count"
to allow the host to process most SCBs that complete with non-zero status
without having to clear critical sections. Instead the host can just pause the
sequencer, performs any necessary cleanup in the waiting for selection list,
increments its freeze count on the controller, and unpauses. This is only
possible because the sequencer defers completions of SCBs with bad status
until after all pending selections have completed. The sequencer then avoids
referencing any data structures the host may touch during completion of the
SCB until the freeze counts match.
aic79xx.c:
Change the strategy for allocating our sentinal HSCB for the QINFIFO. In
the past, this allocation was tacked onto the QOUTFIFO allocation. Now that
the qoutfifo has grown to accomodate larger completion entries, the old
approach will result in a 64byte allocation that costs an extra page of
coherent memory. We now do this extra allocation via ahd_alloc_scbs()
where the "unused space" can be used to allocate "normal" HSCBs.
In our packetized busfree handler, use the ENSELO bit to differentiate
between packetized and non-packetized unexpected busfree events that
occur just after selection, but before the sequencer has had the oportunity
to service the selection.
When cleaning out the waiting for selection list, use the SCSI mode
instead of the command channel mode. The SCB pointer in the command
channel mode may be referenced by the SCB dma engine even while the
sequencer is paused, whereas the SCSI mode SCB pointer is only accessed
by the sequencer.
Print the "complete on qfreeze" sequencer SCB completion list in
ahd_dump_card_state(). This list holds all SCB completions that are deferred
until a pending select-out qfreeze event has taken effect.
aic79xx.h:
Add definitions and structures to handle the new SCB completion scheme.
Add a controller flag that indicates if the controller is in HostRAID
mode.
aic79xx.reg:
Remove macros used for toggling from one data fifo mode to the other.
They have not been in use for some time.
Add scratch ram fields for our new qfreeze count scheme, converting
the complete dma list into an "stailq", and providing for the "complete
on qfreeze" SCB completion list. Some other fields were moved to retain
proper field alignment (alignment >= field size in bytes).
aic79xx.seq:
Add code to our idle loop to:
o Process deferred completions once a qfreeze event has taken full
effect.
o Thaw the queue once the sequencer and host qfreeze counts match.
Generate 64bit completion entries passing the SCB_SGPTR field as the
"good status" indicator. The first bit in this field is only set if
we have a valid status packet to send to the host.
Convert the COMPLETE_DMA_SCB list to an "stailq".
When using "setjmp" to register an idle loop handler, do not combine
the "ret" with the block move to pop the stack address in the same
instruction. At least on the A, this results in a return to the setjmp
caller, not to the new address at the top of the stack. Since we want
the latter (we want the newly registered handler to only be invoked from
the idle loop), we must use a separate ret instruction.
Add a few missing critical sections.
Close a race condition that can occur on Rev A. silicon. If both FIFOs
happen to be allocated before the sequencer has a chance to service the
FIFO that was allocated first, we must take special care to service the
FIFO that is not active on the SCSI bus first. This guarantees that a
FIFO will be freed to handle any snapshot requests for the FIFO that is
still on the bus. Chosing the incorrect FIFO will result in deadlock.
Update comments.
aic79xx_inline.h
Correct the offset calculation for the syncing of our qoutfifo.
Update ahd_check_cmdcmpltqueues() for the larger completion entries.
aic79xx_pci.c:
Attach to HostRAID controllers by default. In the future I may add a
sysctl to modify the behavior, but since FreeBSD does not have any
HostRAID drivers, failing to attach just results in more email and
bug reports for the author.
MFC After: 1week
2004-02-04 16:38:38 +00:00
|
|
|
struct ahd_completion
|
|
|
|
|
{
|
|
|
|
|
uint16_t tag;
|
|
|
|
|
uint8_t sg_status;
|
|
|
|
|
uint8_t valid_tag;
|
|
|
|
|
};
|
|
|
|
|
|
2002-06-05 19:52:45 +00:00
|
|
|
struct ahd_softc {
|
|
|
|
|
bus_space_tag_t tags[2];
|
|
|
|
|
bus_space_handle_t bshs[2];
|
|
|
|
|
#ifndef __linux__
|
|
|
|
|
bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
|
|
|
|
|
#endif
|
|
|
|
|
struct scb_data scb_data;
|
|
|
|
|
|
2002-08-31 06:48:42 +00:00
|
|
|
struct hardware_scb *next_queued_hscb;
|
ahc_eisa.c:
ahc_pci.c:
ahd_pci.c:
aic7xxx.c:
aic79xx.c:
aic_osm_lib.c:
aic_osm_lib.h:
Use common OSM routines from aic_osm_lib for bus dma operations,
delay routines, accessing CCBs, byte swapping, etc.
aic7xxx_pci.c:
Provide a better description for the 2915/30LP on attach.
aic7xxx.c:
aic79xx.c:
aic7770.c:
aic79xx_pci.c:
aic7xxx_pci.c:
aic7xxx_93cx6.c:
Move FBSDID behind an ifdef so that these core files will
still compile under other OSes.
aic79xx.h:
aic79xx_pci.c:
aic79xx.seq:
To speed up non-packetized CDB delivery in Rev B, all CDB
acks are "released" to the output sync as soon as the
command phase starts. There is only one problem with this
approach. If the target changes phase before all data are
sent, we have left over acks that can go out on the bus in
a data phase. Due to other chip contraints, this only
happens if the target goes to data-in, but if the acks go
out before we can test SDONE, we'll think that the transfer
has completed successfully. Work around this by taking
advantage of the 400ns or 800ns dead time between command
phase and the REQ of the new phase. If the transfer has
completed successfully, SCSIEN should fall *long* before we
see a phase change. We thus treat any phasemiss that
occurs before SCSIEN falls as an incomplete transfer.
aic79xx.h:
Add the AHD_FAST_CDB_DELIVERY feature.
aic79xx_pci.c:
Set AHD_FAST_CDB_DELIVERY for all Rev. B parts.
aic79xx.seq:
Test for PHASEMIS in the command phase for
all AHD_FAST_CDB_DELIVERY controlelrs.
ahd_pci.c:
ahc_pci.c:
aic7xxx.h:
aic79xx.h:
Move definition of controller BAR offsets to core header files.
aic7xxx.c:
aic79xx.c:
In the softc free routine, leave removal of a softc from the
global list of softcs to the OSM (the caller of this routine).
This allows us to avoid holding the softc list_lock during device
destruction where we may have to sleep waiting for our recovery
thread to halt.
ahc_pci.c:
Use ahc_pci_test_register access to validate I/O mapped in
addition to the tests already performed for memory mapped
access.
Remove unused ahc_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
ahd_pci.c:
Remove reduntant definition of controller BAR offsets. These
are also defined in aic79xx.h.
Remove unused ahd_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
aic7xxx.c:
aic79xx.c:
aic79xx.h:
aic7xxx.h:
aic7xxx_osm.c:
aic79xx_osm.c:
Move timeout handling to the driver cores. In the case
of the aic79xx driver, the algorithm has been enhanced
to try target resets before performing a bus reset. For
the aic7xxx driver, the algorithm is unchanged. Although
the drivers do not currently sleep during recovery (recovery
is timeout driven), the cores do expect all processing to
be performed via a recovery thread. Our timeout handlers
are now little stubs that wakeup the recovery thread.
aic79xx.c:
aic79xx.h:
aic79xx_inline.h:
Change shared_data allocation to use a map_node so
that the sentinel hscb can use this map node in
ahd_swap_with_next_hscb. This routine now swaps
the hscb_map pointer in additon to the hscb
contents so that any sync operations occur on
the correct map.
physaddr -> busaddr
Pointed out by: Jason Thorpe <thorpej@wasabisystems.com>
aic79xx.c:
Make more use of the in/out/w/l/q macros for accessing
byte registers in the chip.
Correct some issues in the ahd_flush_qoutfifo() routine.
o Run the qoutfifo only once the command channel
DMA engine has been halted. This closes a window
where we might have missed some entries.
o Change ahd_run_data_fifo() to not loop to completion.
If we happen to start on the wrong FIFO and the other
FIFO has a snapshot savepointers, we might deadlock.
This required our delay between FIFO tests to be
moved to the ahd_flush_qoutfifo() routine.
o Update/add comments.
o Remove spurious test for COMPLETE_DMA list being empty
when completing transactions from the GSFIFO with
residuals. The SCB must be put on the COMPLETE_DMA
scb list unconditionally.
o When halting command channel DMA activity, we must
disable the DMA channel in all cases but an update
of the QOUTFIFO. The latter case is required so
that the sequencer will update its position in the
QOUTFIFO. Previously, we left the channel enabled
for all "push" DMAs. This left us vulnerable to
the sequencer handling an SCB push long after that
SCB was already processed manually by this routine.
o Correct the polarity of tests involving
ahd_scb_active_in_fifo(). This routine returns
non-zero for true.
Return to processing bad status completions through
the qoutfifo. This reduces the time that the sequencer
is kept paused when handling transactions with bad
status or underruns.
When waiting for the controller to quiece selections,
add a delay to our loop. Otherwise we may fail to wait
long enough for the sequencer to comply.
On H2A4 hardware, use the slow slewrate for non-paced
transfers. This mirrors what the Adaptec Windows
drivers do.
On the Rev B. only slow down the CRC timing for
older U160 devices that might need the slower timing.
We define "older" as devices that do not support
packetized protocol.
Wait up to 5000 * 5us for the SEEPROM to become unbusy.
Write ops seem to take much longer than read ops.
aic79xx.seq:
For controllers with the FAINT_LED bug, turn the diagnostic
led feature on during selection and reselection. This covers
the non-packetized case. The LED will be disabled for
non-packetized transfers once we return to the top level idle
loop. Add more comments about the busy LED workaround.
Extend a critical section around the entire
command channel idle loop process. Previously
the portion of this handler that directly manipulated
the linked list of completed SCBs was not protected.
This is the likely cause of the recent reports of
commands being completed twice by the driver.
Extend critical sections across the test for,
and the longjump to, longjump routines. This
prevents the firmware from trying to jump to
a longjmp handler that was just cleared by the
host.
Improve the locations of several critical section
begin and end points. Typically these changes
remove instructions that did not need to be
inside a critical section.
Close the "busfree after selection, but before busfree
interrupts can be enabled" race to just a single sequencer
instruction. We now test the BSY line explicitly before
clearing the busfree status and enabling the busfree
interrupt.
Close a race condition in the processing of HS_MAILBOX
updates. We now clear the "updated" status before the
copy. This ensures that we don't accidentally clear
the status incorrectly when the host sneaks in an update
just after our last copy, but before we clear the status.
This race has never been observed.
Don't re-enable SCSIEN if we lose the race to disable SCSIEN
in our interrupt handler's workaround for the RevA data-valid
too early issue.
aic79xx_inline.h:
Add comments indicating that the order in which bytes are
read or written in ahd_inw and ahd_outw is important. This
allows us to use these inlines when accessing registers with
side-effects.
aic79xx_pci.c:
The 29320 and the 29320B are 7902 not 7901 based products.
Correct the driver banner.
aic7xxx.h:
Enable the use of the auto-access pause feature
on the aic7870 and aic7880. It was disabled due
to an oversight.
aic7xxx.reg:
Move TARG_IMMEDIATE_SCB to alias LAST_MSG to
avoid leaving garbage in MWI_RESIDUAL. This
prevents spurious overflows whn operating target
mode on controllers that require the MWI_RESIDUAL
work-around.
aic7xxx.seq:
AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag.
Reference the correct softc field when testing
for its presence.
Set the NOT_IDENTIFIED and NO_CDB_SENT bits
in SEQ_FLAGS to indicate that the nexus is
invalid in await busfree.
aic7xxx_93cx6.c:
Add support for the C56/C66 versions of the EWEN and EWDS
commands.
aic7xxx.c:
aic7xxx_pci.c:
Move test for the validity of left over BIOS data
to ahc_test_register_access(). This guarantees that
any left over CHIPRST value is not clobbered by our
register access test and lost to the test that was
in ahc_reset.
2003-12-17 00:02:10 +00:00
|
|
|
struct map_node *next_queued_hscb_map;
|
2002-06-05 19:52:45 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* SCBs that have been sent to the controller
|
|
|
|
|
*/
|
|
|
|
|
LIST_HEAD(, scb) pending_scbs;
|
|
|
|
|
|
ahc_eisa.c:
ahc_pci.c:
ahd_pci.c:
aic7xxx.c:
aic79xx.c:
aic_osm_lib.c:
aic_osm_lib.h:
Use common OSM routines from aic_osm_lib for bus dma operations,
delay routines, accessing CCBs, byte swapping, etc.
aic7xxx_pci.c:
Provide a better description for the 2915/30LP on attach.
aic7xxx.c:
aic79xx.c:
aic7770.c:
aic79xx_pci.c:
aic7xxx_pci.c:
aic7xxx_93cx6.c:
Move FBSDID behind an ifdef so that these core files will
still compile under other OSes.
aic79xx.h:
aic79xx_pci.c:
aic79xx.seq:
To speed up non-packetized CDB delivery in Rev B, all CDB
acks are "released" to the output sync as soon as the
command phase starts. There is only one problem with this
approach. If the target changes phase before all data are
sent, we have left over acks that can go out on the bus in
a data phase. Due to other chip contraints, this only
happens if the target goes to data-in, but if the acks go
out before we can test SDONE, we'll think that the transfer
has completed successfully. Work around this by taking
advantage of the 400ns or 800ns dead time between command
phase and the REQ of the new phase. If the transfer has
completed successfully, SCSIEN should fall *long* before we
see a phase change. We thus treat any phasemiss that
occurs before SCSIEN falls as an incomplete transfer.
aic79xx.h:
Add the AHD_FAST_CDB_DELIVERY feature.
aic79xx_pci.c:
Set AHD_FAST_CDB_DELIVERY for all Rev. B parts.
aic79xx.seq:
Test for PHASEMIS in the command phase for
all AHD_FAST_CDB_DELIVERY controlelrs.
ahd_pci.c:
ahc_pci.c:
aic7xxx.h:
aic79xx.h:
Move definition of controller BAR offsets to core header files.
aic7xxx.c:
aic79xx.c:
In the softc free routine, leave removal of a softc from the
global list of softcs to the OSM (the caller of this routine).
This allows us to avoid holding the softc list_lock during device
destruction where we may have to sleep waiting for our recovery
thread to halt.
ahc_pci.c:
Use ahc_pci_test_register access to validate I/O mapped in
addition to the tests already performed for memory mapped
access.
Remove unused ahc_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
ahd_pci.c:
Remove reduntant definition of controller BAR offsets. These
are also defined in aic79xx.h.
Remove unused ahd_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
aic7xxx.c:
aic79xx.c:
aic79xx.h:
aic7xxx.h:
aic7xxx_osm.c:
aic79xx_osm.c:
Move timeout handling to the driver cores. In the case
of the aic79xx driver, the algorithm has been enhanced
to try target resets before performing a bus reset. For
the aic7xxx driver, the algorithm is unchanged. Although
the drivers do not currently sleep during recovery (recovery
is timeout driven), the cores do expect all processing to
be performed via a recovery thread. Our timeout handlers
are now little stubs that wakeup the recovery thread.
aic79xx.c:
aic79xx.h:
aic79xx_inline.h:
Change shared_data allocation to use a map_node so
that the sentinel hscb can use this map node in
ahd_swap_with_next_hscb. This routine now swaps
the hscb_map pointer in additon to the hscb
contents so that any sync operations occur on
the correct map.
physaddr -> busaddr
Pointed out by: Jason Thorpe <thorpej@wasabisystems.com>
aic79xx.c:
Make more use of the in/out/w/l/q macros for accessing
byte registers in the chip.
Correct some issues in the ahd_flush_qoutfifo() routine.
o Run the qoutfifo only once the command channel
DMA engine has been halted. This closes a window
where we might have missed some entries.
o Change ahd_run_data_fifo() to not loop to completion.
If we happen to start on the wrong FIFO and the other
FIFO has a snapshot savepointers, we might deadlock.
This required our delay between FIFO tests to be
moved to the ahd_flush_qoutfifo() routine.
o Update/add comments.
o Remove spurious test for COMPLETE_DMA list being empty
when completing transactions from the GSFIFO with
residuals. The SCB must be put on the COMPLETE_DMA
scb list unconditionally.
o When halting command channel DMA activity, we must
disable the DMA channel in all cases but an update
of the QOUTFIFO. The latter case is required so
that the sequencer will update its position in the
QOUTFIFO. Previously, we left the channel enabled
for all "push" DMAs. This left us vulnerable to
the sequencer handling an SCB push long after that
SCB was already processed manually by this routine.
o Correct the polarity of tests involving
ahd_scb_active_in_fifo(). This routine returns
non-zero for true.
Return to processing bad status completions through
the qoutfifo. This reduces the time that the sequencer
is kept paused when handling transactions with bad
status or underruns.
When waiting for the controller to quiece selections,
add a delay to our loop. Otherwise we may fail to wait
long enough for the sequencer to comply.
On H2A4 hardware, use the slow slewrate for non-paced
transfers. This mirrors what the Adaptec Windows
drivers do.
On the Rev B. only slow down the CRC timing for
older U160 devices that might need the slower timing.
We define "older" as devices that do not support
packetized protocol.
Wait up to 5000 * 5us for the SEEPROM to become unbusy.
Write ops seem to take much longer than read ops.
aic79xx.seq:
For controllers with the FAINT_LED bug, turn the diagnostic
led feature on during selection and reselection. This covers
the non-packetized case. The LED will be disabled for
non-packetized transfers once we return to the top level idle
loop. Add more comments about the busy LED workaround.
Extend a critical section around the entire
command channel idle loop process. Previously
the portion of this handler that directly manipulated
the linked list of completed SCBs was not protected.
This is the likely cause of the recent reports of
commands being completed twice by the driver.
Extend critical sections across the test for,
and the longjump to, longjump routines. This
prevents the firmware from trying to jump to
a longjmp handler that was just cleared by the
host.
Improve the locations of several critical section
begin and end points. Typically these changes
remove instructions that did not need to be
inside a critical section.
Close the "busfree after selection, but before busfree
interrupts can be enabled" race to just a single sequencer
instruction. We now test the BSY line explicitly before
clearing the busfree status and enabling the busfree
interrupt.
Close a race condition in the processing of HS_MAILBOX
updates. We now clear the "updated" status before the
copy. This ensures that we don't accidentally clear
the status incorrectly when the host sneaks in an update
just after our last copy, but before we clear the status.
This race has never been observed.
Don't re-enable SCSIEN if we lose the race to disable SCSIEN
in our interrupt handler's workaround for the RevA data-valid
too early issue.
aic79xx_inline.h:
Add comments indicating that the order in which bytes are
read or written in ahd_inw and ahd_outw is important. This
allows us to use these inlines when accessing registers with
side-effects.
aic79xx_pci.c:
The 29320 and the 29320B are 7902 not 7901 based products.
Correct the driver banner.
aic7xxx.h:
Enable the use of the auto-access pause feature
on the aic7870 and aic7880. It was disabled due
to an oversight.
aic7xxx.reg:
Move TARG_IMMEDIATE_SCB to alias LAST_MSG to
avoid leaving garbage in MWI_RESIDUAL. This
prevents spurious overflows whn operating target
mode on controllers that require the MWI_RESIDUAL
work-around.
aic7xxx.seq:
AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag.
Reference the correct softc field when testing
for its presence.
Set the NOT_IDENTIFIED and NO_CDB_SENT bits
in SEQ_FLAGS to indicate that the nexus is
invalid in await busfree.
aic7xxx_93cx6.c:
Add support for the C56/C66 versions of the EWEN and EWDS
commands.
aic7xxx.c:
aic7xxx_pci.c:
Move test for the validity of left over BIOS data
to ahc_test_register_access(). This guarantees that
any left over CHIPRST value is not clobbered by our
register access test and lost to the test that was
in ahc_reset.
2003-12-17 00:02:10 +00:00
|
|
|
/*
|
|
|
|
|
* SCBs whose timeout routine has been called.
|
|
|
|
|
*/
|
|
|
|
|
LIST_HEAD(, scb) timedout_scbs;
|
|
|
|
|
|
2002-06-05 19:52:45 +00:00
|
|
|
/*
|
|
|
|
|
* Current register window mode information.
|
|
|
|
|
*/
|
|
|
|
|
ahd_mode dst_mode;
|
|
|
|
|
ahd_mode src_mode;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Saved register window mode information
|
|
|
|
|
* used for restore on next unpause.
|
|
|
|
|
*/
|
|
|
|
|
ahd_mode saved_dst_mode;
|
|
|
|
|
ahd_mode saved_src_mode;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Platform specific data.
|
|
|
|
|
*/
|
|
|
|
|
struct ahd_platform_data *platform_data;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Platform specific device information.
|
|
|
|
|
*/
|
ahc_eisa.c:
ahc_pci.c:
ahd_pci.c:
aic7xxx.c:
aic79xx.c:
aic_osm_lib.c:
aic_osm_lib.h:
Use common OSM routines from aic_osm_lib for bus dma operations,
delay routines, accessing CCBs, byte swapping, etc.
aic7xxx_pci.c:
Provide a better description for the 2915/30LP on attach.
aic7xxx.c:
aic79xx.c:
aic7770.c:
aic79xx_pci.c:
aic7xxx_pci.c:
aic7xxx_93cx6.c:
Move FBSDID behind an ifdef so that these core files will
still compile under other OSes.
aic79xx.h:
aic79xx_pci.c:
aic79xx.seq:
To speed up non-packetized CDB delivery in Rev B, all CDB
acks are "released" to the output sync as soon as the
command phase starts. There is only one problem with this
approach. If the target changes phase before all data are
sent, we have left over acks that can go out on the bus in
a data phase. Due to other chip contraints, this only
happens if the target goes to data-in, but if the acks go
out before we can test SDONE, we'll think that the transfer
has completed successfully. Work around this by taking
advantage of the 400ns or 800ns dead time between command
phase and the REQ of the new phase. If the transfer has
completed successfully, SCSIEN should fall *long* before we
see a phase change. We thus treat any phasemiss that
occurs before SCSIEN falls as an incomplete transfer.
aic79xx.h:
Add the AHD_FAST_CDB_DELIVERY feature.
aic79xx_pci.c:
Set AHD_FAST_CDB_DELIVERY for all Rev. B parts.
aic79xx.seq:
Test for PHASEMIS in the command phase for
all AHD_FAST_CDB_DELIVERY controlelrs.
ahd_pci.c:
ahc_pci.c:
aic7xxx.h:
aic79xx.h:
Move definition of controller BAR offsets to core header files.
aic7xxx.c:
aic79xx.c:
In the softc free routine, leave removal of a softc from the
global list of softcs to the OSM (the caller of this routine).
This allows us to avoid holding the softc list_lock during device
destruction where we may have to sleep waiting for our recovery
thread to halt.
ahc_pci.c:
Use ahc_pci_test_register access to validate I/O mapped in
addition to the tests already performed for memory mapped
access.
Remove unused ahc_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
ahd_pci.c:
Remove reduntant definition of controller BAR offsets. These
are also defined in aic79xx.h.
Remove unused ahd_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
aic7xxx.c:
aic79xx.c:
aic79xx.h:
aic7xxx.h:
aic7xxx_osm.c:
aic79xx_osm.c:
Move timeout handling to the driver cores. In the case
of the aic79xx driver, the algorithm has been enhanced
to try target resets before performing a bus reset. For
the aic7xxx driver, the algorithm is unchanged. Although
the drivers do not currently sleep during recovery (recovery
is timeout driven), the cores do expect all processing to
be performed via a recovery thread. Our timeout handlers
are now little stubs that wakeup the recovery thread.
aic79xx.c:
aic79xx.h:
aic79xx_inline.h:
Change shared_data allocation to use a map_node so
that the sentinel hscb can use this map node in
ahd_swap_with_next_hscb. This routine now swaps
the hscb_map pointer in additon to the hscb
contents so that any sync operations occur on
the correct map.
physaddr -> busaddr
Pointed out by: Jason Thorpe <thorpej@wasabisystems.com>
aic79xx.c:
Make more use of the in/out/w/l/q macros for accessing
byte registers in the chip.
Correct some issues in the ahd_flush_qoutfifo() routine.
o Run the qoutfifo only once the command channel
DMA engine has been halted. This closes a window
where we might have missed some entries.
o Change ahd_run_data_fifo() to not loop to completion.
If we happen to start on the wrong FIFO and the other
FIFO has a snapshot savepointers, we might deadlock.
This required our delay between FIFO tests to be
moved to the ahd_flush_qoutfifo() routine.
o Update/add comments.
o Remove spurious test for COMPLETE_DMA list being empty
when completing transactions from the GSFIFO with
residuals. The SCB must be put on the COMPLETE_DMA
scb list unconditionally.
o When halting command channel DMA activity, we must
disable the DMA channel in all cases but an update
of the QOUTFIFO. The latter case is required so
that the sequencer will update its position in the
QOUTFIFO. Previously, we left the channel enabled
for all "push" DMAs. This left us vulnerable to
the sequencer handling an SCB push long after that
SCB was already processed manually by this routine.
o Correct the polarity of tests involving
ahd_scb_active_in_fifo(). This routine returns
non-zero for true.
Return to processing bad status completions through
the qoutfifo. This reduces the time that the sequencer
is kept paused when handling transactions with bad
status or underruns.
When waiting for the controller to quiece selections,
add a delay to our loop. Otherwise we may fail to wait
long enough for the sequencer to comply.
On H2A4 hardware, use the slow slewrate for non-paced
transfers. This mirrors what the Adaptec Windows
drivers do.
On the Rev B. only slow down the CRC timing for
older U160 devices that might need the slower timing.
We define "older" as devices that do not support
packetized protocol.
Wait up to 5000 * 5us for the SEEPROM to become unbusy.
Write ops seem to take much longer than read ops.
aic79xx.seq:
For controllers with the FAINT_LED bug, turn the diagnostic
led feature on during selection and reselection. This covers
the non-packetized case. The LED will be disabled for
non-packetized transfers once we return to the top level idle
loop. Add more comments about the busy LED workaround.
Extend a critical section around the entire
command channel idle loop process. Previously
the portion of this handler that directly manipulated
the linked list of completed SCBs was not protected.
This is the likely cause of the recent reports of
commands being completed twice by the driver.
Extend critical sections across the test for,
and the longjump to, longjump routines. This
prevents the firmware from trying to jump to
a longjmp handler that was just cleared by the
host.
Improve the locations of several critical section
begin and end points. Typically these changes
remove instructions that did not need to be
inside a critical section.
Close the "busfree after selection, but before busfree
interrupts can be enabled" race to just a single sequencer
instruction. We now test the BSY line explicitly before
clearing the busfree status and enabling the busfree
interrupt.
Close a race condition in the processing of HS_MAILBOX
updates. We now clear the "updated" status before the
copy. This ensures that we don't accidentally clear
the status incorrectly when the host sneaks in an update
just after our last copy, but before we clear the status.
This race has never been observed.
Don't re-enable SCSIEN if we lose the race to disable SCSIEN
in our interrupt handler's workaround for the RevA data-valid
too early issue.
aic79xx_inline.h:
Add comments indicating that the order in which bytes are
read or written in ahd_inw and ahd_outw is important. This
allows us to use these inlines when accessing registers with
side-effects.
aic79xx_pci.c:
The 29320 and the 29320B are 7902 not 7901 based products.
Correct the driver banner.
aic7xxx.h:
Enable the use of the auto-access pause feature
on the aic7870 and aic7880. It was disabled due
to an oversight.
aic7xxx.reg:
Move TARG_IMMEDIATE_SCB to alias LAST_MSG to
avoid leaving garbage in MWI_RESIDUAL. This
prevents spurious overflows whn operating target
mode on controllers that require the MWI_RESIDUAL
work-around.
aic7xxx.seq:
AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag.
Reference the correct softc field when testing
for its presence.
Set the NOT_IDENTIFIED and NO_CDB_SENT bits
in SEQ_FLAGS to indicate that the nexus is
invalid in await busfree.
aic7xxx_93cx6.c:
Add support for the C56/C66 versions of the EWEN and EWDS
commands.
aic7xxx.c:
aic7xxx_pci.c:
Move test for the validity of left over BIOS data
to ahc_test_register_access(). This guarantees that
any left over CHIPRST value is not clobbered by our
register access test and lost to the test that was
in ahc_reset.
2003-12-17 00:02:10 +00:00
|
|
|
aic_dev_softc_t dev_softc;
|
2002-06-05 19:52:45 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Bus specific device information.
|
|
|
|
|
*/
|
|
|
|
|
ahd_bus_intr_t bus_intr;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Target mode related state kept on a per enabled lun basis.
|
|
|
|
|
* Targets that are not enabled will have null entries.
|
|
|
|
|
* As an initiator, we keep one target entry for our initiator
|
|
|
|
|
* ID to store our sync/wide transfer settings.
|
|
|
|
|
*/
|
|
|
|
|
struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS];
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The black hole device responsible for handling requests for
|
|
|
|
|
* disabled luns on enabled targets.
|
|
|
|
|
*/
|
|
|
|
|
struct ahd_tmode_lstate *black_hole;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Device instance currently on the bus awaiting a continue TIO
|
|
|
|
|
* for a command that was not given the disconnect priveledge.
|
|
|
|
|
*/
|
|
|
|
|
struct ahd_tmode_lstate *pending_device;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Timer handles for timer driven callbacks.
|
|
|
|
|
*/
|
ahc_eisa.c:
ahc_pci.c:
ahd_pci.c:
aic7xxx.c:
aic79xx.c:
aic_osm_lib.c:
aic_osm_lib.h:
Use common OSM routines from aic_osm_lib for bus dma operations,
delay routines, accessing CCBs, byte swapping, etc.
aic7xxx_pci.c:
Provide a better description for the 2915/30LP on attach.
aic7xxx.c:
aic79xx.c:
aic7770.c:
aic79xx_pci.c:
aic7xxx_pci.c:
aic7xxx_93cx6.c:
Move FBSDID behind an ifdef so that these core files will
still compile under other OSes.
aic79xx.h:
aic79xx_pci.c:
aic79xx.seq:
To speed up non-packetized CDB delivery in Rev B, all CDB
acks are "released" to the output sync as soon as the
command phase starts. There is only one problem with this
approach. If the target changes phase before all data are
sent, we have left over acks that can go out on the bus in
a data phase. Due to other chip contraints, this only
happens if the target goes to data-in, but if the acks go
out before we can test SDONE, we'll think that the transfer
has completed successfully. Work around this by taking
advantage of the 400ns or 800ns dead time between command
phase and the REQ of the new phase. If the transfer has
completed successfully, SCSIEN should fall *long* before we
see a phase change. We thus treat any phasemiss that
occurs before SCSIEN falls as an incomplete transfer.
aic79xx.h:
Add the AHD_FAST_CDB_DELIVERY feature.
aic79xx_pci.c:
Set AHD_FAST_CDB_DELIVERY for all Rev. B parts.
aic79xx.seq:
Test for PHASEMIS in the command phase for
all AHD_FAST_CDB_DELIVERY controlelrs.
ahd_pci.c:
ahc_pci.c:
aic7xxx.h:
aic79xx.h:
Move definition of controller BAR offsets to core header files.
aic7xxx.c:
aic79xx.c:
In the softc free routine, leave removal of a softc from the
global list of softcs to the OSM (the caller of this routine).
This allows us to avoid holding the softc list_lock during device
destruction where we may have to sleep waiting for our recovery
thread to halt.
ahc_pci.c:
Use ahc_pci_test_register access to validate I/O mapped in
addition to the tests already performed for memory mapped
access.
Remove unused ahc_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
ahd_pci.c:
Remove reduntant definition of controller BAR offsets. These
are also defined in aic79xx.h.
Remove unused ahd_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
aic7xxx.c:
aic79xx.c:
aic79xx.h:
aic7xxx.h:
aic7xxx_osm.c:
aic79xx_osm.c:
Move timeout handling to the driver cores. In the case
of the aic79xx driver, the algorithm has been enhanced
to try target resets before performing a bus reset. For
the aic7xxx driver, the algorithm is unchanged. Although
the drivers do not currently sleep during recovery (recovery
is timeout driven), the cores do expect all processing to
be performed via a recovery thread. Our timeout handlers
are now little stubs that wakeup the recovery thread.
aic79xx.c:
aic79xx.h:
aic79xx_inline.h:
Change shared_data allocation to use a map_node so
that the sentinel hscb can use this map node in
ahd_swap_with_next_hscb. This routine now swaps
the hscb_map pointer in additon to the hscb
contents so that any sync operations occur on
the correct map.
physaddr -> busaddr
Pointed out by: Jason Thorpe <thorpej@wasabisystems.com>
aic79xx.c:
Make more use of the in/out/w/l/q macros for accessing
byte registers in the chip.
Correct some issues in the ahd_flush_qoutfifo() routine.
o Run the qoutfifo only once the command channel
DMA engine has been halted. This closes a window
where we might have missed some entries.
o Change ahd_run_data_fifo() to not loop to completion.
If we happen to start on the wrong FIFO and the other
FIFO has a snapshot savepointers, we might deadlock.
This required our delay between FIFO tests to be
moved to the ahd_flush_qoutfifo() routine.
o Update/add comments.
o Remove spurious test for COMPLETE_DMA list being empty
when completing transactions from the GSFIFO with
residuals. The SCB must be put on the COMPLETE_DMA
scb list unconditionally.
o When halting command channel DMA activity, we must
disable the DMA channel in all cases but an update
of the QOUTFIFO. The latter case is required so
that the sequencer will update its position in the
QOUTFIFO. Previously, we left the channel enabled
for all "push" DMAs. This left us vulnerable to
the sequencer handling an SCB push long after that
SCB was already processed manually by this routine.
o Correct the polarity of tests involving
ahd_scb_active_in_fifo(). This routine returns
non-zero for true.
Return to processing bad status completions through
the qoutfifo. This reduces the time that the sequencer
is kept paused when handling transactions with bad
status or underruns.
When waiting for the controller to quiece selections,
add a delay to our loop. Otherwise we may fail to wait
long enough for the sequencer to comply.
On H2A4 hardware, use the slow slewrate for non-paced
transfers. This mirrors what the Adaptec Windows
drivers do.
On the Rev B. only slow down the CRC timing for
older U160 devices that might need the slower timing.
We define "older" as devices that do not support
packetized protocol.
Wait up to 5000 * 5us for the SEEPROM to become unbusy.
Write ops seem to take much longer than read ops.
aic79xx.seq:
For controllers with the FAINT_LED bug, turn the diagnostic
led feature on during selection and reselection. This covers
the non-packetized case. The LED will be disabled for
non-packetized transfers once we return to the top level idle
loop. Add more comments about the busy LED workaround.
Extend a critical section around the entire
command channel idle loop process. Previously
the portion of this handler that directly manipulated
the linked list of completed SCBs was not protected.
This is the likely cause of the recent reports of
commands being completed twice by the driver.
Extend critical sections across the test for,
and the longjump to, longjump routines. This
prevents the firmware from trying to jump to
a longjmp handler that was just cleared by the
host.
Improve the locations of several critical section
begin and end points. Typically these changes
remove instructions that did not need to be
inside a critical section.
Close the "busfree after selection, but before busfree
interrupts can be enabled" race to just a single sequencer
instruction. We now test the BSY line explicitly before
clearing the busfree status and enabling the busfree
interrupt.
Close a race condition in the processing of HS_MAILBOX
updates. We now clear the "updated" status before the
copy. This ensures that we don't accidentally clear
the status incorrectly when the host sneaks in an update
just after our last copy, but before we clear the status.
This race has never been observed.
Don't re-enable SCSIEN if we lose the race to disable SCSIEN
in our interrupt handler's workaround for the RevA data-valid
too early issue.
aic79xx_inline.h:
Add comments indicating that the order in which bytes are
read or written in ahd_inw and ahd_outw is important. This
allows us to use these inlines when accessing registers with
side-effects.
aic79xx_pci.c:
The 29320 and the 29320B are 7902 not 7901 based products.
Correct the driver banner.
aic7xxx.h:
Enable the use of the auto-access pause feature
on the aic7870 and aic7880. It was disabled due
to an oversight.
aic7xxx.reg:
Move TARG_IMMEDIATE_SCB to alias LAST_MSG to
avoid leaving garbage in MWI_RESIDUAL. This
prevents spurious overflows whn operating target
mode on controllers that require the MWI_RESIDUAL
work-around.
aic7xxx.seq:
AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag.
Reference the correct softc field when testing
for its presence.
Set the NOT_IDENTIFIED and NO_CDB_SENT bits
in SEQ_FLAGS to indicate that the nexus is
invalid in await busfree.
aic7xxx_93cx6.c:
Add support for the C56/C66 versions of the EWEN and EWDS
commands.
aic7xxx.c:
aic7xxx_pci.c:
Move test for the validity of left over BIOS data
to ahc_test_register_access(). This guarantees that
any left over CHIPRST value is not clobbered by our
register access test and lost to the test that was
in ahc_reset.
2003-12-17 00:02:10 +00:00
|
|
|
aic_timer_t reset_timer;
|
|
|
|
|
aic_timer_t stat_timer;
|
aic79xx.c:
Implement the SCB_SILENT flag. This is useful for
hushing up the driver during DV or other operations
that we expect to cause transmission errors. The
messages will still print if the SHOW_MASKED_ERRORS
debug option is enabled.
Save and restore the NEGOADDR address when setting
new transfer settings. The sequencer performs lookups
in the negotiation table too and it expects NEGOADDR
to remain consistent across pause/unpause sessions.
Consistently use "offset" instead of "period" to determine
if we are running sync or not.
Add a SHOW_MESSAGES diagnostic for when we assert ATN
during message processing.
Print out IU, QAS, and RTI features when showing transfer options.
Limit the syncrate after all option conformance
changes have taken place in ahd_devlimited_syncrate.
Changes in options may change the final syncrate we
accept.
Keep a copy of the hs_mailbox in our softc so that
we can perform read/modify/write operations on the
hs_mailbox without having to pause the sequencer to
read the last written value. Use the ENINT_COALESS
flag in the hs_mailbox to toggle interrupt coalessing.
Add entrypoints for enabling interrupt coalessing and
setting both a timeout (how long to wait for commands
to be coalessed) and a maximum commands to coaless value.
Add a statistics timer that decides when to enable or
disable interrupt coalessing based on load.
Add a routine, ahd_reset_cmds_pending() which is used
to update the CMDS_PENDING sequencer variable whenever
error recovery compeltes SCBs without notifying the
sequencer. Since ahd_reset_cmds_pending is called
during ahd_unpause() only if we've aborted SCBs, its
call to ahd_flush_qoutfifo should not cause recursion
through ahd_run_qoutfifo(). A panic has been added to
ensure that this recursion does not occur.
In ahd_search_qinfifo, update the CMDS_PENDING sequencer
variable directly. ahd_search_qinififo can be called
in situations where using ahd_reset_cmds_pending() might
cause recursion. Since we can safely determine the
exact number to reduce CMDS_PENDING by in this scenario
without running the qoutfifo, the manual update is sufficient.
Clean up diagnostics.
Add ahd_flush_qoutfifo() which will run the qoutfifo
as well as complete any commands sitting on the
sequencer's COMPLETE_SCB lists or the good status FIFO.
Use this routine in several places that did similar
things in an add-hoc, but incomplete, fashion. A call
to this routine was also added to ahd_abort_scbs() to
close a race.
In ahd_pause_and_flushwork() only return once selections
are safely disabled. Flush all completed commands via
ahd_flush_qoutfifo().
Remove "Now packetized" diagnostic now that this
information is incorperated into the actual negotiation
messages that are displayed.
When forcing renegotiation, don't clober the current
ppr_options. Much of the driver uses this information
to determine if we are currently packetized or not.
Remove some stray spaces at column 1 in ahd_set_tags.
When complaining about getting a host message loop
request with no pending messages, print out the
SCB_CONTROL register down on the card.
Modify the ahd_sent_msg() routine to handle a search
for an outgoing identify message. Use this to detect
a msg reject on an identify message which typically
indicates that the target thought we were packetized.
Force a renegotiation in this case.
In ahd_search_qinfifo(), wait more effectively for SCB
DMA activities to cease. We also disable SCB fetch
operations since we are about to change the qinfifo
and any fetch in progress will likely be invalidated.
In ahd_qinfifo_count(), fix the qinfifo empty case.
In ahd_dump_card_state(), print out CCSCBCTL in the
correct mode.
If we are a narrow controller, don't set the current
width to unknown when forcing a future negotiation.
This just confuses the code into attempting a wide
negotiation on a narrow bus.
Add support for task management function completions.
Modify ahd_handle_devreset so that it can handle
lun resets in addition to target resets. Use
ahd_handle_devreset for lun and target reset task
management functions.
Handle the abort task TMF race case better. We now
wait until any current selections are over and then
set the TMF back to zero. This should cause the sequencer
to ignore the abort TMF completion should it occur.
Correct a bug in the illegal phase handler that
caused us to drop down to narrow when handling the
unexpected command phase case after 3rd party
reset of a packetized device.
Indicate the features, bugs, and flags set in the softc
that are used to control firmware patch download when
booting verbose.
aic79xx.h:
Add coalessing and HS_MAILBOX fields.
Add per-softc variables for the stats "daemon".
Add a debug option for interrupt coalessing activities.
Add two new softc flags:
o AHD_UPDATE_PEND_CMDS
Run ahd_reset_cmds_pending() on the next unpause.
o AHD_RUNNING_QOUTFIFO
Used to catch recursion through ahd_run_qoutfifo().
aic79xx.reg:
Correct register addresses related to the software timer
and the DFDBCTL register.
Add constants paramaterizing the software timer.
Add scratch ram locations for storing interrupt coalessing
tunables.
Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2.
In at least the REV A, these are writable bits. We make
use of that for a swtimer workaround in the sequencer.
Since HS_MAILBOX autoclears, provide a sequencer variable
to store its contents.
Add SEQINT codes for handling task management completions.
aic79xx.seq:
Correct ignore wide residue processing check for
a wide negotiation being in effect. We must be
in the SCSI register window in order to access the
negotiation table.
Use the software timer and a commands completed count to
implement interrupt coalessing. The command complete is
deferred until either the maximum command threshold or a
the expiration of a command deferral timer. If we have
more SCBs to complete to the host (sitting in COMPLETE_SCB
lists), always try to coaless them up to our coalessing limit.
If coalessing is enabled, but we have fewer commands oustanting
than the host's min coalessing limit, complete the command
immediately.
Add code to track the number of commands outstanding.
Commands are outstanding from the time they are placed
into the execution queue until the DMA to post completion
is setup.
Add a workaround for intvec_2 interrupts on the H2A4.
In H2A4, the mode pointer is not saved for intvec2, but
is restored on iret. This can lead to the restoration
of a bogus mode ptr. Manually clear the intmask bits and
do a normal return to compensate. We use intvec_2 to
track interrupt coalessing timeouts.
Since we cannot disable the swtimer's countdown, simply
mask its interrupt once we no longer care about it firing.
In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime
we are notified of an HS_MAILBOX update via the
HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a
local copy of persistant portions of the HS_MAILBOX as
the mailbox auto-clears on any read.
Move the test for the cfg4istat interrupt up an instruction
to hopefully close a race between the next outgoing selection
and our disabling of selections.
Add a missing ret to the last instruction in load_overrun_buf.
Add notifications to the host of task management
completions as well as the completions for commands
that completed successfully before their corresponding
TMF could be sent.
Hold a critical section during select-out processing
until we have a fully identified connection. This
removes a race condition with the legacy abort handler.
Correct a few spelling errors in some comments.
aic79xx_inline.h:
Call ahd_reset_cmds_pending() in ahd_unpause if required.
Update cmdcmplt interrupt statistics in our interrupt
handler.
Allow callers to ahd_send_scb() to set the task management
function.
aic79xx_pci.c:
Disable SERR and pause the controller prior to performing
our mmapped I/O test. The U320 controllers do not support
"auto-access-pause".
aic79xx_osm.c:
Set the task management function now that
ahd_send_scb() doesn't do it for us. We
also perform a lun reset in response to BDR
requests to packetized devices.
2003-01-20 20:17:35 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Statistics.
|
|
|
|
|
*/
|
|
|
|
|
#define AHD_STAT_UPDATE_US 250000 /* 250ms */
|
|
|
|
|
#define AHD_STAT_BUCKETS 4
|
|
|
|
|
u_int cmdcmplt_bucket;
|
|
|
|
|
uint32_t cmdcmplt_counts[AHD_STAT_BUCKETS];
|
|
|
|
|
uint32_t cmdcmplt_total;
|
2002-06-05 19:52:45 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Card characteristics
|
|
|
|
|
*/
|
|
|
|
|
ahd_chip chip;
|
|
|
|
|
ahd_feature features;
|
|
|
|
|
ahd_bug bugs;
|
|
|
|
|
ahd_flag flags;
|
|
|
|
|
struct seeprom_config *seep_config;
|
|
|
|
|
|
|
|
|
|
/* Command Queues */
|
aic79xx.c:
aic79xx.seq:
Convert the COMPLETE_DMA_SCB list to an "stailq". This allows us to
safely keep the SCB that is currently being DMA'ed back the host on
the head of the list while processing completions off of the bus. The
newly completed SCBs are appended to the tail of the queue. In the
past, we just dequeued the SCB that was in flight from the list, but
this could result in a lost completion should the host perform certain
types of error recovery that must cancel all in-flight SCB DMA operations.
Switch from using a 16bit completion entry, holding just the tag and the
completion valid bit, to a 64bit completion entry that also contains a
"status packet valid" indicator. This solves two problems:
o The SCB DMA engine on at least Rev B. silicon does not properly deal
with a PCI disconnect that occurs at a non-64bit aligned offset in the
chips "source buffer". When the transfer is resumed, the DMA engine
continues at the correct offset, but may wrap to the head of the buffer
causing duplicate completions to be reported to the host. By using a
completion buffer in host memory that is 64bit aligned and using 64bit
completion entries, such disconnects should only occur at aligned addresses.
This assumes that the host bridge will only disconnect on cache-line
boundaries and that cache-lines are multpiles of 64bits.
o By embedding the status information in the completion entry we can avoid
an extra memory reference to the HSCB for commands that complete without
error.
Use the comparison of a "host freeze count" and a "sequencer freeze count"
to allow the host to process most SCBs that complete with non-zero status
without having to clear critical sections. Instead the host can just pause the
sequencer, performs any necessary cleanup in the waiting for selection list,
increments its freeze count on the controller, and unpauses. This is only
possible because the sequencer defers completions of SCBs with bad status
until after all pending selections have completed. The sequencer then avoids
referencing any data structures the host may touch during completion of the
SCB until the freeze counts match.
aic79xx.c:
Change the strategy for allocating our sentinal HSCB for the QINFIFO. In
the past, this allocation was tacked onto the QOUTFIFO allocation. Now that
the qoutfifo has grown to accomodate larger completion entries, the old
approach will result in a 64byte allocation that costs an extra page of
coherent memory. We now do this extra allocation via ahd_alloc_scbs()
where the "unused space" can be used to allocate "normal" HSCBs.
In our packetized busfree handler, use the ENSELO bit to differentiate
between packetized and non-packetized unexpected busfree events that
occur just after selection, but before the sequencer has had the oportunity
to service the selection.
When cleaning out the waiting for selection list, use the SCSI mode
instead of the command channel mode. The SCB pointer in the command
channel mode may be referenced by the SCB dma engine even while the
sequencer is paused, whereas the SCSI mode SCB pointer is only accessed
by the sequencer.
Print the "complete on qfreeze" sequencer SCB completion list in
ahd_dump_card_state(). This list holds all SCB completions that are deferred
until a pending select-out qfreeze event has taken effect.
aic79xx.h:
Add definitions and structures to handle the new SCB completion scheme.
Add a controller flag that indicates if the controller is in HostRAID
mode.
aic79xx.reg:
Remove macros used for toggling from one data fifo mode to the other.
They have not been in use for some time.
Add scratch ram fields for our new qfreeze count scheme, converting
the complete dma list into an "stailq", and providing for the "complete
on qfreeze" SCB completion list. Some other fields were moved to retain
proper field alignment (alignment >= field size in bytes).
aic79xx.seq:
Add code to our idle loop to:
o Process deferred completions once a qfreeze event has taken full
effect.
o Thaw the queue once the sequencer and host qfreeze counts match.
Generate 64bit completion entries passing the SCB_SGPTR field as the
"good status" indicator. The first bit in this field is only set if
we have a valid status packet to send to the host.
Convert the COMPLETE_DMA_SCB list to an "stailq".
When using "setjmp" to register an idle loop handler, do not combine
the "ret" with the block move to pop the stack address in the same
instruction. At least on the A, this results in a return to the setjmp
caller, not to the new address at the top of the stack. Since we want
the latter (we want the newly registered handler to only be invoked from
the idle loop), we must use a separate ret instruction.
Add a few missing critical sections.
Close a race condition that can occur on Rev A. silicon. If both FIFOs
happen to be allocated before the sequencer has a chance to service the
FIFO that was allocated first, we must take special care to service the
FIFO that is not active on the SCSI bus first. This guarantees that a
FIFO will be freed to handle any snapshot requests for the FIFO that is
still on the bus. Chosing the incorrect FIFO will result in deadlock.
Update comments.
aic79xx_inline.h
Correct the offset calculation for the syncing of our qoutfifo.
Update ahd_check_cmdcmpltqueues() for the larger completion entries.
aic79xx_pci.c:
Attach to HostRAID controllers by default. In the future I may add a
sysctl to modify the behavior, but since FreeBSD does not have any
HostRAID drivers, failing to attach just results in more email and
bug reports for the author.
MFC After: 1week
2004-02-04 16:38:38 +00:00
|
|
|
struct ahd_completion *qoutfifo;
|
2002-06-05 19:52:45 +00:00
|
|
|
uint16_t qoutfifonext;
|
2002-08-31 06:48:42 +00:00
|
|
|
uint16_t qoutfifonext_valid_tag;
|
2002-06-05 19:52:45 +00:00
|
|
|
uint16_t qinfifonext;
|
|
|
|
|
uint16_t qinfifo[AHD_SCB_MAX];
|
aic79xx.c:
aic79xx.seq:
Convert the COMPLETE_DMA_SCB list to an "stailq". This allows us to
safely keep the SCB that is currently being DMA'ed back the host on
the head of the list while processing completions off of the bus. The
newly completed SCBs are appended to the tail of the queue. In the
past, we just dequeued the SCB that was in flight from the list, but
this could result in a lost completion should the host perform certain
types of error recovery that must cancel all in-flight SCB DMA operations.
Switch from using a 16bit completion entry, holding just the tag and the
completion valid bit, to a 64bit completion entry that also contains a
"status packet valid" indicator. This solves two problems:
o The SCB DMA engine on at least Rev B. silicon does not properly deal
with a PCI disconnect that occurs at a non-64bit aligned offset in the
chips "source buffer". When the transfer is resumed, the DMA engine
continues at the correct offset, but may wrap to the head of the buffer
causing duplicate completions to be reported to the host. By using a
completion buffer in host memory that is 64bit aligned and using 64bit
completion entries, such disconnects should only occur at aligned addresses.
This assumes that the host bridge will only disconnect on cache-line
boundaries and that cache-lines are multpiles of 64bits.
o By embedding the status information in the completion entry we can avoid
an extra memory reference to the HSCB for commands that complete without
error.
Use the comparison of a "host freeze count" and a "sequencer freeze count"
to allow the host to process most SCBs that complete with non-zero status
without having to clear critical sections. Instead the host can just pause the
sequencer, performs any necessary cleanup in the waiting for selection list,
increments its freeze count on the controller, and unpauses. This is only
possible because the sequencer defers completions of SCBs with bad status
until after all pending selections have completed. The sequencer then avoids
referencing any data structures the host may touch during completion of the
SCB until the freeze counts match.
aic79xx.c:
Change the strategy for allocating our sentinal HSCB for the QINFIFO. In
the past, this allocation was tacked onto the QOUTFIFO allocation. Now that
the qoutfifo has grown to accomodate larger completion entries, the old
approach will result in a 64byte allocation that costs an extra page of
coherent memory. We now do this extra allocation via ahd_alloc_scbs()
where the "unused space" can be used to allocate "normal" HSCBs.
In our packetized busfree handler, use the ENSELO bit to differentiate
between packetized and non-packetized unexpected busfree events that
occur just after selection, but before the sequencer has had the oportunity
to service the selection.
When cleaning out the waiting for selection list, use the SCSI mode
instead of the command channel mode. The SCB pointer in the command
channel mode may be referenced by the SCB dma engine even while the
sequencer is paused, whereas the SCSI mode SCB pointer is only accessed
by the sequencer.
Print the "complete on qfreeze" sequencer SCB completion list in
ahd_dump_card_state(). This list holds all SCB completions that are deferred
until a pending select-out qfreeze event has taken effect.
aic79xx.h:
Add definitions and structures to handle the new SCB completion scheme.
Add a controller flag that indicates if the controller is in HostRAID
mode.
aic79xx.reg:
Remove macros used for toggling from one data fifo mode to the other.
They have not been in use for some time.
Add scratch ram fields for our new qfreeze count scheme, converting
the complete dma list into an "stailq", and providing for the "complete
on qfreeze" SCB completion list. Some other fields were moved to retain
proper field alignment (alignment >= field size in bytes).
aic79xx.seq:
Add code to our idle loop to:
o Process deferred completions once a qfreeze event has taken full
effect.
o Thaw the queue once the sequencer and host qfreeze counts match.
Generate 64bit completion entries passing the SCB_SGPTR field as the
"good status" indicator. The first bit in this field is only set if
we have a valid status packet to send to the host.
Convert the COMPLETE_DMA_SCB list to an "stailq".
When using "setjmp" to register an idle loop handler, do not combine
the "ret" with the block move to pop the stack address in the same
instruction. At least on the A, this results in a return to the setjmp
caller, not to the new address at the top of the stack. Since we want
the latter (we want the newly registered handler to only be invoked from
the idle loop), we must use a separate ret instruction.
Add a few missing critical sections.
Close a race condition that can occur on Rev A. silicon. If both FIFOs
happen to be allocated before the sequencer has a chance to service the
FIFO that was allocated first, we must take special care to service the
FIFO that is not active on the SCSI bus first. This guarantees that a
FIFO will be freed to handle any snapshot requests for the FIFO that is
still on the bus. Chosing the incorrect FIFO will result in deadlock.
Update comments.
aic79xx_inline.h
Correct the offset calculation for the syncing of our qoutfifo.
Update ahd_check_cmdcmpltqueues() for the larger completion entries.
aic79xx_pci.c:
Attach to HostRAID controllers by default. In the future I may add a
sysctl to modify the behavior, but since FreeBSD does not have any
HostRAID drivers, failing to attach just results in more email and
bug reports for the author.
MFC After: 1week
2004-02-04 16:38:38 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Our qfreeze count. The sequencer compares
|
|
|
|
|
* this value with its own counter to determine
|
|
|
|
|
* whether to allow selections to occur.
|
|
|
|
|
*/
|
|
|
|
|
uint16_t qfreeze_cnt;
|
|
|
|
|
|
|
|
|
|
/* Values to store in the SEQCTL register for pause and unpause */
|
|
|
|
|
uint8_t unpause;
|
|
|
|
|
uint8_t pause;
|
2002-06-05 19:52:45 +00:00
|
|
|
|
|
|
|
|
/* Critical Section Data */
|
|
|
|
|
struct cs *critical_sections;
|
|
|
|
|
u_int num_critical_sections;
|
|
|
|
|
|
|
|
|
|
/* Buffer for handling packetized bitbucket. */
|
|
|
|
|
uint8_t *overrun_buf;
|
|
|
|
|
|
|
|
|
|
/* Links for chaining softcs */
|
|
|
|
|
TAILQ_ENTRY(ahd_softc) links;
|
|
|
|
|
|
|
|
|
|
/* Channel Names ('A', 'B', etc.) */
|
|
|
|
|
char channel;
|
|
|
|
|
|
|
|
|
|
/* Initiator Bus ID */
|
|
|
|
|
uint8_t our_id;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Target incoming command FIFO.
|
|
|
|
|
*/
|
|
|
|
|
struct target_cmd *targetcmds;
|
|
|
|
|
uint8_t tqinfifonext;
|
|
|
|
|
|
aic79xx.c:
Implement the SCB_SILENT flag. This is useful for
hushing up the driver during DV or other operations
that we expect to cause transmission errors. The
messages will still print if the SHOW_MASKED_ERRORS
debug option is enabled.
Save and restore the NEGOADDR address when setting
new transfer settings. The sequencer performs lookups
in the negotiation table too and it expects NEGOADDR
to remain consistent across pause/unpause sessions.
Consistently use "offset" instead of "period" to determine
if we are running sync or not.
Add a SHOW_MESSAGES diagnostic for when we assert ATN
during message processing.
Print out IU, QAS, and RTI features when showing transfer options.
Limit the syncrate after all option conformance
changes have taken place in ahd_devlimited_syncrate.
Changes in options may change the final syncrate we
accept.
Keep a copy of the hs_mailbox in our softc so that
we can perform read/modify/write operations on the
hs_mailbox without having to pause the sequencer to
read the last written value. Use the ENINT_COALESS
flag in the hs_mailbox to toggle interrupt coalessing.
Add entrypoints for enabling interrupt coalessing and
setting both a timeout (how long to wait for commands
to be coalessed) and a maximum commands to coaless value.
Add a statistics timer that decides when to enable or
disable interrupt coalessing based on load.
Add a routine, ahd_reset_cmds_pending() which is used
to update the CMDS_PENDING sequencer variable whenever
error recovery compeltes SCBs without notifying the
sequencer. Since ahd_reset_cmds_pending is called
during ahd_unpause() only if we've aborted SCBs, its
call to ahd_flush_qoutfifo should not cause recursion
through ahd_run_qoutfifo(). A panic has been added to
ensure that this recursion does not occur.
In ahd_search_qinfifo, update the CMDS_PENDING sequencer
variable directly. ahd_search_qinififo can be called
in situations where using ahd_reset_cmds_pending() might
cause recursion. Since we can safely determine the
exact number to reduce CMDS_PENDING by in this scenario
without running the qoutfifo, the manual update is sufficient.
Clean up diagnostics.
Add ahd_flush_qoutfifo() which will run the qoutfifo
as well as complete any commands sitting on the
sequencer's COMPLETE_SCB lists or the good status FIFO.
Use this routine in several places that did similar
things in an add-hoc, but incomplete, fashion. A call
to this routine was also added to ahd_abort_scbs() to
close a race.
In ahd_pause_and_flushwork() only return once selections
are safely disabled. Flush all completed commands via
ahd_flush_qoutfifo().
Remove "Now packetized" diagnostic now that this
information is incorperated into the actual negotiation
messages that are displayed.
When forcing renegotiation, don't clober the current
ppr_options. Much of the driver uses this information
to determine if we are currently packetized or not.
Remove some stray spaces at column 1 in ahd_set_tags.
When complaining about getting a host message loop
request with no pending messages, print out the
SCB_CONTROL register down on the card.
Modify the ahd_sent_msg() routine to handle a search
for an outgoing identify message. Use this to detect
a msg reject on an identify message which typically
indicates that the target thought we were packetized.
Force a renegotiation in this case.
In ahd_search_qinfifo(), wait more effectively for SCB
DMA activities to cease. We also disable SCB fetch
operations since we are about to change the qinfifo
and any fetch in progress will likely be invalidated.
In ahd_qinfifo_count(), fix the qinfifo empty case.
In ahd_dump_card_state(), print out CCSCBCTL in the
correct mode.
If we are a narrow controller, don't set the current
width to unknown when forcing a future negotiation.
This just confuses the code into attempting a wide
negotiation on a narrow bus.
Add support for task management function completions.
Modify ahd_handle_devreset so that it can handle
lun resets in addition to target resets. Use
ahd_handle_devreset for lun and target reset task
management functions.
Handle the abort task TMF race case better. We now
wait until any current selections are over and then
set the TMF back to zero. This should cause the sequencer
to ignore the abort TMF completion should it occur.
Correct a bug in the illegal phase handler that
caused us to drop down to narrow when handling the
unexpected command phase case after 3rd party
reset of a packetized device.
Indicate the features, bugs, and flags set in the softc
that are used to control firmware patch download when
booting verbose.
aic79xx.h:
Add coalessing and HS_MAILBOX fields.
Add per-softc variables for the stats "daemon".
Add a debug option for interrupt coalessing activities.
Add two new softc flags:
o AHD_UPDATE_PEND_CMDS
Run ahd_reset_cmds_pending() on the next unpause.
o AHD_RUNNING_QOUTFIFO
Used to catch recursion through ahd_run_qoutfifo().
aic79xx.reg:
Correct register addresses related to the software timer
and the DFDBCTL register.
Add constants paramaterizing the software timer.
Add scratch ram locations for storing interrupt coalessing
tunables.
Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2.
In at least the REV A, these are writable bits. We make
use of that for a swtimer workaround in the sequencer.
Since HS_MAILBOX autoclears, provide a sequencer variable
to store its contents.
Add SEQINT codes for handling task management completions.
aic79xx.seq:
Correct ignore wide residue processing check for
a wide negotiation being in effect. We must be
in the SCSI register window in order to access the
negotiation table.
Use the software timer and a commands completed count to
implement interrupt coalessing. The command complete is
deferred until either the maximum command threshold or a
the expiration of a command deferral timer. If we have
more SCBs to complete to the host (sitting in COMPLETE_SCB
lists), always try to coaless them up to our coalessing limit.
If coalessing is enabled, but we have fewer commands oustanting
than the host's min coalessing limit, complete the command
immediately.
Add code to track the number of commands outstanding.
Commands are outstanding from the time they are placed
into the execution queue until the DMA to post completion
is setup.
Add a workaround for intvec_2 interrupts on the H2A4.
In H2A4, the mode pointer is not saved for intvec2, but
is restored on iret. This can lead to the restoration
of a bogus mode ptr. Manually clear the intmask bits and
do a normal return to compensate. We use intvec_2 to
track interrupt coalessing timeouts.
Since we cannot disable the swtimer's countdown, simply
mask its interrupt once we no longer care about it firing.
In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime
we are notified of an HS_MAILBOX update via the
HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a
local copy of persistant portions of the HS_MAILBOX as
the mailbox auto-clears on any read.
Move the test for the cfg4istat interrupt up an instruction
to hopefully close a race between the next outgoing selection
and our disabling of selections.
Add a missing ret to the last instruction in load_overrun_buf.
Add notifications to the host of task management
completions as well as the completions for commands
that completed successfully before their corresponding
TMF could be sent.
Hold a critical section during select-out processing
until we have a fully identified connection. This
removes a race condition with the legacy abort handler.
Correct a few spelling errors in some comments.
aic79xx_inline.h:
Call ahd_reset_cmds_pending() in ahd_unpause if required.
Update cmdcmplt interrupt statistics in our interrupt
handler.
Allow callers to ahd_send_scb() to set the task management
function.
aic79xx_pci.c:
Disable SERR and pause the controller prior to performing
our mmapped I/O test. The U320 controllers do not support
"auto-access-pause".
aic79xx_osm.c:
Set the task management function now that
ahd_send_scb() doesn't do it for us. We
also perform a lun reset in response to BDR
requests to packetized devices.
2003-01-20 20:17:35 +00:00
|
|
|
/*
|
|
|
|
|
* Cached verson of the hs_mailbox so we can avoid
|
|
|
|
|
* pausing the sequencer during mailbox updates.
|
|
|
|
|
*/
|
|
|
|
|
uint8_t hs_mailbox;
|
|
|
|
|
|
2002-06-05 19:52:45 +00:00
|
|
|
/*
|
|
|
|
|
* Incoming and outgoing message handling.
|
|
|
|
|
*/
|
|
|
|
|
uint8_t send_msg_perror;
|
|
|
|
|
ahd_msg_flags msg_flags;
|
|
|
|
|
ahd_msg_type msg_type;
|
|
|
|
|
uint8_t msgout_buf[12];/* Message we are sending */
|
|
|
|
|
uint8_t msgin_buf[12];/* Message we are receiving */
|
|
|
|
|
u_int msgout_len; /* Length of message to send */
|
|
|
|
|
u_int msgout_index; /* Current index in msgout */
|
|
|
|
|
u_int msgin_index; /* Current index in msgin */
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Mapping information for data structures shared
|
|
|
|
|
* between the sequencer and kernel.
|
|
|
|
|
*/
|
|
|
|
|
bus_dma_tag_t parent_dmat;
|
|
|
|
|
bus_dma_tag_t shared_data_dmat;
|
ahc_eisa.c:
ahc_pci.c:
ahd_pci.c:
aic7xxx.c:
aic79xx.c:
aic_osm_lib.c:
aic_osm_lib.h:
Use common OSM routines from aic_osm_lib for bus dma operations,
delay routines, accessing CCBs, byte swapping, etc.
aic7xxx_pci.c:
Provide a better description for the 2915/30LP on attach.
aic7xxx.c:
aic79xx.c:
aic7770.c:
aic79xx_pci.c:
aic7xxx_pci.c:
aic7xxx_93cx6.c:
Move FBSDID behind an ifdef so that these core files will
still compile under other OSes.
aic79xx.h:
aic79xx_pci.c:
aic79xx.seq:
To speed up non-packetized CDB delivery in Rev B, all CDB
acks are "released" to the output sync as soon as the
command phase starts. There is only one problem with this
approach. If the target changes phase before all data are
sent, we have left over acks that can go out on the bus in
a data phase. Due to other chip contraints, this only
happens if the target goes to data-in, but if the acks go
out before we can test SDONE, we'll think that the transfer
has completed successfully. Work around this by taking
advantage of the 400ns or 800ns dead time between command
phase and the REQ of the new phase. If the transfer has
completed successfully, SCSIEN should fall *long* before we
see a phase change. We thus treat any phasemiss that
occurs before SCSIEN falls as an incomplete transfer.
aic79xx.h:
Add the AHD_FAST_CDB_DELIVERY feature.
aic79xx_pci.c:
Set AHD_FAST_CDB_DELIVERY for all Rev. B parts.
aic79xx.seq:
Test for PHASEMIS in the command phase for
all AHD_FAST_CDB_DELIVERY controlelrs.
ahd_pci.c:
ahc_pci.c:
aic7xxx.h:
aic79xx.h:
Move definition of controller BAR offsets to core header files.
aic7xxx.c:
aic79xx.c:
In the softc free routine, leave removal of a softc from the
global list of softcs to the OSM (the caller of this routine).
This allows us to avoid holding the softc list_lock during device
destruction where we may have to sleep waiting for our recovery
thread to halt.
ahc_pci.c:
Use ahc_pci_test_register access to validate I/O mapped in
addition to the tests already performed for memory mapped
access.
Remove unused ahc_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
ahd_pci.c:
Remove reduntant definition of controller BAR offsets. These
are also defined in aic79xx.h.
Remove unused ahd_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
aic7xxx.c:
aic79xx.c:
aic79xx.h:
aic7xxx.h:
aic7xxx_osm.c:
aic79xx_osm.c:
Move timeout handling to the driver cores. In the case
of the aic79xx driver, the algorithm has been enhanced
to try target resets before performing a bus reset. For
the aic7xxx driver, the algorithm is unchanged. Although
the drivers do not currently sleep during recovery (recovery
is timeout driven), the cores do expect all processing to
be performed via a recovery thread. Our timeout handlers
are now little stubs that wakeup the recovery thread.
aic79xx.c:
aic79xx.h:
aic79xx_inline.h:
Change shared_data allocation to use a map_node so
that the sentinel hscb can use this map node in
ahd_swap_with_next_hscb. This routine now swaps
the hscb_map pointer in additon to the hscb
contents so that any sync operations occur on
the correct map.
physaddr -> busaddr
Pointed out by: Jason Thorpe <thorpej@wasabisystems.com>
aic79xx.c:
Make more use of the in/out/w/l/q macros for accessing
byte registers in the chip.
Correct some issues in the ahd_flush_qoutfifo() routine.
o Run the qoutfifo only once the command channel
DMA engine has been halted. This closes a window
where we might have missed some entries.
o Change ahd_run_data_fifo() to not loop to completion.
If we happen to start on the wrong FIFO and the other
FIFO has a snapshot savepointers, we might deadlock.
This required our delay between FIFO tests to be
moved to the ahd_flush_qoutfifo() routine.
o Update/add comments.
o Remove spurious test for COMPLETE_DMA list being empty
when completing transactions from the GSFIFO with
residuals. The SCB must be put on the COMPLETE_DMA
scb list unconditionally.
o When halting command channel DMA activity, we must
disable the DMA channel in all cases but an update
of the QOUTFIFO. The latter case is required so
that the sequencer will update its position in the
QOUTFIFO. Previously, we left the channel enabled
for all "push" DMAs. This left us vulnerable to
the sequencer handling an SCB push long after that
SCB was already processed manually by this routine.
o Correct the polarity of tests involving
ahd_scb_active_in_fifo(). This routine returns
non-zero for true.
Return to processing bad status completions through
the qoutfifo. This reduces the time that the sequencer
is kept paused when handling transactions with bad
status or underruns.
When waiting for the controller to quiece selections,
add a delay to our loop. Otherwise we may fail to wait
long enough for the sequencer to comply.
On H2A4 hardware, use the slow slewrate for non-paced
transfers. This mirrors what the Adaptec Windows
drivers do.
On the Rev B. only slow down the CRC timing for
older U160 devices that might need the slower timing.
We define "older" as devices that do not support
packetized protocol.
Wait up to 5000 * 5us for the SEEPROM to become unbusy.
Write ops seem to take much longer than read ops.
aic79xx.seq:
For controllers with the FAINT_LED bug, turn the diagnostic
led feature on during selection and reselection. This covers
the non-packetized case. The LED will be disabled for
non-packetized transfers once we return to the top level idle
loop. Add more comments about the busy LED workaround.
Extend a critical section around the entire
command channel idle loop process. Previously
the portion of this handler that directly manipulated
the linked list of completed SCBs was not protected.
This is the likely cause of the recent reports of
commands being completed twice by the driver.
Extend critical sections across the test for,
and the longjump to, longjump routines. This
prevents the firmware from trying to jump to
a longjmp handler that was just cleared by the
host.
Improve the locations of several critical section
begin and end points. Typically these changes
remove instructions that did not need to be
inside a critical section.
Close the "busfree after selection, but before busfree
interrupts can be enabled" race to just a single sequencer
instruction. We now test the BSY line explicitly before
clearing the busfree status and enabling the busfree
interrupt.
Close a race condition in the processing of HS_MAILBOX
updates. We now clear the "updated" status before the
copy. This ensures that we don't accidentally clear
the status incorrectly when the host sneaks in an update
just after our last copy, but before we clear the status.
This race has never been observed.
Don't re-enable SCSIEN if we lose the race to disable SCSIEN
in our interrupt handler's workaround for the RevA data-valid
too early issue.
aic79xx_inline.h:
Add comments indicating that the order in which bytes are
read or written in ahd_inw and ahd_outw is important. This
allows us to use these inlines when accessing registers with
side-effects.
aic79xx_pci.c:
The 29320 and the 29320B are 7902 not 7901 based products.
Correct the driver banner.
aic7xxx.h:
Enable the use of the auto-access pause feature
on the aic7870 and aic7880. It was disabled due
to an oversight.
aic7xxx.reg:
Move TARG_IMMEDIATE_SCB to alias LAST_MSG to
avoid leaving garbage in MWI_RESIDUAL. This
prevents spurious overflows whn operating target
mode on controllers that require the MWI_RESIDUAL
work-around.
aic7xxx.seq:
AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag.
Reference the correct softc field when testing
for its presence.
Set the NOT_IDENTIFIED and NO_CDB_SENT bits
in SEQ_FLAGS to indicate that the nexus is
invalid in await busfree.
aic7xxx_93cx6.c:
Add support for the C56/C66 versions of the EWEN and EWDS
commands.
aic7xxx.c:
aic7xxx_pci.c:
Move test for the validity of left over BIOS data
to ahc_test_register_access(). This guarantees that
any left over CHIPRST value is not clobbered by our
register access test and lost to the test that was
in ahc_reset.
2003-12-17 00:02:10 +00:00
|
|
|
struct map_node shared_data_map;
|
2002-06-05 19:52:45 +00:00
|
|
|
|
|
|
|
|
/* Information saved through suspend/resume cycles */
|
|
|
|
|
struct ahd_suspend_state suspend_state;
|
|
|
|
|
|
|
|
|
|
/* Number of enabled target mode device on this card */
|
|
|
|
|
u_int enabled_luns;
|
|
|
|
|
|
|
|
|
|
/* Initialization level of this data structure */
|
|
|
|
|
u_int init_level;
|
|
|
|
|
|
|
|
|
|
/* PCI cacheline size. */
|
|
|
|
|
u_int pci_cachesize;
|
|
|
|
|
|
2002-12-01 08:13:37 +00:00
|
|
|
/* IO Cell Parameters */
|
|
|
|
|
uint8_t iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS];
|
|
|
|
|
|
|
|
|
|
u_int stack_size;
|
|
|
|
|
uint16_t *saved_stack;
|
|
|
|
|
|
2002-06-05 19:52:45 +00:00
|
|
|
/* Per-Unit descriptive information */
|
|
|
|
|
const char *description;
|
|
|
|
|
const char *bus_description;
|
|
|
|
|
char *name;
|
|
|
|
|
int unit;
|
|
|
|
|
|
|
|
|
|
/* Selection Timer settings */
|
|
|
|
|
int seltime;
|
|
|
|
|
|
aic79xx.c:
Implement the SCB_SILENT flag. This is useful for
hushing up the driver during DV or other operations
that we expect to cause transmission errors. The
messages will still print if the SHOW_MASKED_ERRORS
debug option is enabled.
Save and restore the NEGOADDR address when setting
new transfer settings. The sequencer performs lookups
in the negotiation table too and it expects NEGOADDR
to remain consistent across pause/unpause sessions.
Consistently use "offset" instead of "period" to determine
if we are running sync or not.
Add a SHOW_MESSAGES diagnostic for when we assert ATN
during message processing.
Print out IU, QAS, and RTI features when showing transfer options.
Limit the syncrate after all option conformance
changes have taken place in ahd_devlimited_syncrate.
Changes in options may change the final syncrate we
accept.
Keep a copy of the hs_mailbox in our softc so that
we can perform read/modify/write operations on the
hs_mailbox without having to pause the sequencer to
read the last written value. Use the ENINT_COALESS
flag in the hs_mailbox to toggle interrupt coalessing.
Add entrypoints for enabling interrupt coalessing and
setting both a timeout (how long to wait for commands
to be coalessed) and a maximum commands to coaless value.
Add a statistics timer that decides when to enable or
disable interrupt coalessing based on load.
Add a routine, ahd_reset_cmds_pending() which is used
to update the CMDS_PENDING sequencer variable whenever
error recovery compeltes SCBs without notifying the
sequencer. Since ahd_reset_cmds_pending is called
during ahd_unpause() only if we've aborted SCBs, its
call to ahd_flush_qoutfifo should not cause recursion
through ahd_run_qoutfifo(). A panic has been added to
ensure that this recursion does not occur.
In ahd_search_qinfifo, update the CMDS_PENDING sequencer
variable directly. ahd_search_qinififo can be called
in situations where using ahd_reset_cmds_pending() might
cause recursion. Since we can safely determine the
exact number to reduce CMDS_PENDING by in this scenario
without running the qoutfifo, the manual update is sufficient.
Clean up diagnostics.
Add ahd_flush_qoutfifo() which will run the qoutfifo
as well as complete any commands sitting on the
sequencer's COMPLETE_SCB lists or the good status FIFO.
Use this routine in several places that did similar
things in an add-hoc, but incomplete, fashion. A call
to this routine was also added to ahd_abort_scbs() to
close a race.
In ahd_pause_and_flushwork() only return once selections
are safely disabled. Flush all completed commands via
ahd_flush_qoutfifo().
Remove "Now packetized" diagnostic now that this
information is incorperated into the actual negotiation
messages that are displayed.
When forcing renegotiation, don't clober the current
ppr_options. Much of the driver uses this information
to determine if we are currently packetized or not.
Remove some stray spaces at column 1 in ahd_set_tags.
When complaining about getting a host message loop
request with no pending messages, print out the
SCB_CONTROL register down on the card.
Modify the ahd_sent_msg() routine to handle a search
for an outgoing identify message. Use this to detect
a msg reject on an identify message which typically
indicates that the target thought we were packetized.
Force a renegotiation in this case.
In ahd_search_qinfifo(), wait more effectively for SCB
DMA activities to cease. We also disable SCB fetch
operations since we are about to change the qinfifo
and any fetch in progress will likely be invalidated.
In ahd_qinfifo_count(), fix the qinfifo empty case.
In ahd_dump_card_state(), print out CCSCBCTL in the
correct mode.
If we are a narrow controller, don't set the current
width to unknown when forcing a future negotiation.
This just confuses the code into attempting a wide
negotiation on a narrow bus.
Add support for task management function completions.
Modify ahd_handle_devreset so that it can handle
lun resets in addition to target resets. Use
ahd_handle_devreset for lun and target reset task
management functions.
Handle the abort task TMF race case better. We now
wait until any current selections are over and then
set the TMF back to zero. This should cause the sequencer
to ignore the abort TMF completion should it occur.
Correct a bug in the illegal phase handler that
caused us to drop down to narrow when handling the
unexpected command phase case after 3rd party
reset of a packetized device.
Indicate the features, bugs, and flags set in the softc
that are used to control firmware patch download when
booting verbose.
aic79xx.h:
Add coalessing and HS_MAILBOX fields.
Add per-softc variables for the stats "daemon".
Add a debug option for interrupt coalessing activities.
Add two new softc flags:
o AHD_UPDATE_PEND_CMDS
Run ahd_reset_cmds_pending() on the next unpause.
o AHD_RUNNING_QOUTFIFO
Used to catch recursion through ahd_run_qoutfifo().
aic79xx.reg:
Correct register addresses related to the software timer
and the DFDBCTL register.
Add constants paramaterizing the software timer.
Add scratch ram locations for storing interrupt coalessing
tunables.
Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2.
In at least the REV A, these are writable bits. We make
use of that for a swtimer workaround in the sequencer.
Since HS_MAILBOX autoclears, provide a sequencer variable
to store its contents.
Add SEQINT codes for handling task management completions.
aic79xx.seq:
Correct ignore wide residue processing check for
a wide negotiation being in effect. We must be
in the SCSI register window in order to access the
negotiation table.
Use the software timer and a commands completed count to
implement interrupt coalessing. The command complete is
deferred until either the maximum command threshold or a
the expiration of a command deferral timer. If we have
more SCBs to complete to the host (sitting in COMPLETE_SCB
lists), always try to coaless them up to our coalessing limit.
If coalessing is enabled, but we have fewer commands oustanting
than the host's min coalessing limit, complete the command
immediately.
Add code to track the number of commands outstanding.
Commands are outstanding from the time they are placed
into the execution queue until the DMA to post completion
is setup.
Add a workaround for intvec_2 interrupts on the H2A4.
In H2A4, the mode pointer is not saved for intvec2, but
is restored on iret. This can lead to the restoration
of a bogus mode ptr. Manually clear the intmask bits and
do a normal return to compensate. We use intvec_2 to
track interrupt coalessing timeouts.
Since we cannot disable the swtimer's countdown, simply
mask its interrupt once we no longer care about it firing.
In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime
we are notified of an HS_MAILBOX update via the
HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a
local copy of persistant portions of the HS_MAILBOX as
the mailbox auto-clears on any read.
Move the test for the cfg4istat interrupt up an instruction
to hopefully close a race between the next outgoing selection
and our disabling of selections.
Add a missing ret to the last instruction in load_overrun_buf.
Add notifications to the host of task management
completions as well as the completions for commands
that completed successfully before their corresponding
TMF could be sent.
Hold a critical section during select-out processing
until we have a fully identified connection. This
removes a race condition with the legacy abort handler.
Correct a few spelling errors in some comments.
aic79xx_inline.h:
Call ahd_reset_cmds_pending() in ahd_unpause if required.
Update cmdcmplt interrupt statistics in our interrupt
handler.
Allow callers to ahd_send_scb() to set the task management
function.
aic79xx_pci.c:
Disable SERR and pause the controller prior to performing
our mmapped I/O test. The U320 controllers do not support
"auto-access-pause".
aic79xx_osm.c:
Set the task management function now that
ahd_send_scb() doesn't do it for us. We
also perform a lun reset in response to BDR
requests to packetized devices.
2003-01-20 20:17:35 +00:00
|
|
|
/*
|
2003-05-26 21:10:58 +00:00
|
|
|
* Interrupt coalescing settings.
|
aic79xx.c:
Implement the SCB_SILENT flag. This is useful for
hushing up the driver during DV or other operations
that we expect to cause transmission errors. The
messages will still print if the SHOW_MASKED_ERRORS
debug option is enabled.
Save and restore the NEGOADDR address when setting
new transfer settings. The sequencer performs lookups
in the negotiation table too and it expects NEGOADDR
to remain consistent across pause/unpause sessions.
Consistently use "offset" instead of "period" to determine
if we are running sync or not.
Add a SHOW_MESSAGES diagnostic for when we assert ATN
during message processing.
Print out IU, QAS, and RTI features when showing transfer options.
Limit the syncrate after all option conformance
changes have taken place in ahd_devlimited_syncrate.
Changes in options may change the final syncrate we
accept.
Keep a copy of the hs_mailbox in our softc so that
we can perform read/modify/write operations on the
hs_mailbox without having to pause the sequencer to
read the last written value. Use the ENINT_COALESS
flag in the hs_mailbox to toggle interrupt coalessing.
Add entrypoints for enabling interrupt coalessing and
setting both a timeout (how long to wait for commands
to be coalessed) and a maximum commands to coaless value.
Add a statistics timer that decides when to enable or
disable interrupt coalessing based on load.
Add a routine, ahd_reset_cmds_pending() which is used
to update the CMDS_PENDING sequencer variable whenever
error recovery compeltes SCBs without notifying the
sequencer. Since ahd_reset_cmds_pending is called
during ahd_unpause() only if we've aborted SCBs, its
call to ahd_flush_qoutfifo should not cause recursion
through ahd_run_qoutfifo(). A panic has been added to
ensure that this recursion does not occur.
In ahd_search_qinfifo, update the CMDS_PENDING sequencer
variable directly. ahd_search_qinififo can be called
in situations where using ahd_reset_cmds_pending() might
cause recursion. Since we can safely determine the
exact number to reduce CMDS_PENDING by in this scenario
without running the qoutfifo, the manual update is sufficient.
Clean up diagnostics.
Add ahd_flush_qoutfifo() which will run the qoutfifo
as well as complete any commands sitting on the
sequencer's COMPLETE_SCB lists or the good status FIFO.
Use this routine in several places that did similar
things in an add-hoc, but incomplete, fashion. A call
to this routine was also added to ahd_abort_scbs() to
close a race.
In ahd_pause_and_flushwork() only return once selections
are safely disabled. Flush all completed commands via
ahd_flush_qoutfifo().
Remove "Now packetized" diagnostic now that this
information is incorperated into the actual negotiation
messages that are displayed.
When forcing renegotiation, don't clober the current
ppr_options. Much of the driver uses this information
to determine if we are currently packetized or not.
Remove some stray spaces at column 1 in ahd_set_tags.
When complaining about getting a host message loop
request with no pending messages, print out the
SCB_CONTROL register down on the card.
Modify the ahd_sent_msg() routine to handle a search
for an outgoing identify message. Use this to detect
a msg reject on an identify message which typically
indicates that the target thought we were packetized.
Force a renegotiation in this case.
In ahd_search_qinfifo(), wait more effectively for SCB
DMA activities to cease. We also disable SCB fetch
operations since we are about to change the qinfifo
and any fetch in progress will likely be invalidated.
In ahd_qinfifo_count(), fix the qinfifo empty case.
In ahd_dump_card_state(), print out CCSCBCTL in the
correct mode.
If we are a narrow controller, don't set the current
width to unknown when forcing a future negotiation.
This just confuses the code into attempting a wide
negotiation on a narrow bus.
Add support for task management function completions.
Modify ahd_handle_devreset so that it can handle
lun resets in addition to target resets. Use
ahd_handle_devreset for lun and target reset task
management functions.
Handle the abort task TMF race case better. We now
wait until any current selections are over and then
set the TMF back to zero. This should cause the sequencer
to ignore the abort TMF completion should it occur.
Correct a bug in the illegal phase handler that
caused us to drop down to narrow when handling the
unexpected command phase case after 3rd party
reset of a packetized device.
Indicate the features, bugs, and flags set in the softc
that are used to control firmware patch download when
booting verbose.
aic79xx.h:
Add coalessing and HS_MAILBOX fields.
Add per-softc variables for the stats "daemon".
Add a debug option for interrupt coalessing activities.
Add two new softc flags:
o AHD_UPDATE_PEND_CMDS
Run ahd_reset_cmds_pending() on the next unpause.
o AHD_RUNNING_QOUTFIFO
Used to catch recursion through ahd_run_qoutfifo().
aic79xx.reg:
Correct register addresses related to the software timer
and the DFDBCTL register.
Add constants paramaterizing the software timer.
Add scratch ram locations for storing interrupt coalessing
tunables.
Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2.
In at least the REV A, these are writable bits. We make
use of that for a swtimer workaround in the sequencer.
Since HS_MAILBOX autoclears, provide a sequencer variable
to store its contents.
Add SEQINT codes for handling task management completions.
aic79xx.seq:
Correct ignore wide residue processing check for
a wide negotiation being in effect. We must be
in the SCSI register window in order to access the
negotiation table.
Use the software timer and a commands completed count to
implement interrupt coalessing. The command complete is
deferred until either the maximum command threshold or a
the expiration of a command deferral timer. If we have
more SCBs to complete to the host (sitting in COMPLETE_SCB
lists), always try to coaless them up to our coalessing limit.
If coalessing is enabled, but we have fewer commands oustanting
than the host's min coalessing limit, complete the command
immediately.
Add code to track the number of commands outstanding.
Commands are outstanding from the time they are placed
into the execution queue until the DMA to post completion
is setup.
Add a workaround for intvec_2 interrupts on the H2A4.
In H2A4, the mode pointer is not saved for intvec2, but
is restored on iret. This can lead to the restoration
of a bogus mode ptr. Manually clear the intmask bits and
do a normal return to compensate. We use intvec_2 to
track interrupt coalessing timeouts.
Since we cannot disable the swtimer's countdown, simply
mask its interrupt once we no longer care about it firing.
In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime
we are notified of an HS_MAILBOX update via the
HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a
local copy of persistant portions of the HS_MAILBOX as
the mailbox auto-clears on any read.
Move the test for the cfg4istat interrupt up an instruction
to hopefully close a race between the next outgoing selection
and our disabling of selections.
Add a missing ret to the last instruction in load_overrun_buf.
Add notifications to the host of task management
completions as well as the completions for commands
that completed successfully before their corresponding
TMF could be sent.
Hold a critical section during select-out processing
until we have a fully identified connection. This
removes a race condition with the legacy abort handler.
Correct a few spelling errors in some comments.
aic79xx_inline.h:
Call ahd_reset_cmds_pending() in ahd_unpause if required.
Update cmdcmplt interrupt statistics in our interrupt
handler.
Allow callers to ahd_send_scb() to set the task management
function.
aic79xx_pci.c:
Disable SERR and pause the controller prior to performing
our mmapped I/O test. The U320 controllers do not support
"auto-access-pause".
aic79xx_osm.c:
Set the task management function now that
ahd_send_scb() doesn't do it for us. We
also perform a lun reset in response to BDR
requests to packetized devices.
2003-01-20 20:17:35 +00:00
|
|
|
*/
|
2003-05-26 21:10:58 +00:00
|
|
|
#define AHD_INT_COALESCING_TIMER_DEFAULT 250 /*us*/
|
|
|
|
|
#define AHD_INT_COALESCING_MAXCMDS_DEFAULT 10
|
|
|
|
|
#define AHD_INT_COALESCING_MAXCMDS_MAX 127
|
|
|
|
|
#define AHD_INT_COALESCING_MINCMDS_DEFAULT 5
|
|
|
|
|
#define AHD_INT_COALESCING_MINCMDS_MAX 127
|
|
|
|
|
#define AHD_INT_COALESCING_THRESHOLD_DEFAULT 2000
|
|
|
|
|
#define AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT 1000
|
|
|
|
|
u_int int_coalescing_timer;
|
|
|
|
|
u_int int_coalescing_maxcmds;
|
|
|
|
|
u_int int_coalescing_mincmds;
|
|
|
|
|
u_int int_coalescing_threshold;
|
|
|
|
|
u_int int_coalescing_stop_threshold;
|
aic79xx.c:
Implement the SCB_SILENT flag. This is useful for
hushing up the driver during DV or other operations
that we expect to cause transmission errors. The
messages will still print if the SHOW_MASKED_ERRORS
debug option is enabled.
Save and restore the NEGOADDR address when setting
new transfer settings. The sequencer performs lookups
in the negotiation table too and it expects NEGOADDR
to remain consistent across pause/unpause sessions.
Consistently use "offset" instead of "period" to determine
if we are running sync or not.
Add a SHOW_MESSAGES diagnostic for when we assert ATN
during message processing.
Print out IU, QAS, and RTI features when showing transfer options.
Limit the syncrate after all option conformance
changes have taken place in ahd_devlimited_syncrate.
Changes in options may change the final syncrate we
accept.
Keep a copy of the hs_mailbox in our softc so that
we can perform read/modify/write operations on the
hs_mailbox without having to pause the sequencer to
read the last written value. Use the ENINT_COALESS
flag in the hs_mailbox to toggle interrupt coalessing.
Add entrypoints for enabling interrupt coalessing and
setting both a timeout (how long to wait for commands
to be coalessed) and a maximum commands to coaless value.
Add a statistics timer that decides when to enable or
disable interrupt coalessing based on load.
Add a routine, ahd_reset_cmds_pending() which is used
to update the CMDS_PENDING sequencer variable whenever
error recovery compeltes SCBs without notifying the
sequencer. Since ahd_reset_cmds_pending is called
during ahd_unpause() only if we've aborted SCBs, its
call to ahd_flush_qoutfifo should not cause recursion
through ahd_run_qoutfifo(). A panic has been added to
ensure that this recursion does not occur.
In ahd_search_qinfifo, update the CMDS_PENDING sequencer
variable directly. ahd_search_qinififo can be called
in situations where using ahd_reset_cmds_pending() might
cause recursion. Since we can safely determine the
exact number to reduce CMDS_PENDING by in this scenario
without running the qoutfifo, the manual update is sufficient.
Clean up diagnostics.
Add ahd_flush_qoutfifo() which will run the qoutfifo
as well as complete any commands sitting on the
sequencer's COMPLETE_SCB lists or the good status FIFO.
Use this routine in several places that did similar
things in an add-hoc, but incomplete, fashion. A call
to this routine was also added to ahd_abort_scbs() to
close a race.
In ahd_pause_and_flushwork() only return once selections
are safely disabled. Flush all completed commands via
ahd_flush_qoutfifo().
Remove "Now packetized" diagnostic now that this
information is incorperated into the actual negotiation
messages that are displayed.
When forcing renegotiation, don't clober the current
ppr_options. Much of the driver uses this information
to determine if we are currently packetized or not.
Remove some stray spaces at column 1 in ahd_set_tags.
When complaining about getting a host message loop
request with no pending messages, print out the
SCB_CONTROL register down on the card.
Modify the ahd_sent_msg() routine to handle a search
for an outgoing identify message. Use this to detect
a msg reject on an identify message which typically
indicates that the target thought we were packetized.
Force a renegotiation in this case.
In ahd_search_qinfifo(), wait more effectively for SCB
DMA activities to cease. We also disable SCB fetch
operations since we are about to change the qinfifo
and any fetch in progress will likely be invalidated.
In ahd_qinfifo_count(), fix the qinfifo empty case.
In ahd_dump_card_state(), print out CCSCBCTL in the
correct mode.
If we are a narrow controller, don't set the current
width to unknown when forcing a future negotiation.
This just confuses the code into attempting a wide
negotiation on a narrow bus.
Add support for task management function completions.
Modify ahd_handle_devreset so that it can handle
lun resets in addition to target resets. Use
ahd_handle_devreset for lun and target reset task
management functions.
Handle the abort task TMF race case better. We now
wait until any current selections are over and then
set the TMF back to zero. This should cause the sequencer
to ignore the abort TMF completion should it occur.
Correct a bug in the illegal phase handler that
caused us to drop down to narrow when handling the
unexpected command phase case after 3rd party
reset of a packetized device.
Indicate the features, bugs, and flags set in the softc
that are used to control firmware patch download when
booting verbose.
aic79xx.h:
Add coalessing and HS_MAILBOX fields.
Add per-softc variables for the stats "daemon".
Add a debug option for interrupt coalessing activities.
Add two new softc flags:
o AHD_UPDATE_PEND_CMDS
Run ahd_reset_cmds_pending() on the next unpause.
o AHD_RUNNING_QOUTFIFO
Used to catch recursion through ahd_run_qoutfifo().
aic79xx.reg:
Correct register addresses related to the software timer
and the DFDBCTL register.
Add constants paramaterizing the software timer.
Add scratch ram locations for storing interrupt coalessing
tunables.
Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2.
In at least the REV A, these are writable bits. We make
use of that for a swtimer workaround in the sequencer.
Since HS_MAILBOX autoclears, provide a sequencer variable
to store its contents.
Add SEQINT codes for handling task management completions.
aic79xx.seq:
Correct ignore wide residue processing check for
a wide negotiation being in effect. We must be
in the SCSI register window in order to access the
negotiation table.
Use the software timer and a commands completed count to
implement interrupt coalessing. The command complete is
deferred until either the maximum command threshold or a
the expiration of a command deferral timer. If we have
more SCBs to complete to the host (sitting in COMPLETE_SCB
lists), always try to coaless them up to our coalessing limit.
If coalessing is enabled, but we have fewer commands oustanting
than the host's min coalessing limit, complete the command
immediately.
Add code to track the number of commands outstanding.
Commands are outstanding from the time they are placed
into the execution queue until the DMA to post completion
is setup.
Add a workaround for intvec_2 interrupts on the H2A4.
In H2A4, the mode pointer is not saved for intvec2, but
is restored on iret. This can lead to the restoration
of a bogus mode ptr. Manually clear the intmask bits and
do a normal return to compensate. We use intvec_2 to
track interrupt coalessing timeouts.
Since we cannot disable the swtimer's countdown, simply
mask its interrupt once we no longer care about it firing.
In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime
we are notified of an HS_MAILBOX update via the
HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a
local copy of persistant portions of the HS_MAILBOX as
the mailbox auto-clears on any read.
Move the test for the cfg4istat interrupt up an instruction
to hopefully close a race between the next outgoing selection
and our disabling of selections.
Add a missing ret to the last instruction in load_overrun_buf.
Add notifications to the host of task management
completions as well as the completions for commands
that completed successfully before their corresponding
TMF could be sent.
Hold a critical section during select-out processing
until we have a fully identified connection. This
removes a race condition with the legacy abort handler.
Correct a few spelling errors in some comments.
aic79xx_inline.h:
Call ahd_reset_cmds_pending() in ahd_unpause if required.
Update cmdcmplt interrupt statistics in our interrupt
handler.
Allow callers to ahd_send_scb() to set the task management
function.
aic79xx_pci.c:
Disable SERR and pause the controller prior to performing
our mmapped I/O test. The U320 controllers do not support
"auto-access-pause".
aic79xx_osm.c:
Set the task management function now that
ahd_send_scb() doesn't do it for us. We
also perform a lun reset in response to BDR
requests to packetized devices.
2003-01-20 20:17:35 +00:00
|
|
|
|
2002-06-05 19:52:45 +00:00
|
|
|
uint16_t user_discenable;/* Disconnection allowed */
|
|
|
|
|
uint16_t user_tagenable;/* Tagged Queuing allowed */
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
TAILQ_HEAD(ahd_softc_tailq, ahd_softc);
|
|
|
|
|
extern struct ahd_softc_tailq ahd_tailq;
|
|
|
|
|
|
2002-12-01 08:13:37 +00:00
|
|
|
/*************************** IO Cell Configuration ****************************/
|
|
|
|
|
#define AHD_PRECOMP_SLEW_INDEX \
|
|
|
|
|
(AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0)
|
|
|
|
|
|
|
|
|
|
#define AHD_AMPLITUDE_INDEX \
|
|
|
|
|
(AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0)
|
|
|
|
|
|
|
|
|
|
#define AHD_SET_SLEWRATE(ahd, new_slew) \
|
|
|
|
|
do { \
|
|
|
|
|
(ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_SLEWRATE_MASK; \
|
|
|
|
|
(ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \
|
|
|
|
|
(((new_slew) << AHD_SLEWRATE_SHIFT) & AHD_SLEWRATE_MASK); \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
|
|
#define AHD_SET_PRECOMP(ahd, new_pcomp) \
|
|
|
|
|
do { \
|
|
|
|
|
(ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; \
|
|
|
|
|
(ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \
|
|
|
|
|
(((new_pcomp) << AHD_PRECOMP_SHIFT) & AHD_PRECOMP_MASK); \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
|
|
#define AHD_SET_AMPLITUDE(ahd, new_amp) \
|
|
|
|
|
do { \
|
|
|
|
|
(ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] &= ~AHD_AMPLITUDE_MASK; \
|
|
|
|
|
(ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] |= \
|
|
|
|
|
(((new_amp) << AHD_AMPLITUDE_SHIFT) & AHD_AMPLITUDE_MASK); \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
2002-06-05 19:52:45 +00:00
|
|
|
/************************ Active Device Information ***************************/
|
|
|
|
|
typedef enum {
|
|
|
|
|
ROLE_UNKNOWN,
|
|
|
|
|
ROLE_INITIATOR,
|
|
|
|
|
ROLE_TARGET
|
|
|
|
|
} role_t;
|
|
|
|
|
|
|
|
|
|
struct ahd_devinfo {
|
|
|
|
|
int our_scsiid;
|
|
|
|
|
int target_offset;
|
|
|
|
|
uint16_t target_mask;
|
|
|
|
|
u_int target;
|
|
|
|
|
u_int lun;
|
|
|
|
|
char channel;
|
|
|
|
|
role_t role; /*
|
|
|
|
|
* Only guaranteed to be correct if not
|
|
|
|
|
* in the busfree state.
|
|
|
|
|
*/
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/****************************** PCI Structures ********************************/
|
2003-09-02 17:30:40 +00:00
|
|
|
#define AHD_PCI_IOADDR0 PCIR_BAR(0) /* I/O BAR*/
|
|
|
|
|
#define AHD_PCI_MEMADDR PCIR_BAR(1) /* Memory BAR */
|
|
|
|
|
#define AHD_PCI_IOADDR1 PCIR_BAR(3) /* Second I/O BAR */
|
2002-06-05 19:52:45 +00:00
|
|
|
|
|
|
|
|
typedef int (ahd_device_setup_t)(struct ahd_softc *);
|
|
|
|
|
|
|
|
|
|
struct ahd_pci_identity {
|
|
|
|
|
uint64_t full_id;
|
|
|
|
|
uint64_t id_mask;
|
|
|
|
|
char *name;
|
|
|
|
|
ahd_device_setup_t *setup;
|
|
|
|
|
};
|
|
|
|
|
extern struct ahd_pci_identity ahd_pci_ident_table [];
|
|
|
|
|
extern const u_int ahd_num_pci_devs;
|
|
|
|
|
|
|
|
|
|
/***************************** VL/EISA Declarations ***************************/
|
|
|
|
|
struct aic7770_identity {
|
|
|
|
|
uint32_t full_id;
|
|
|
|
|
uint32_t id_mask;
|
|
|
|
|
char *name;
|
|
|
|
|
ahd_device_setup_t *setup;
|
|
|
|
|
};
|
|
|
|
|
extern struct aic7770_identity aic7770_ident_table [];
|
|
|
|
|
extern const int ahd_num_aic7770_devs;
|
|
|
|
|
|
|
|
|
|
#define AHD_EISA_SLOT_OFFSET 0xc00
|
|
|
|
|
#define AHD_EISA_IOSIZE 0x100
|
|
|
|
|
|
|
|
|
|
/*************************** Function Declarations ****************************/
|
|
|
|
|
/******************************************************************************/
|
aic79xx.c:
Implement the SCB_SILENT flag. This is useful for
hushing up the driver during DV or other operations
that we expect to cause transmission errors. The
messages will still print if the SHOW_MASKED_ERRORS
debug option is enabled.
Save and restore the NEGOADDR address when setting
new transfer settings. The sequencer performs lookups
in the negotiation table too and it expects NEGOADDR
to remain consistent across pause/unpause sessions.
Consistently use "offset" instead of "period" to determine
if we are running sync or not.
Add a SHOW_MESSAGES diagnostic for when we assert ATN
during message processing.
Print out IU, QAS, and RTI features when showing transfer options.
Limit the syncrate after all option conformance
changes have taken place in ahd_devlimited_syncrate.
Changes in options may change the final syncrate we
accept.
Keep a copy of the hs_mailbox in our softc so that
we can perform read/modify/write operations on the
hs_mailbox without having to pause the sequencer to
read the last written value. Use the ENINT_COALESS
flag in the hs_mailbox to toggle interrupt coalessing.
Add entrypoints for enabling interrupt coalessing and
setting both a timeout (how long to wait for commands
to be coalessed) and a maximum commands to coaless value.
Add a statistics timer that decides when to enable or
disable interrupt coalessing based on load.
Add a routine, ahd_reset_cmds_pending() which is used
to update the CMDS_PENDING sequencer variable whenever
error recovery compeltes SCBs without notifying the
sequencer. Since ahd_reset_cmds_pending is called
during ahd_unpause() only if we've aborted SCBs, its
call to ahd_flush_qoutfifo should not cause recursion
through ahd_run_qoutfifo(). A panic has been added to
ensure that this recursion does not occur.
In ahd_search_qinfifo, update the CMDS_PENDING sequencer
variable directly. ahd_search_qinififo can be called
in situations where using ahd_reset_cmds_pending() might
cause recursion. Since we can safely determine the
exact number to reduce CMDS_PENDING by in this scenario
without running the qoutfifo, the manual update is sufficient.
Clean up diagnostics.
Add ahd_flush_qoutfifo() which will run the qoutfifo
as well as complete any commands sitting on the
sequencer's COMPLETE_SCB lists or the good status FIFO.
Use this routine in several places that did similar
things in an add-hoc, but incomplete, fashion. A call
to this routine was also added to ahd_abort_scbs() to
close a race.
In ahd_pause_and_flushwork() only return once selections
are safely disabled. Flush all completed commands via
ahd_flush_qoutfifo().
Remove "Now packetized" diagnostic now that this
information is incorperated into the actual negotiation
messages that are displayed.
When forcing renegotiation, don't clober the current
ppr_options. Much of the driver uses this information
to determine if we are currently packetized or not.
Remove some stray spaces at column 1 in ahd_set_tags.
When complaining about getting a host message loop
request with no pending messages, print out the
SCB_CONTROL register down on the card.
Modify the ahd_sent_msg() routine to handle a search
for an outgoing identify message. Use this to detect
a msg reject on an identify message which typically
indicates that the target thought we were packetized.
Force a renegotiation in this case.
In ahd_search_qinfifo(), wait more effectively for SCB
DMA activities to cease. We also disable SCB fetch
operations since we are about to change the qinfifo
and any fetch in progress will likely be invalidated.
In ahd_qinfifo_count(), fix the qinfifo empty case.
In ahd_dump_card_state(), print out CCSCBCTL in the
correct mode.
If we are a narrow controller, don't set the current
width to unknown when forcing a future negotiation.
This just confuses the code into attempting a wide
negotiation on a narrow bus.
Add support for task management function completions.
Modify ahd_handle_devreset so that it can handle
lun resets in addition to target resets. Use
ahd_handle_devreset for lun and target reset task
management functions.
Handle the abort task TMF race case better. We now
wait until any current selections are over and then
set the TMF back to zero. This should cause the sequencer
to ignore the abort TMF completion should it occur.
Correct a bug in the illegal phase handler that
caused us to drop down to narrow when handling the
unexpected command phase case after 3rd party
reset of a packetized device.
Indicate the features, bugs, and flags set in the softc
that are used to control firmware patch download when
booting verbose.
aic79xx.h:
Add coalessing and HS_MAILBOX fields.
Add per-softc variables for the stats "daemon".
Add a debug option for interrupt coalessing activities.
Add two new softc flags:
o AHD_UPDATE_PEND_CMDS
Run ahd_reset_cmds_pending() on the next unpause.
o AHD_RUNNING_QOUTFIFO
Used to catch recursion through ahd_run_qoutfifo().
aic79xx.reg:
Correct register addresses related to the software timer
and the DFDBCTL register.
Add constants paramaterizing the software timer.
Add scratch ram locations for storing interrupt coalessing
tunables.
Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2.
In at least the REV A, these are writable bits. We make
use of that for a swtimer workaround in the sequencer.
Since HS_MAILBOX autoclears, provide a sequencer variable
to store its contents.
Add SEQINT codes for handling task management completions.
aic79xx.seq:
Correct ignore wide residue processing check for
a wide negotiation being in effect. We must be
in the SCSI register window in order to access the
negotiation table.
Use the software timer and a commands completed count to
implement interrupt coalessing. The command complete is
deferred until either the maximum command threshold or a
the expiration of a command deferral timer. If we have
more SCBs to complete to the host (sitting in COMPLETE_SCB
lists), always try to coaless them up to our coalessing limit.
If coalessing is enabled, but we have fewer commands oustanting
than the host's min coalessing limit, complete the command
immediately.
Add code to track the number of commands outstanding.
Commands are outstanding from the time they are placed
into the execution queue until the DMA to post completion
is setup.
Add a workaround for intvec_2 interrupts on the H2A4.
In H2A4, the mode pointer is not saved for intvec2, but
is restored on iret. This can lead to the restoration
of a bogus mode ptr. Manually clear the intmask bits and
do a normal return to compensate. We use intvec_2 to
track interrupt coalessing timeouts.
Since we cannot disable the swtimer's countdown, simply
mask its interrupt once we no longer care about it firing.
In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime
we are notified of an HS_MAILBOX update via the
HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a
local copy of persistant portions of the HS_MAILBOX as
the mailbox auto-clears on any read.
Move the test for the cfg4istat interrupt up an instruction
to hopefully close a race between the next outgoing selection
and our disabling of selections.
Add a missing ret to the last instruction in load_overrun_buf.
Add notifications to the host of task management
completions as well as the completions for commands
that completed successfully before their corresponding
TMF could be sent.
Hold a critical section during select-out processing
until we have a fully identified connection. This
removes a race condition with the legacy abort handler.
Correct a few spelling errors in some comments.
aic79xx_inline.h:
Call ahd_reset_cmds_pending() in ahd_unpause if required.
Update cmdcmplt interrupt statistics in our interrupt
handler.
Allow callers to ahd_send_scb() to set the task management
function.
aic79xx_pci.c:
Disable SERR and pause the controller prior to performing
our mmapped I/O test. The U320 controllers do not support
"auto-access-pause".
aic79xx_osm.c:
Set the task management function now that
ahd_send_scb() doesn't do it for us. We
also perform a lun reset in response to BDR
requests to packetized devices.
2003-01-20 20:17:35 +00:00
|
|
|
void ahd_reset_cmds_pending(struct ahd_softc *ahd);
|
2002-06-05 19:52:45 +00:00
|
|
|
u_int ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl);
|
|
|
|
|
void ahd_busy_tcl(struct ahd_softc *ahd,
|
|
|
|
|
u_int tcl, u_int busyid);
|
|
|
|
|
static __inline void ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl);
|
|
|
|
|
static __inline void
|
|
|
|
|
ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl)
|
|
|
|
|
{
|
|
|
|
|
ahd_busy_tcl(ahd, tcl, SCB_LIST_NULL);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/***************************** PCI Front End *********************************/
|
ahc_eisa.c:
ahc_pci.c:
ahd_pci.c:
aic7xxx.c:
aic79xx.c:
aic_osm_lib.c:
aic_osm_lib.h:
Use common OSM routines from aic_osm_lib for bus dma operations,
delay routines, accessing CCBs, byte swapping, etc.
aic7xxx_pci.c:
Provide a better description for the 2915/30LP on attach.
aic7xxx.c:
aic79xx.c:
aic7770.c:
aic79xx_pci.c:
aic7xxx_pci.c:
aic7xxx_93cx6.c:
Move FBSDID behind an ifdef so that these core files will
still compile under other OSes.
aic79xx.h:
aic79xx_pci.c:
aic79xx.seq:
To speed up non-packetized CDB delivery in Rev B, all CDB
acks are "released" to the output sync as soon as the
command phase starts. There is only one problem with this
approach. If the target changes phase before all data are
sent, we have left over acks that can go out on the bus in
a data phase. Due to other chip contraints, this only
happens if the target goes to data-in, but if the acks go
out before we can test SDONE, we'll think that the transfer
has completed successfully. Work around this by taking
advantage of the 400ns or 800ns dead time between command
phase and the REQ of the new phase. If the transfer has
completed successfully, SCSIEN should fall *long* before we
see a phase change. We thus treat any phasemiss that
occurs before SCSIEN falls as an incomplete transfer.
aic79xx.h:
Add the AHD_FAST_CDB_DELIVERY feature.
aic79xx_pci.c:
Set AHD_FAST_CDB_DELIVERY for all Rev. B parts.
aic79xx.seq:
Test for PHASEMIS in the command phase for
all AHD_FAST_CDB_DELIVERY controlelrs.
ahd_pci.c:
ahc_pci.c:
aic7xxx.h:
aic79xx.h:
Move definition of controller BAR offsets to core header files.
aic7xxx.c:
aic79xx.c:
In the softc free routine, leave removal of a softc from the
global list of softcs to the OSM (the caller of this routine).
This allows us to avoid holding the softc list_lock during device
destruction where we may have to sleep waiting for our recovery
thread to halt.
ahc_pci.c:
Use ahc_pci_test_register access to validate I/O mapped in
addition to the tests already performed for memory mapped
access.
Remove unused ahc_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
ahd_pci.c:
Remove reduntant definition of controller BAR offsets. These
are also defined in aic79xx.h.
Remove unused ahd_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
aic7xxx.c:
aic79xx.c:
aic79xx.h:
aic7xxx.h:
aic7xxx_osm.c:
aic79xx_osm.c:
Move timeout handling to the driver cores. In the case
of the aic79xx driver, the algorithm has been enhanced
to try target resets before performing a bus reset. For
the aic7xxx driver, the algorithm is unchanged. Although
the drivers do not currently sleep during recovery (recovery
is timeout driven), the cores do expect all processing to
be performed via a recovery thread. Our timeout handlers
are now little stubs that wakeup the recovery thread.
aic79xx.c:
aic79xx.h:
aic79xx_inline.h:
Change shared_data allocation to use a map_node so
that the sentinel hscb can use this map node in
ahd_swap_with_next_hscb. This routine now swaps
the hscb_map pointer in additon to the hscb
contents so that any sync operations occur on
the correct map.
physaddr -> busaddr
Pointed out by: Jason Thorpe <thorpej@wasabisystems.com>
aic79xx.c:
Make more use of the in/out/w/l/q macros for accessing
byte registers in the chip.
Correct some issues in the ahd_flush_qoutfifo() routine.
o Run the qoutfifo only once the command channel
DMA engine has been halted. This closes a window
where we might have missed some entries.
o Change ahd_run_data_fifo() to not loop to completion.
If we happen to start on the wrong FIFO and the other
FIFO has a snapshot savepointers, we might deadlock.
This required our delay between FIFO tests to be
moved to the ahd_flush_qoutfifo() routine.
o Update/add comments.
o Remove spurious test for COMPLETE_DMA list being empty
when completing transactions from the GSFIFO with
residuals. The SCB must be put on the COMPLETE_DMA
scb list unconditionally.
o When halting command channel DMA activity, we must
disable the DMA channel in all cases but an update
of the QOUTFIFO. The latter case is required so
that the sequencer will update its position in the
QOUTFIFO. Previously, we left the channel enabled
for all "push" DMAs. This left us vulnerable to
the sequencer handling an SCB push long after that
SCB was already processed manually by this routine.
o Correct the polarity of tests involving
ahd_scb_active_in_fifo(). This routine returns
non-zero for true.
Return to processing bad status completions through
the qoutfifo. This reduces the time that the sequencer
is kept paused when handling transactions with bad
status or underruns.
When waiting for the controller to quiece selections,
add a delay to our loop. Otherwise we may fail to wait
long enough for the sequencer to comply.
On H2A4 hardware, use the slow slewrate for non-paced
transfers. This mirrors what the Adaptec Windows
drivers do.
On the Rev B. only slow down the CRC timing for
older U160 devices that might need the slower timing.
We define "older" as devices that do not support
packetized protocol.
Wait up to 5000 * 5us for the SEEPROM to become unbusy.
Write ops seem to take much longer than read ops.
aic79xx.seq:
For controllers with the FAINT_LED bug, turn the diagnostic
led feature on during selection and reselection. This covers
the non-packetized case. The LED will be disabled for
non-packetized transfers once we return to the top level idle
loop. Add more comments about the busy LED workaround.
Extend a critical section around the entire
command channel idle loop process. Previously
the portion of this handler that directly manipulated
the linked list of completed SCBs was not protected.
This is the likely cause of the recent reports of
commands being completed twice by the driver.
Extend critical sections across the test for,
and the longjump to, longjump routines. This
prevents the firmware from trying to jump to
a longjmp handler that was just cleared by the
host.
Improve the locations of several critical section
begin and end points. Typically these changes
remove instructions that did not need to be
inside a critical section.
Close the "busfree after selection, but before busfree
interrupts can be enabled" race to just a single sequencer
instruction. We now test the BSY line explicitly before
clearing the busfree status and enabling the busfree
interrupt.
Close a race condition in the processing of HS_MAILBOX
updates. We now clear the "updated" status before the
copy. This ensures that we don't accidentally clear
the status incorrectly when the host sneaks in an update
just after our last copy, but before we clear the status.
This race has never been observed.
Don't re-enable SCSIEN if we lose the race to disable SCSIEN
in our interrupt handler's workaround for the RevA data-valid
too early issue.
aic79xx_inline.h:
Add comments indicating that the order in which bytes are
read or written in ahd_inw and ahd_outw is important. This
allows us to use these inlines when accessing registers with
side-effects.
aic79xx_pci.c:
The 29320 and the 29320B are 7902 not 7901 based products.
Correct the driver banner.
aic7xxx.h:
Enable the use of the auto-access pause feature
on the aic7870 and aic7880. It was disabled due
to an oversight.
aic7xxx.reg:
Move TARG_IMMEDIATE_SCB to alias LAST_MSG to
avoid leaving garbage in MWI_RESIDUAL. This
prevents spurious overflows whn operating target
mode on controllers that require the MWI_RESIDUAL
work-around.
aic7xxx.seq:
AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag.
Reference the correct softc field when testing
for its presence.
Set the NOT_IDENTIFIED and NO_CDB_SENT bits
in SEQ_FLAGS to indicate that the nexus is
invalid in await busfree.
aic7xxx_93cx6.c:
Add support for the C56/C66 versions of the EWEN and EWDS
commands.
aic7xxx.c:
aic7xxx_pci.c:
Move test for the validity of left over BIOS data
to ahc_test_register_access(). This guarantees that
any left over CHIPRST value is not clobbered by our
register access test and lost to the test that was
in ahc_reset.
2003-12-17 00:02:10 +00:00
|
|
|
struct ahd_pci_identity *ahd_find_pci_device(aic_dev_softc_t);
|
2002-12-01 08:13:37 +00:00
|
|
|
int ahd_pci_config(struct ahd_softc *,
|
|
|
|
|
struct ahd_pci_identity *);
|
|
|
|
|
int ahd_pci_test_register_access(struct ahd_softc *);
|
2002-06-05 19:52:45 +00:00
|
|
|
|
|
|
|
|
/************************** SCB and SCB queue management **********************/
|
|
|
|
|
int ahd_probe_scbs(struct ahd_softc *);
|
|
|
|
|
void ahd_qinfifo_requeue_tail(struct ahd_softc *ahd,
|
|
|
|
|
struct scb *scb);
|
|
|
|
|
int ahd_match_scb(struct ahd_softc *ahd, struct scb *scb,
|
|
|
|
|
int target, char channel, int lun,
|
|
|
|
|
u_int tag, role_t role);
|
|
|
|
|
|
|
|
|
|
/****************************** Initialization ********************************/
|
|
|
|
|
struct ahd_softc *ahd_alloc(void *platform_arg, char *name);
|
|
|
|
|
int ahd_softc_init(struct ahd_softc *);
|
|
|
|
|
void ahd_controller_info(struct ahd_softc *ahd, char *buf);
|
|
|
|
|
int ahd_init(struct ahd_softc *ahd);
|
|
|
|
|
int ahd_default_config(struct ahd_softc *ahd);
|
Correct spelling errors.
Switch to handling bad SCSI status as a sequencer interrupt
instead of having the kernel proccess these failures via
the completion queue. This is done because:
o The old scheme required us to pause the sequencer and clear
critical sections for each SCB. It seems that these pause
actions, if coincident with a sequencer FIFO interrupt, would
result in a FIFO interrupt getting lost or directing to the
wrong FIFO. This caused hangs when the driver was stressed
under high "queue full" loads.
o The completion code assumed that it was always called with
the sequencer running. This may not be the case in timeout
processing where completions occur manually via
ahd_pause_and_flushwork().
o With this scheme, the extra expense of clearing critical
sections is avoided since the sequencer will only self pause
once all pending selections have cleared and it is not in
a critical section.
aic79xx.c
Add code to handle the new BAD_SCB_STATUS sequencer
interrupt code. This just redirects the SCB through
the already existing ahd_complete_scb() code path.
Remove code in ahd_handle_scsi_status() that paused
the sequencer, made sure that no selections where
pending, and cleared critical sections. Bad
status SCBs are now only processed when all of these
conditions are true.
aic79xx.reg:
Add the BAD_SCB_STATUS sequencer interrupt code.
aic79xx.seq:
When completing an SCB upload to the host, if
we are doing this because the SCB contains non-zero
SCSI status, defer completing the SCB until there
are no pending selection events. When completing
these SCBs, use the new BAD_SCB_STATUS sequencer
interrupt. For all other uploaded SCBs (currently
only for underruns), the SCB is completed via the
normal done queue. Additionally, keep the SCB that
is currently being uploaded on the COMPLETE_DMA_SCB
list until the dma is completed, not just until the
DMA is started. This ensures that the DMA is restarted
properly should the host disable the DMA transfer for
some reason.
In our RevA workaround for Maxtor drives, guard against
the host pausing us while trying to pause I/O until the
first data-valid REQ by clearing the current snapshot
so that we can tell if the transfer has completed prior
to us noticing the REQINIT status.
In cfg4data_intr, shave off an instruction before getting
the data path running by adding an entrypoint to the
overrun handler to also increment the FIFO use count.
In the overrun handler, be sure to clear our LONGJMP
address in both exit paths.
Perform a few sequencer optimizations.
aic79xx.c:
Print the full path from the SCB when a packetized
status overrun occurs.
Remove references to LONGJMP_SCB which is being
removed from firmware usage.
Print the new SCB_FIFO_USE_COUNT field in the
per-SCB section of ahd_dump_card_state(). The
SCB_TAG field is now re-used by the sequencer,
so it no longer makes sense to reference this
field in the kernel driver.
aic79xx.h:
Re-arrange fields in the hardware SCB from largest
size type to smallest. This makes it easier to
move fields without changing field alignment.
The hardware scb tag field is now down near the
"spare" portion of the SCB to facilitate reuse
by the sequencer.
aic79xx.reg:
Remove LONGJMP_ADDR.
Rearrange SCB fields to match aic79xx.h.
Add SCB_FIFO_USE_COUNT as the first byte
of the SCB_TAG field.
aic79xx.seq:
Add a per-SCB "Fifos in use count" field and use
it to determine when it is safe (all data posted)
to deliver status back to the host. The old method
involved polling one or both FIFOs to verify that
the current task did not have pending data. This
makes running down the GSFIFO very cheap, so we
will empty the GSFIFO in one idle loop pass in
all cases.
Use this simplification of the completion process
to prune down the data FIFO teardown sequencer for
packetized transfers. Much more code is now shared
between the data residual and transfer complete cases.
Correct some issues in the packetized status handler.
It used to be possible to CLRCHN our FIFO before status
had fully transferred to the host. We also failed to
handle NONPACKREQ phases that could occur should a CRC
error occur during transmission of the status data packet.
Correct a few big endian issues:
aic79xx.c:
aic79xx_inline.h:
aic79xx_pci.c:
aic79xx_osm.c:
o Always get the SCB's tag via the SCB_GET_TAG acccessor
o Add missing use of byte swapping macros when touching
hscb fields.
o Don't double swap SEEPROM data when it is printed.
Correct a big-endian bug. We cannot assign a
o When assigning a 32bit LE variable to a 64bit LE
variable, we must be explict about how the words
of the 64bit LE variable are initialized. Cast to
(uint32_t*) to do this.
aic79xx.c:
In ahd_clear_critical_section(), hit CRLSCSIINT
after restoring the interrupt masks to avoid what
appears to be a glitch on SCSIINT. Any real SCSIINT
status will be persistent and will immidiately
reset SCSIINT. This clear should only get rid of
spurious SCSIINTs.
This glitch was the cause of the "Unexpected PKT busfree"
status that occurred under high queue full loads
Call ahd_fini_scbdata() after shutdown so that
any ahd_chip_init() routine that might access
SCB data will not access free'd memory.
Reset the bus on an IOERR since the chip doesn't
seem to reset to the new voltage level without
this.
Change offset calculation for scatter gather maps
so that the calculation is correct if an integral
multiple of sg lists does not fit in the allocation
size.
Adjust bus dma tag for data buffers based on 39BIT
addressing flag in our softc.
Use the QFREEZE count to simplify ahd_pause_and_flushworkd().
We can thus rely on the sequencer eventually clearing ENSELO.
In ahd_abort_scbs(), fix a bug that could potentially
corrupt sequencer state. The saved SCB was being
restored in the SCSI mode instead of the saved mode.
It turns out that the SCB did not need to be saved at all
as the scbptr is already restored by all subroutines
called during this function that modify that register.
aic79xx.c:
aic79xx.h:
aic79xx_pci.c:
Add support for parsing the seeprom vital product
data. The VPD data are currently unused.
aic79xx.h:
aic79xx.seq:
aic79xx_pci.c:
Add a firmware workaround to make the LED blink
brighter during packetized operations on the H2A.
aic79xx_inline.h:
The host does not use timer interrupts, so don't
gate our decision on whether or not to unpause
the sequencer on whether or not a timer interrupt
is pending.
2003-05-04 00:20:07 +00:00
|
|
|
int ahd_parse_vpddata(struct ahd_softc *ahd,
|
|
|
|
|
struct vpd_config *vpd);
|
2002-06-05 19:52:45 +00:00
|
|
|
int ahd_parse_cfgdata(struct ahd_softc *ahd,
|
|
|
|
|
struct seeprom_config *sc);
|
|
|
|
|
void ahd_intr_enable(struct ahd_softc *ahd, int enable);
|
2003-05-26 21:10:58 +00:00
|
|
|
void ahd_update_coalescing_values(struct ahd_softc *ahd,
|
aic79xx.c:
Implement the SCB_SILENT flag. This is useful for
hushing up the driver during DV or other operations
that we expect to cause transmission errors. The
messages will still print if the SHOW_MASKED_ERRORS
debug option is enabled.
Save and restore the NEGOADDR address when setting
new transfer settings. The sequencer performs lookups
in the negotiation table too and it expects NEGOADDR
to remain consistent across pause/unpause sessions.
Consistently use "offset" instead of "period" to determine
if we are running sync or not.
Add a SHOW_MESSAGES diagnostic for when we assert ATN
during message processing.
Print out IU, QAS, and RTI features when showing transfer options.
Limit the syncrate after all option conformance
changes have taken place in ahd_devlimited_syncrate.
Changes in options may change the final syncrate we
accept.
Keep a copy of the hs_mailbox in our softc so that
we can perform read/modify/write operations on the
hs_mailbox without having to pause the sequencer to
read the last written value. Use the ENINT_COALESS
flag in the hs_mailbox to toggle interrupt coalessing.
Add entrypoints for enabling interrupt coalessing and
setting both a timeout (how long to wait for commands
to be coalessed) and a maximum commands to coaless value.
Add a statistics timer that decides when to enable or
disable interrupt coalessing based on load.
Add a routine, ahd_reset_cmds_pending() which is used
to update the CMDS_PENDING sequencer variable whenever
error recovery compeltes SCBs without notifying the
sequencer. Since ahd_reset_cmds_pending is called
during ahd_unpause() only if we've aborted SCBs, its
call to ahd_flush_qoutfifo should not cause recursion
through ahd_run_qoutfifo(). A panic has been added to
ensure that this recursion does not occur.
In ahd_search_qinfifo, update the CMDS_PENDING sequencer
variable directly. ahd_search_qinififo can be called
in situations where using ahd_reset_cmds_pending() might
cause recursion. Since we can safely determine the
exact number to reduce CMDS_PENDING by in this scenario
without running the qoutfifo, the manual update is sufficient.
Clean up diagnostics.
Add ahd_flush_qoutfifo() which will run the qoutfifo
as well as complete any commands sitting on the
sequencer's COMPLETE_SCB lists or the good status FIFO.
Use this routine in several places that did similar
things in an add-hoc, but incomplete, fashion. A call
to this routine was also added to ahd_abort_scbs() to
close a race.
In ahd_pause_and_flushwork() only return once selections
are safely disabled. Flush all completed commands via
ahd_flush_qoutfifo().
Remove "Now packetized" diagnostic now that this
information is incorperated into the actual negotiation
messages that are displayed.
When forcing renegotiation, don't clober the current
ppr_options. Much of the driver uses this information
to determine if we are currently packetized or not.
Remove some stray spaces at column 1 in ahd_set_tags.
When complaining about getting a host message loop
request with no pending messages, print out the
SCB_CONTROL register down on the card.
Modify the ahd_sent_msg() routine to handle a search
for an outgoing identify message. Use this to detect
a msg reject on an identify message which typically
indicates that the target thought we were packetized.
Force a renegotiation in this case.
In ahd_search_qinfifo(), wait more effectively for SCB
DMA activities to cease. We also disable SCB fetch
operations since we are about to change the qinfifo
and any fetch in progress will likely be invalidated.
In ahd_qinfifo_count(), fix the qinfifo empty case.
In ahd_dump_card_state(), print out CCSCBCTL in the
correct mode.
If we are a narrow controller, don't set the current
width to unknown when forcing a future negotiation.
This just confuses the code into attempting a wide
negotiation on a narrow bus.
Add support for task management function completions.
Modify ahd_handle_devreset so that it can handle
lun resets in addition to target resets. Use
ahd_handle_devreset for lun and target reset task
management functions.
Handle the abort task TMF race case better. We now
wait until any current selections are over and then
set the TMF back to zero. This should cause the sequencer
to ignore the abort TMF completion should it occur.
Correct a bug in the illegal phase handler that
caused us to drop down to narrow when handling the
unexpected command phase case after 3rd party
reset of a packetized device.
Indicate the features, bugs, and flags set in the softc
that are used to control firmware patch download when
booting verbose.
aic79xx.h:
Add coalessing and HS_MAILBOX fields.
Add per-softc variables for the stats "daemon".
Add a debug option for interrupt coalessing activities.
Add two new softc flags:
o AHD_UPDATE_PEND_CMDS
Run ahd_reset_cmds_pending() on the next unpause.
o AHD_RUNNING_QOUTFIFO
Used to catch recursion through ahd_run_qoutfifo().
aic79xx.reg:
Correct register addresses related to the software timer
and the DFDBCTL register.
Add constants paramaterizing the software timer.
Add scratch ram locations for storing interrupt coalessing
tunables.
Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2.
In at least the REV A, these are writable bits. We make
use of that for a swtimer workaround in the sequencer.
Since HS_MAILBOX autoclears, provide a sequencer variable
to store its contents.
Add SEQINT codes for handling task management completions.
aic79xx.seq:
Correct ignore wide residue processing check for
a wide negotiation being in effect. We must be
in the SCSI register window in order to access the
negotiation table.
Use the software timer and a commands completed count to
implement interrupt coalessing. The command complete is
deferred until either the maximum command threshold or a
the expiration of a command deferral timer. If we have
more SCBs to complete to the host (sitting in COMPLETE_SCB
lists), always try to coaless them up to our coalessing limit.
If coalessing is enabled, but we have fewer commands oustanting
than the host's min coalessing limit, complete the command
immediately.
Add code to track the number of commands outstanding.
Commands are outstanding from the time they are placed
into the execution queue until the DMA to post completion
is setup.
Add a workaround for intvec_2 interrupts on the H2A4.
In H2A4, the mode pointer is not saved for intvec2, but
is restored on iret. This can lead to the restoration
of a bogus mode ptr. Manually clear the intmask bits and
do a normal return to compensate. We use intvec_2 to
track interrupt coalessing timeouts.
Since we cannot disable the swtimer's countdown, simply
mask its interrupt once we no longer care about it firing.
In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime
we are notified of an HS_MAILBOX update via the
HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a
local copy of persistant portions of the HS_MAILBOX as
the mailbox auto-clears on any read.
Move the test for the cfg4istat interrupt up an instruction
to hopefully close a race between the next outgoing selection
and our disabling of selections.
Add a missing ret to the last instruction in load_overrun_buf.
Add notifications to the host of task management
completions as well as the completions for commands
that completed successfully before their corresponding
TMF could be sent.
Hold a critical section during select-out processing
until we have a fully identified connection. This
removes a race condition with the legacy abort handler.
Correct a few spelling errors in some comments.
aic79xx_inline.h:
Call ahd_reset_cmds_pending() in ahd_unpause if required.
Update cmdcmplt interrupt statistics in our interrupt
handler.
Allow callers to ahd_send_scb() to set the task management
function.
aic79xx_pci.c:
Disable SERR and pause the controller prior to performing
our mmapped I/O test. The U320 controllers do not support
"auto-access-pause".
aic79xx_osm.c:
Set the task management function now that
ahd_send_scb() doesn't do it for us. We
also perform a lun reset in response to BDR
requests to packetized devices.
2003-01-20 20:17:35 +00:00
|
|
|
u_int timer,
|
|
|
|
|
u_int maxcmds,
|
|
|
|
|
u_int mincmds);
|
2003-05-26 21:10:58 +00:00
|
|
|
void ahd_enable_coalescing(struct ahd_softc *ahd,
|
aic79xx.c:
Implement the SCB_SILENT flag. This is useful for
hushing up the driver during DV or other operations
that we expect to cause transmission errors. The
messages will still print if the SHOW_MASKED_ERRORS
debug option is enabled.
Save and restore the NEGOADDR address when setting
new transfer settings. The sequencer performs lookups
in the negotiation table too and it expects NEGOADDR
to remain consistent across pause/unpause sessions.
Consistently use "offset" instead of "period" to determine
if we are running sync or not.
Add a SHOW_MESSAGES diagnostic for when we assert ATN
during message processing.
Print out IU, QAS, and RTI features when showing transfer options.
Limit the syncrate after all option conformance
changes have taken place in ahd_devlimited_syncrate.
Changes in options may change the final syncrate we
accept.
Keep a copy of the hs_mailbox in our softc so that
we can perform read/modify/write operations on the
hs_mailbox without having to pause the sequencer to
read the last written value. Use the ENINT_COALESS
flag in the hs_mailbox to toggle interrupt coalessing.
Add entrypoints for enabling interrupt coalessing and
setting both a timeout (how long to wait for commands
to be coalessed) and a maximum commands to coaless value.
Add a statistics timer that decides when to enable or
disable interrupt coalessing based on load.
Add a routine, ahd_reset_cmds_pending() which is used
to update the CMDS_PENDING sequencer variable whenever
error recovery compeltes SCBs without notifying the
sequencer. Since ahd_reset_cmds_pending is called
during ahd_unpause() only if we've aborted SCBs, its
call to ahd_flush_qoutfifo should not cause recursion
through ahd_run_qoutfifo(). A panic has been added to
ensure that this recursion does not occur.
In ahd_search_qinfifo, update the CMDS_PENDING sequencer
variable directly. ahd_search_qinififo can be called
in situations where using ahd_reset_cmds_pending() might
cause recursion. Since we can safely determine the
exact number to reduce CMDS_PENDING by in this scenario
without running the qoutfifo, the manual update is sufficient.
Clean up diagnostics.
Add ahd_flush_qoutfifo() which will run the qoutfifo
as well as complete any commands sitting on the
sequencer's COMPLETE_SCB lists or the good status FIFO.
Use this routine in several places that did similar
things in an add-hoc, but incomplete, fashion. A call
to this routine was also added to ahd_abort_scbs() to
close a race.
In ahd_pause_and_flushwork() only return once selections
are safely disabled. Flush all completed commands via
ahd_flush_qoutfifo().
Remove "Now packetized" diagnostic now that this
information is incorperated into the actual negotiation
messages that are displayed.
When forcing renegotiation, don't clober the current
ppr_options. Much of the driver uses this information
to determine if we are currently packetized or not.
Remove some stray spaces at column 1 in ahd_set_tags.
When complaining about getting a host message loop
request with no pending messages, print out the
SCB_CONTROL register down on the card.
Modify the ahd_sent_msg() routine to handle a search
for an outgoing identify message. Use this to detect
a msg reject on an identify message which typically
indicates that the target thought we were packetized.
Force a renegotiation in this case.
In ahd_search_qinfifo(), wait more effectively for SCB
DMA activities to cease. We also disable SCB fetch
operations since we are about to change the qinfifo
and any fetch in progress will likely be invalidated.
In ahd_qinfifo_count(), fix the qinfifo empty case.
In ahd_dump_card_state(), print out CCSCBCTL in the
correct mode.
If we are a narrow controller, don't set the current
width to unknown when forcing a future negotiation.
This just confuses the code into attempting a wide
negotiation on a narrow bus.
Add support for task management function completions.
Modify ahd_handle_devreset so that it can handle
lun resets in addition to target resets. Use
ahd_handle_devreset for lun and target reset task
management functions.
Handle the abort task TMF race case better. We now
wait until any current selections are over and then
set the TMF back to zero. This should cause the sequencer
to ignore the abort TMF completion should it occur.
Correct a bug in the illegal phase handler that
caused us to drop down to narrow when handling the
unexpected command phase case after 3rd party
reset of a packetized device.
Indicate the features, bugs, and flags set in the softc
that are used to control firmware patch download when
booting verbose.
aic79xx.h:
Add coalessing and HS_MAILBOX fields.
Add per-softc variables for the stats "daemon".
Add a debug option for interrupt coalessing activities.
Add two new softc flags:
o AHD_UPDATE_PEND_CMDS
Run ahd_reset_cmds_pending() on the next unpause.
o AHD_RUNNING_QOUTFIFO
Used to catch recursion through ahd_run_qoutfifo().
aic79xx.reg:
Correct register addresses related to the software timer
and the DFDBCTL register.
Add constants paramaterizing the software timer.
Add scratch ram locations for storing interrupt coalessing
tunables.
Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2.
In at least the REV A, these are writable bits. We make
use of that for a swtimer workaround in the sequencer.
Since HS_MAILBOX autoclears, provide a sequencer variable
to store its contents.
Add SEQINT codes for handling task management completions.
aic79xx.seq:
Correct ignore wide residue processing check for
a wide negotiation being in effect. We must be
in the SCSI register window in order to access the
negotiation table.
Use the software timer and a commands completed count to
implement interrupt coalessing. The command complete is
deferred until either the maximum command threshold or a
the expiration of a command deferral timer. If we have
more SCBs to complete to the host (sitting in COMPLETE_SCB
lists), always try to coaless them up to our coalessing limit.
If coalessing is enabled, but we have fewer commands oustanting
than the host's min coalessing limit, complete the command
immediately.
Add code to track the number of commands outstanding.
Commands are outstanding from the time they are placed
into the execution queue until the DMA to post completion
is setup.
Add a workaround for intvec_2 interrupts on the H2A4.
In H2A4, the mode pointer is not saved for intvec2, but
is restored on iret. This can lead to the restoration
of a bogus mode ptr. Manually clear the intmask bits and
do a normal return to compensate. We use intvec_2 to
track interrupt coalessing timeouts.
Since we cannot disable the swtimer's countdown, simply
mask its interrupt once we no longer care about it firing.
In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime
we are notified of an HS_MAILBOX update via the
HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a
local copy of persistant portions of the HS_MAILBOX as
the mailbox auto-clears on any read.
Move the test for the cfg4istat interrupt up an instruction
to hopefully close a race between the next outgoing selection
and our disabling of selections.
Add a missing ret to the last instruction in load_overrun_buf.
Add notifications to the host of task management
completions as well as the completions for commands
that completed successfully before their corresponding
TMF could be sent.
Hold a critical section during select-out processing
until we have a fully identified connection. This
removes a race condition with the legacy abort handler.
Correct a few spelling errors in some comments.
aic79xx_inline.h:
Call ahd_reset_cmds_pending() in ahd_unpause if required.
Update cmdcmplt interrupt statistics in our interrupt
handler.
Allow callers to ahd_send_scb() to set the task management
function.
aic79xx_pci.c:
Disable SERR and pause the controller prior to performing
our mmapped I/O test. The U320 controllers do not support
"auto-access-pause".
aic79xx_osm.c:
Set the task management function now that
ahd_send_scb() doesn't do it for us. We
also perform a lun reset in response to BDR
requests to packetized devices.
2003-01-20 20:17:35 +00:00
|
|
|
int enable);
|
2002-06-05 19:52:45 +00:00
|
|
|
void ahd_pause_and_flushwork(struct ahd_softc *ahd);
|
|
|
|
|
int ahd_suspend(struct ahd_softc *ahd);
|
|
|
|
|
int ahd_resume(struct ahd_softc *ahd);
|
|
|
|
|
void ahd_softc_insert(struct ahd_softc *);
|
|
|
|
|
struct ahd_softc *ahd_find_softc(struct ahd_softc *ahd);
|
|
|
|
|
void ahd_set_unit(struct ahd_softc *, int);
|
|
|
|
|
void ahd_set_name(struct ahd_softc *, char *);
|
2002-08-31 06:48:42 +00:00
|
|
|
struct scb *ahd_get_scb(struct ahd_softc *ahd, u_int col_idx);
|
|
|
|
|
void ahd_free_scb(struct ahd_softc *ahd, struct scb *scb);
|
2002-06-05 19:52:45 +00:00
|
|
|
void ahd_alloc_scbs(struct ahd_softc *ahd);
|
|
|
|
|
void ahd_free(struct ahd_softc *ahd);
|
2003-06-06 23:48:19 +00:00
|
|
|
int ahd_reset(struct ahd_softc *ahd, int reinit);
|
2002-06-05 19:52:45 +00:00
|
|
|
void ahd_shutdown(void *arg);
|
2003-06-06 23:48:19 +00:00
|
|
|
int ahd_write_flexport(struct ahd_softc *ahd,
|
|
|
|
|
u_int addr, u_int value);
|
|
|
|
|
int ahd_read_flexport(struct ahd_softc *ahd, u_int addr,
|
|
|
|
|
uint8_t *value);
|
|
|
|
|
int ahd_wait_flexport(struct ahd_softc *ahd);
|
2002-06-05 19:52:45 +00:00
|
|
|
|
|
|
|
|
/*************************** Interrupt Services *******************************/
|
|
|
|
|
void ahd_pci_intr(struct ahd_softc *ahd);
|
|
|
|
|
void ahd_clear_intstat(struct ahd_softc *ahd);
|
aic79xx.c:
Implement the SCB_SILENT flag. This is useful for
hushing up the driver during DV or other operations
that we expect to cause transmission errors. The
messages will still print if the SHOW_MASKED_ERRORS
debug option is enabled.
Save and restore the NEGOADDR address when setting
new transfer settings. The sequencer performs lookups
in the negotiation table too and it expects NEGOADDR
to remain consistent across pause/unpause sessions.
Consistently use "offset" instead of "period" to determine
if we are running sync or not.
Add a SHOW_MESSAGES diagnostic for when we assert ATN
during message processing.
Print out IU, QAS, and RTI features when showing transfer options.
Limit the syncrate after all option conformance
changes have taken place in ahd_devlimited_syncrate.
Changes in options may change the final syncrate we
accept.
Keep a copy of the hs_mailbox in our softc so that
we can perform read/modify/write operations on the
hs_mailbox without having to pause the sequencer to
read the last written value. Use the ENINT_COALESS
flag in the hs_mailbox to toggle interrupt coalessing.
Add entrypoints for enabling interrupt coalessing and
setting both a timeout (how long to wait for commands
to be coalessed) and a maximum commands to coaless value.
Add a statistics timer that decides when to enable or
disable interrupt coalessing based on load.
Add a routine, ahd_reset_cmds_pending() which is used
to update the CMDS_PENDING sequencer variable whenever
error recovery compeltes SCBs without notifying the
sequencer. Since ahd_reset_cmds_pending is called
during ahd_unpause() only if we've aborted SCBs, its
call to ahd_flush_qoutfifo should not cause recursion
through ahd_run_qoutfifo(). A panic has been added to
ensure that this recursion does not occur.
In ahd_search_qinfifo, update the CMDS_PENDING sequencer
variable directly. ahd_search_qinififo can be called
in situations where using ahd_reset_cmds_pending() might
cause recursion. Since we can safely determine the
exact number to reduce CMDS_PENDING by in this scenario
without running the qoutfifo, the manual update is sufficient.
Clean up diagnostics.
Add ahd_flush_qoutfifo() which will run the qoutfifo
as well as complete any commands sitting on the
sequencer's COMPLETE_SCB lists or the good status FIFO.
Use this routine in several places that did similar
things in an add-hoc, but incomplete, fashion. A call
to this routine was also added to ahd_abort_scbs() to
close a race.
In ahd_pause_and_flushwork() only return once selections
are safely disabled. Flush all completed commands via
ahd_flush_qoutfifo().
Remove "Now packetized" diagnostic now that this
information is incorperated into the actual negotiation
messages that are displayed.
When forcing renegotiation, don't clober the current
ppr_options. Much of the driver uses this information
to determine if we are currently packetized or not.
Remove some stray spaces at column 1 in ahd_set_tags.
When complaining about getting a host message loop
request with no pending messages, print out the
SCB_CONTROL register down on the card.
Modify the ahd_sent_msg() routine to handle a search
for an outgoing identify message. Use this to detect
a msg reject on an identify message which typically
indicates that the target thought we were packetized.
Force a renegotiation in this case.
In ahd_search_qinfifo(), wait more effectively for SCB
DMA activities to cease. We also disable SCB fetch
operations since we are about to change the qinfifo
and any fetch in progress will likely be invalidated.
In ahd_qinfifo_count(), fix the qinfifo empty case.
In ahd_dump_card_state(), print out CCSCBCTL in the
correct mode.
If we are a narrow controller, don't set the current
width to unknown when forcing a future negotiation.
This just confuses the code into attempting a wide
negotiation on a narrow bus.
Add support for task management function completions.
Modify ahd_handle_devreset so that it can handle
lun resets in addition to target resets. Use
ahd_handle_devreset for lun and target reset task
management functions.
Handle the abort task TMF race case better. We now
wait until any current selections are over and then
set the TMF back to zero. This should cause the sequencer
to ignore the abort TMF completion should it occur.
Correct a bug in the illegal phase handler that
caused us to drop down to narrow when handling the
unexpected command phase case after 3rd party
reset of a packetized device.
Indicate the features, bugs, and flags set in the softc
that are used to control firmware patch download when
booting verbose.
aic79xx.h:
Add coalessing and HS_MAILBOX fields.
Add per-softc variables for the stats "daemon".
Add a debug option for interrupt coalessing activities.
Add two new softc flags:
o AHD_UPDATE_PEND_CMDS
Run ahd_reset_cmds_pending() on the next unpause.
o AHD_RUNNING_QOUTFIFO
Used to catch recursion through ahd_run_qoutfifo().
aic79xx.reg:
Correct register addresses related to the software timer
and the DFDBCTL register.
Add constants paramaterizing the software timer.
Add scratch ram locations for storing interrupt coalessing
tunables.
Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2.
In at least the REV A, these are writable bits. We make
use of that for a swtimer workaround in the sequencer.
Since HS_MAILBOX autoclears, provide a sequencer variable
to store its contents.
Add SEQINT codes for handling task management completions.
aic79xx.seq:
Correct ignore wide residue processing check for
a wide negotiation being in effect. We must be
in the SCSI register window in order to access the
negotiation table.
Use the software timer and a commands completed count to
implement interrupt coalessing. The command complete is
deferred until either the maximum command threshold or a
the expiration of a command deferral timer. If we have
more SCBs to complete to the host (sitting in COMPLETE_SCB
lists), always try to coaless them up to our coalessing limit.
If coalessing is enabled, but we have fewer commands oustanting
than the host's min coalessing limit, complete the command
immediately.
Add code to track the number of commands outstanding.
Commands are outstanding from the time they are placed
into the execution queue until the DMA to post completion
is setup.
Add a workaround for intvec_2 interrupts on the H2A4.
In H2A4, the mode pointer is not saved for intvec2, but
is restored on iret. This can lead to the restoration
of a bogus mode ptr. Manually clear the intmask bits and
do a normal return to compensate. We use intvec_2 to
track interrupt coalessing timeouts.
Since we cannot disable the swtimer's countdown, simply
mask its interrupt once we no longer care about it firing.
In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime
we are notified of an HS_MAILBOX update via the
HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a
local copy of persistant portions of the HS_MAILBOX as
the mailbox auto-clears on any read.
Move the test for the cfg4istat interrupt up an instruction
to hopefully close a race between the next outgoing selection
and our disabling of selections.
Add a missing ret to the last instruction in load_overrun_buf.
Add notifications to the host of task management
completions as well as the completions for commands
that completed successfully before their corresponding
TMF could be sent.
Hold a critical section during select-out processing
until we have a fully identified connection. This
removes a race condition with the legacy abort handler.
Correct a few spelling errors in some comments.
aic79xx_inline.h:
Call ahd_reset_cmds_pending() in ahd_unpause if required.
Update cmdcmplt interrupt statistics in our interrupt
handler.
Allow callers to ahd_send_scb() to set the task management
function.
aic79xx_pci.c:
Disable SERR and pause the controller prior to performing
our mmapped I/O test. The U320 controllers do not support
"auto-access-pause".
aic79xx_osm.c:
Set the task management function now that
ahd_send_scb() doesn't do it for us. We
also perform a lun reset in response to BDR
requests to packetized devices.
2003-01-20 20:17:35 +00:00
|
|
|
void ahd_flush_qoutfifo(struct ahd_softc *ahd);
|
2002-06-05 19:52:45 +00:00
|
|
|
void ahd_run_qoutfifo(struct ahd_softc *ahd);
|
|
|
|
|
#ifdef AHD_TARGET_MODE
|
|
|
|
|
void ahd_run_tqinfifo(struct ahd_softc *ahd, int paused);
|
|
|
|
|
#endif
|
|
|
|
|
void ahd_handle_hwerrint(struct ahd_softc *ahd);
|
|
|
|
|
void ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat);
|
|
|
|
|
void ahd_handle_scsiint(struct ahd_softc *ahd,
|
|
|
|
|
u_int intstat);
|
|
|
|
|
void ahd_clear_critical_section(struct ahd_softc *ahd);
|
|
|
|
|
|
|
|
|
|
/***************************** Error Recovery *********************************/
|
|
|
|
|
typedef enum {
|
|
|
|
|
SEARCH_COMPLETE,
|
|
|
|
|
SEARCH_COUNT,
|
|
|
|
|
SEARCH_REMOVE,
|
|
|
|
|
SEARCH_PRINT
|
|
|
|
|
} ahd_search_action;
|
Correct a very rare case where command ordering could be compromised
by a transaction performing a driver handled message sequence (an
scb with the MK_MESSAGE flag set).
SCBs that perform host managed messaging must always be
at the head of their per-target selection queue so that
the firmware knows to manually assert ATN if the current
negotiation agreement is packetized. In the past we
guaranteed this by queuing these SCBs separarately in
the execution queue. This exposes the system to potential
command reordering in two cases:
1) Another SCB for the same ITL nexus is queued that does
not have the MK_MESSAGE flag set. This SCB will be
queued to the per-target list which can be serviced
before the MK_MESSAGE scb that preceeded it.
2) If the target cannot accept all of the commands in the
per-target selection queue in one selection, the remainder
is queued to the tail of the selection queues so as to
effect round-robin scheduling. This could allow the
MK_MESSAGE scb to be sent to the target before the
requeued commands.
This commit changes the firmware policy to defer queuing
MK_MESSAGE SCBs into the selection queues until this can
be done without affecting order. This means that the
target's selection queue is either empty, or the last
SCB on the execution queue is also a MK_MESSAGE SCB.
During any wait, the firmware halts the download of new
SCBs so only a single "holding location" is required.
Luckily, MK_MESSAGE SCBs are rare and typically occur only
during CAM's bus probe where only one command is outstanding
at a time. However, during some recovery scenarios, the
reordering *could* occur.
aic79xx.c:
Update ahd_search_qinfifo() and helper routines to
search for pending MK_MESSAGE scbs and properly
restitch the execution queue if either the MK_MESSAGE
SCB is being aborted, or the MK_MESSAGE SCB can be
queued due to the execution queue draining due to
aborts.
Enable LQOBUSFREE status to assert an interrupt.
This should be redundant since a BUSFREE interrupt
should always occur along with an LQOBUSFREE event,
but on the Rev A, this doesn't seem to be guaranteed.
When a PPR request is rejected when a previously
existing packetized agreement is in place, assume
that the target has been reset without our knowledge
and revert to async/narrow transfers. This corrects
two issues: the stale ENATNO setting that was used
to send the PPR is cleared so the firmware is not
confused by a future packetized selection with
ATN asserted but no MK_MESSAGE flag in the SCB and
it speeds up recovery by aborting any pending
packetized transactions that by definition are now
dead.
When re-queueing SCBs after a failed negotiation
attempt, ensure command ordering by freezing the
device queue first.
Traverse the list of pending SCBs rather than the
whole SCB array on the controller when pushing
MK_MESSAGE flag changes out to the controller.
The original code was optimized for the aic7xxx
controllers where there are fewer controller slots
then pending SCBs and the firmware picks SCB
slots. For the U320 controller, the hope is
that we have fewer pending SCBs then the 512
slots on the controller.
Enhance some diagnostics.
Factor out some common code.
aic79xx.h:
Add prototype for new ahd_done_with_status() that is
used to factor out some commone code.
aic79xx.reg:
Add definisions for the pending MK_MESSAGE SCB.
aic79xx.seq:
Defer MK_MESSAGE SCB queing to the execution queue
so as to preserve command ordering. Re-arrange some
of the selection processing code so the above change
had no performance impact on the common code path.
Close a few critical section holes.
When entering a non-packetized phase, manually enable
busfree interrupts, since the controller hardware
does not do this automatically.
aic79xx_inline.h:
Enhance logging for queued SCBs.
aic79xx_osm.c:
Add new a new DDB ahd command, ahd_dump, which
invokes the ahd_dump_card_state() routine on the
unit specified with the ahd_sunit DDB command.
aic79xx_pci.c:
Turn on the BUSFREEREV bug for the Rev B. controller.
This is required to close the busfree during non-packetized
phase hole.
2004-08-04 17:55:34 +00:00
|
|
|
void ahd_done_with_status(struct ahd_softc *ahd,
|
|
|
|
|
struct scb *scb, uint32_t status);
|
2002-06-05 19:52:45 +00:00
|
|
|
int ahd_search_qinfifo(struct ahd_softc *ahd, int target,
|
|
|
|
|
char channel, int lun, u_int tag,
|
|
|
|
|
role_t role, uint32_t status,
|
|
|
|
|
ahd_search_action action);
|
|
|
|
|
int ahd_search_disc_list(struct ahd_softc *ahd, int target,
|
|
|
|
|
char channel, int lun, u_int tag,
|
|
|
|
|
int stop_on_first, int remove,
|
|
|
|
|
int save_state);
|
|
|
|
|
void ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb);
|
|
|
|
|
int ahd_reset_channel(struct ahd_softc *ahd, char channel,
|
|
|
|
|
int initiate_reset);
|
|
|
|
|
int ahd_abort_scbs(struct ahd_softc *ahd, int target,
|
|
|
|
|
char channel, int lun, u_int tag,
|
|
|
|
|
role_t role, uint32_t status);
|
|
|
|
|
void ahd_restart(struct ahd_softc *ahd);
|
|
|
|
|
void ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo);
|
|
|
|
|
void ahd_handle_scb_status(struct ahd_softc *ahd,
|
|
|
|
|
struct scb *scb);
|
|
|
|
|
void ahd_handle_scsi_status(struct ahd_softc *ahd,
|
|
|
|
|
struct scb *scb);
|
|
|
|
|
void ahd_calc_residual(struct ahd_softc *ahd,
|
|
|
|
|
struct scb *scb);
|
ahc_eisa.c:
ahc_pci.c:
ahd_pci.c:
aic7xxx.c:
aic79xx.c:
aic_osm_lib.c:
aic_osm_lib.h:
Use common OSM routines from aic_osm_lib for bus dma operations,
delay routines, accessing CCBs, byte swapping, etc.
aic7xxx_pci.c:
Provide a better description for the 2915/30LP on attach.
aic7xxx.c:
aic79xx.c:
aic7770.c:
aic79xx_pci.c:
aic7xxx_pci.c:
aic7xxx_93cx6.c:
Move FBSDID behind an ifdef so that these core files will
still compile under other OSes.
aic79xx.h:
aic79xx_pci.c:
aic79xx.seq:
To speed up non-packetized CDB delivery in Rev B, all CDB
acks are "released" to the output sync as soon as the
command phase starts. There is only one problem with this
approach. If the target changes phase before all data are
sent, we have left over acks that can go out on the bus in
a data phase. Due to other chip contraints, this only
happens if the target goes to data-in, but if the acks go
out before we can test SDONE, we'll think that the transfer
has completed successfully. Work around this by taking
advantage of the 400ns or 800ns dead time between command
phase and the REQ of the new phase. If the transfer has
completed successfully, SCSIEN should fall *long* before we
see a phase change. We thus treat any phasemiss that
occurs before SCSIEN falls as an incomplete transfer.
aic79xx.h:
Add the AHD_FAST_CDB_DELIVERY feature.
aic79xx_pci.c:
Set AHD_FAST_CDB_DELIVERY for all Rev. B parts.
aic79xx.seq:
Test for PHASEMIS in the command phase for
all AHD_FAST_CDB_DELIVERY controlelrs.
ahd_pci.c:
ahc_pci.c:
aic7xxx.h:
aic79xx.h:
Move definition of controller BAR offsets to core header files.
aic7xxx.c:
aic79xx.c:
In the softc free routine, leave removal of a softc from the
global list of softcs to the OSM (the caller of this routine).
This allows us to avoid holding the softc list_lock during device
destruction where we may have to sleep waiting for our recovery
thread to halt.
ahc_pci.c:
Use ahc_pci_test_register access to validate I/O mapped in
addition to the tests already performed for memory mapped
access.
Remove unused ahc_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
ahd_pci.c:
Remove reduntant definition of controller BAR offsets. These
are also defined in aic79xx.h.
Remove unused ahd_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
aic7xxx.c:
aic79xx.c:
aic79xx.h:
aic7xxx.h:
aic7xxx_osm.c:
aic79xx_osm.c:
Move timeout handling to the driver cores. In the case
of the aic79xx driver, the algorithm has been enhanced
to try target resets before performing a bus reset. For
the aic7xxx driver, the algorithm is unchanged. Although
the drivers do not currently sleep during recovery (recovery
is timeout driven), the cores do expect all processing to
be performed via a recovery thread. Our timeout handlers
are now little stubs that wakeup the recovery thread.
aic79xx.c:
aic79xx.h:
aic79xx_inline.h:
Change shared_data allocation to use a map_node so
that the sentinel hscb can use this map node in
ahd_swap_with_next_hscb. This routine now swaps
the hscb_map pointer in additon to the hscb
contents so that any sync operations occur on
the correct map.
physaddr -> busaddr
Pointed out by: Jason Thorpe <thorpej@wasabisystems.com>
aic79xx.c:
Make more use of the in/out/w/l/q macros for accessing
byte registers in the chip.
Correct some issues in the ahd_flush_qoutfifo() routine.
o Run the qoutfifo only once the command channel
DMA engine has been halted. This closes a window
where we might have missed some entries.
o Change ahd_run_data_fifo() to not loop to completion.
If we happen to start on the wrong FIFO and the other
FIFO has a snapshot savepointers, we might deadlock.
This required our delay between FIFO tests to be
moved to the ahd_flush_qoutfifo() routine.
o Update/add comments.
o Remove spurious test for COMPLETE_DMA list being empty
when completing transactions from the GSFIFO with
residuals. The SCB must be put on the COMPLETE_DMA
scb list unconditionally.
o When halting command channel DMA activity, we must
disable the DMA channel in all cases but an update
of the QOUTFIFO. The latter case is required so
that the sequencer will update its position in the
QOUTFIFO. Previously, we left the channel enabled
for all "push" DMAs. This left us vulnerable to
the sequencer handling an SCB push long after that
SCB was already processed manually by this routine.
o Correct the polarity of tests involving
ahd_scb_active_in_fifo(). This routine returns
non-zero for true.
Return to processing bad status completions through
the qoutfifo. This reduces the time that the sequencer
is kept paused when handling transactions with bad
status or underruns.
When waiting for the controller to quiece selections,
add a delay to our loop. Otherwise we may fail to wait
long enough for the sequencer to comply.
On H2A4 hardware, use the slow slewrate for non-paced
transfers. This mirrors what the Adaptec Windows
drivers do.
On the Rev B. only slow down the CRC timing for
older U160 devices that might need the slower timing.
We define "older" as devices that do not support
packetized protocol.
Wait up to 5000 * 5us for the SEEPROM to become unbusy.
Write ops seem to take much longer than read ops.
aic79xx.seq:
For controllers with the FAINT_LED bug, turn the diagnostic
led feature on during selection and reselection. This covers
the non-packetized case. The LED will be disabled for
non-packetized transfers once we return to the top level idle
loop. Add more comments about the busy LED workaround.
Extend a critical section around the entire
command channel idle loop process. Previously
the portion of this handler that directly manipulated
the linked list of completed SCBs was not protected.
This is the likely cause of the recent reports of
commands being completed twice by the driver.
Extend critical sections across the test for,
and the longjump to, longjump routines. This
prevents the firmware from trying to jump to
a longjmp handler that was just cleared by the
host.
Improve the locations of several critical section
begin and end points. Typically these changes
remove instructions that did not need to be
inside a critical section.
Close the "busfree after selection, but before busfree
interrupts can be enabled" race to just a single sequencer
instruction. We now test the BSY line explicitly before
clearing the busfree status and enabling the busfree
interrupt.
Close a race condition in the processing of HS_MAILBOX
updates. We now clear the "updated" status before the
copy. This ensures that we don't accidentally clear
the status incorrectly when the host sneaks in an update
just after our last copy, but before we clear the status.
This race has never been observed.
Don't re-enable SCSIEN if we lose the race to disable SCSIEN
in our interrupt handler's workaround for the RevA data-valid
too early issue.
aic79xx_inline.h:
Add comments indicating that the order in which bytes are
read or written in ahd_inw and ahd_outw is important. This
allows us to use these inlines when accessing registers with
side-effects.
aic79xx_pci.c:
The 29320 and the 29320B are 7902 not 7901 based products.
Correct the driver banner.
aic7xxx.h:
Enable the use of the auto-access pause feature
on the aic7870 and aic7880. It was disabled due
to an oversight.
aic7xxx.reg:
Move TARG_IMMEDIATE_SCB to alias LAST_MSG to
avoid leaving garbage in MWI_RESIDUAL. This
prevents spurious overflows whn operating target
mode on controllers that require the MWI_RESIDUAL
work-around.
aic7xxx.seq:
AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag.
Reference the correct softc field when testing
for its presence.
Set the NOT_IDENTIFIED and NO_CDB_SENT bits
in SEQ_FLAGS to indicate that the nexus is
invalid in await busfree.
aic7xxx_93cx6.c:
Add support for the C56/C66 versions of the EWEN and EWDS
commands.
aic7xxx.c:
aic7xxx_pci.c:
Move test for the validity of left over BIOS data
to ahc_test_register_access(). This guarantees that
any left over CHIPRST value is not clobbered by our
register access test and lost to the test that was
in ahc_reset.
2003-12-17 00:02:10 +00:00
|
|
|
void ahd_timeout(struct scb *scb);
|
|
|
|
|
void ahd_recover_commands(struct ahd_softc *ahd);
|
2002-06-05 19:52:45 +00:00
|
|
|
/*************************** Utility Functions ********************************/
|
|
|
|
|
struct ahd_phase_table_entry*
|
|
|
|
|
ahd_lookup_phase_entry(int phase);
|
|
|
|
|
void ahd_compile_devinfo(struct ahd_devinfo *devinfo,
|
|
|
|
|
u_int our_id, u_int target,
|
|
|
|
|
u_int lun, char channel,
|
|
|
|
|
role_t role);
|
|
|
|
|
/************************** Transfer Negotiation ******************************/
|
|
|
|
|
void ahd_find_syncrate(struct ahd_softc *ahd, u_int *period,
|
|
|
|
|
u_int *ppr_options, u_int maxsync);
|
|
|
|
|
void ahd_validate_offset(struct ahd_softc *ahd,
|
|
|
|
|
struct ahd_initiator_tinfo *tinfo,
|
|
|
|
|
u_int period, u_int *offset,
|
|
|
|
|
int wide, role_t role);
|
|
|
|
|
void ahd_validate_width(struct ahd_softc *ahd,
|
|
|
|
|
struct ahd_initiator_tinfo *tinfo,
|
|
|
|
|
u_int *bus_width,
|
|
|
|
|
role_t role);
|
2002-12-01 08:13:37 +00:00
|
|
|
/*
|
|
|
|
|
* Negotiation types. These are used to qualify if we should renegotiate
|
|
|
|
|
* even if our goal and current transport parameters are identical.
|
|
|
|
|
*/
|
|
|
|
|
typedef enum {
|
|
|
|
|
AHD_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */
|
|
|
|
|
AHD_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */
|
|
|
|
|
AHD_NEG_ALWAYS /* Renegotiat even if goal is async. */
|
|
|
|
|
} ahd_neg_type;
|
2002-06-05 19:52:45 +00:00
|
|
|
int ahd_update_neg_request(struct ahd_softc*,
|
|
|
|
|
struct ahd_devinfo*,
|
|
|
|
|
struct ahd_tmode_tstate*,
|
|
|
|
|
struct ahd_initiator_tinfo*,
|
2002-12-01 08:13:37 +00:00
|
|
|
ahd_neg_type);
|
2002-06-05 19:52:45 +00:00
|
|
|
void ahd_set_width(struct ahd_softc *ahd,
|
|
|
|
|
struct ahd_devinfo *devinfo,
|
|
|
|
|
u_int width, u_int type, int paused);
|
|
|
|
|
void ahd_set_syncrate(struct ahd_softc *ahd,
|
|
|
|
|
struct ahd_devinfo *devinfo,
|
|
|
|
|
u_int period, u_int offset,
|
|
|
|
|
u_int ppr_options,
|
|
|
|
|
u_int type, int paused);
|
|
|
|
|
typedef enum {
|
|
|
|
|
AHD_QUEUE_NONE,
|
|
|
|
|
AHD_QUEUE_BASIC,
|
|
|
|
|
AHD_QUEUE_TAGGED
|
|
|
|
|
} ahd_queue_alg;
|
|
|
|
|
|
|
|
|
|
void ahd_set_tags(struct ahd_softc *ahd,
|
|
|
|
|
struct ahd_devinfo *devinfo,
|
|
|
|
|
ahd_queue_alg alg);
|
|
|
|
|
|
|
|
|
|
/**************************** Target Mode *************************************/
|
|
|
|
|
#ifdef AHD_TARGET_MODE
|
|
|
|
|
void ahd_send_lstate_events(struct ahd_softc *,
|
|
|
|
|
struct ahd_tmode_lstate *);
|
|
|
|
|
void ahd_handle_en_lun(struct ahd_softc *ahd,
|
|
|
|
|
struct cam_sim *sim, union ccb *ccb);
|
|
|
|
|
cam_status ahd_find_tmode_devs(struct ahd_softc *ahd,
|
|
|
|
|
struct cam_sim *sim, union ccb *ccb,
|
|
|
|
|
struct ahd_tmode_tstate **tstate,
|
|
|
|
|
struct ahd_tmode_lstate **lstate,
|
|
|
|
|
int notfound_failure);
|
|
|
|
|
#ifndef AHD_TMODE_ENABLE
|
|
|
|
|
#define AHD_TMODE_ENABLE 0
|
|
|
|
|
#endif
|
|
|
|
|
#endif
|
|
|
|
|
/******************************* Debug ***************************************/
|
|
|
|
|
#ifdef AHD_DEBUG
|
|
|
|
|
extern uint32_t ahd_debug;
|
2002-12-01 08:13:37 +00:00
|
|
|
#define AHD_SHOW_MISC 0x00001
|
|
|
|
|
#define AHD_SHOW_SENSE 0x00002
|
|
|
|
|
#define AHD_SHOW_RECOVERY 0x00004
|
|
|
|
|
#define AHD_DUMP_SEEPROM 0x00008
|
|
|
|
|
#define AHD_SHOW_TERMCTL 0x00010
|
|
|
|
|
#define AHD_SHOW_MEMORY 0x00020
|
|
|
|
|
#define AHD_SHOW_MESSAGES 0x00040
|
|
|
|
|
#define AHD_SHOW_MODEPTR 0x00080
|
|
|
|
|
#define AHD_SHOW_SELTO 0x00100
|
|
|
|
|
#define AHD_SHOW_FIFOS 0x00200
|
|
|
|
|
#define AHD_SHOW_QFULL 0x00400
|
|
|
|
|
#define AHD_SHOW_DV 0x00800
|
|
|
|
|
#define AHD_SHOW_MASKED_ERRORS 0x01000
|
|
|
|
|
#define AHD_SHOW_QUEUE 0x02000
|
|
|
|
|
#define AHD_SHOW_TQIN 0x04000
|
|
|
|
|
#define AHD_SHOW_SG 0x08000
|
2003-05-26 21:10:58 +00:00
|
|
|
#define AHD_SHOW_INT_COALESCING 0x10000
|
aic79xx.c:
Implement the SCB_SILENT flag. This is useful for
hushing up the driver during DV or other operations
that we expect to cause transmission errors. The
messages will still print if the SHOW_MASKED_ERRORS
debug option is enabled.
Save and restore the NEGOADDR address when setting
new transfer settings. The sequencer performs lookups
in the negotiation table too and it expects NEGOADDR
to remain consistent across pause/unpause sessions.
Consistently use "offset" instead of "period" to determine
if we are running sync or not.
Add a SHOW_MESSAGES diagnostic for when we assert ATN
during message processing.
Print out IU, QAS, and RTI features when showing transfer options.
Limit the syncrate after all option conformance
changes have taken place in ahd_devlimited_syncrate.
Changes in options may change the final syncrate we
accept.
Keep a copy of the hs_mailbox in our softc so that
we can perform read/modify/write operations on the
hs_mailbox without having to pause the sequencer to
read the last written value. Use the ENINT_COALESS
flag in the hs_mailbox to toggle interrupt coalessing.
Add entrypoints for enabling interrupt coalessing and
setting both a timeout (how long to wait for commands
to be coalessed) and a maximum commands to coaless value.
Add a statistics timer that decides when to enable or
disable interrupt coalessing based on load.
Add a routine, ahd_reset_cmds_pending() which is used
to update the CMDS_PENDING sequencer variable whenever
error recovery compeltes SCBs without notifying the
sequencer. Since ahd_reset_cmds_pending is called
during ahd_unpause() only if we've aborted SCBs, its
call to ahd_flush_qoutfifo should not cause recursion
through ahd_run_qoutfifo(). A panic has been added to
ensure that this recursion does not occur.
In ahd_search_qinfifo, update the CMDS_PENDING sequencer
variable directly. ahd_search_qinififo can be called
in situations where using ahd_reset_cmds_pending() might
cause recursion. Since we can safely determine the
exact number to reduce CMDS_PENDING by in this scenario
without running the qoutfifo, the manual update is sufficient.
Clean up diagnostics.
Add ahd_flush_qoutfifo() which will run the qoutfifo
as well as complete any commands sitting on the
sequencer's COMPLETE_SCB lists or the good status FIFO.
Use this routine in several places that did similar
things in an add-hoc, but incomplete, fashion. A call
to this routine was also added to ahd_abort_scbs() to
close a race.
In ahd_pause_and_flushwork() only return once selections
are safely disabled. Flush all completed commands via
ahd_flush_qoutfifo().
Remove "Now packetized" diagnostic now that this
information is incorperated into the actual negotiation
messages that are displayed.
When forcing renegotiation, don't clober the current
ppr_options. Much of the driver uses this information
to determine if we are currently packetized or not.
Remove some stray spaces at column 1 in ahd_set_tags.
When complaining about getting a host message loop
request with no pending messages, print out the
SCB_CONTROL register down on the card.
Modify the ahd_sent_msg() routine to handle a search
for an outgoing identify message. Use this to detect
a msg reject on an identify message which typically
indicates that the target thought we were packetized.
Force a renegotiation in this case.
In ahd_search_qinfifo(), wait more effectively for SCB
DMA activities to cease. We also disable SCB fetch
operations since we are about to change the qinfifo
and any fetch in progress will likely be invalidated.
In ahd_qinfifo_count(), fix the qinfifo empty case.
In ahd_dump_card_state(), print out CCSCBCTL in the
correct mode.
If we are a narrow controller, don't set the current
width to unknown when forcing a future negotiation.
This just confuses the code into attempting a wide
negotiation on a narrow bus.
Add support for task management function completions.
Modify ahd_handle_devreset so that it can handle
lun resets in addition to target resets. Use
ahd_handle_devreset for lun and target reset task
management functions.
Handle the abort task TMF race case better. We now
wait until any current selections are over and then
set the TMF back to zero. This should cause the sequencer
to ignore the abort TMF completion should it occur.
Correct a bug in the illegal phase handler that
caused us to drop down to narrow when handling the
unexpected command phase case after 3rd party
reset of a packetized device.
Indicate the features, bugs, and flags set in the softc
that are used to control firmware patch download when
booting verbose.
aic79xx.h:
Add coalessing and HS_MAILBOX fields.
Add per-softc variables for the stats "daemon".
Add a debug option for interrupt coalessing activities.
Add two new softc flags:
o AHD_UPDATE_PEND_CMDS
Run ahd_reset_cmds_pending() on the next unpause.
o AHD_RUNNING_QOUTFIFO
Used to catch recursion through ahd_run_qoutfifo().
aic79xx.reg:
Correct register addresses related to the software timer
and the DFDBCTL register.
Add constants paramaterizing the software timer.
Add scratch ram locations for storing interrupt coalessing
tunables.
Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2.
In at least the REV A, these are writable bits. We make
use of that for a swtimer workaround in the sequencer.
Since HS_MAILBOX autoclears, provide a sequencer variable
to store its contents.
Add SEQINT codes for handling task management completions.
aic79xx.seq:
Correct ignore wide residue processing check for
a wide negotiation being in effect. We must be
in the SCSI register window in order to access the
negotiation table.
Use the software timer and a commands completed count to
implement interrupt coalessing. The command complete is
deferred until either the maximum command threshold or a
the expiration of a command deferral timer. If we have
more SCBs to complete to the host (sitting in COMPLETE_SCB
lists), always try to coaless them up to our coalessing limit.
If coalessing is enabled, but we have fewer commands oustanting
than the host's min coalessing limit, complete the command
immediately.
Add code to track the number of commands outstanding.
Commands are outstanding from the time they are placed
into the execution queue until the DMA to post completion
is setup.
Add a workaround for intvec_2 interrupts on the H2A4.
In H2A4, the mode pointer is not saved for intvec2, but
is restored on iret. This can lead to the restoration
of a bogus mode ptr. Manually clear the intmask bits and
do a normal return to compensate. We use intvec_2 to
track interrupt coalessing timeouts.
Since we cannot disable the swtimer's countdown, simply
mask its interrupt once we no longer care about it firing.
In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime
we are notified of an HS_MAILBOX update via the
HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a
local copy of persistant portions of the HS_MAILBOX as
the mailbox auto-clears on any read.
Move the test for the cfg4istat interrupt up an instruction
to hopefully close a race between the next outgoing selection
and our disabling of selections.
Add a missing ret to the last instruction in load_overrun_buf.
Add notifications to the host of task management
completions as well as the completions for commands
that completed successfully before their corresponding
TMF could be sent.
Hold a critical section during select-out processing
until we have a fully identified connection. This
removes a race condition with the legacy abort handler.
Correct a few spelling errors in some comments.
aic79xx_inline.h:
Call ahd_reset_cmds_pending() in ahd_unpause if required.
Update cmdcmplt interrupt statistics in our interrupt
handler.
Allow callers to ahd_send_scb() to set the task management
function.
aic79xx_pci.c:
Disable SERR and pause the controller prior to performing
our mmapped I/O test. The U320 controllers do not support
"auto-access-pause".
aic79xx_osm.c:
Set the task management function now that
ahd_send_scb() doesn't do it for us. We
also perform a lun reset in response to BDR
requests to packetized devices.
2003-01-20 20:17:35 +00:00
|
|
|
#define AHD_DEBUG_SEQUENCER 0x20000
|
2002-06-05 19:52:45 +00:00
|
|
|
#endif
|
|
|
|
|
void ahd_print_scb(struct scb *scb);
|
2002-12-01 08:13:37 +00:00
|
|
|
void ahd_print_devinfo(struct ahd_softc *ahd,
|
|
|
|
|
struct ahd_devinfo *devinfo);
|
2002-06-05 19:52:45 +00:00
|
|
|
void ahd_dump_sglist(struct scb *scb);
|
|
|
|
|
void ahd_dump_all_cards_state(void);
|
|
|
|
|
void ahd_dump_card_state(struct ahd_softc *ahd);
|
2002-08-31 06:48:42 +00:00
|
|
|
int ahd_print_register(ahd_reg_parse_entry_t *table,
|
|
|
|
|
u_int num_entries,
|
|
|
|
|
const char *name,
|
|
|
|
|
u_int address,
|
|
|
|
|
u_int value,
|
|
|
|
|
u_int *cur_column,
|
|
|
|
|
u_int wrap_point);
|
2002-06-05 19:52:45 +00:00
|
|
|
void ahd_dump_scbs(struct ahd_softc *ahd);
|
|
|
|
|
#endif /* _AIC79XX_H_ */
|
