465 lines
13 KiB
C
465 lines
13 KiB
C
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/*
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* Generic register and struct definitions for the Adaptech 154x/164x
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* SCSI host adapters. Product specific probe and attach routines can
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* be found in:
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* <fill in list here>
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*
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* Derived from bt.c written by:
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*
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* Copyright (c) 1998 Justin T. Gibbs.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id$
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*/
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#ifndef _AHAREG_H_
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#define _AHAREG_H_
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#include "aha.h"
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#include <sys/queue.h>
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#include <cam/scsi/scsi_all.h>
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#define AHA_MAXTRANSFER_SIZE 0xffffff /* limited by 24bit counter */
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#define AHA_NSEG 17 /* The number of dma segments
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* supported. */
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#define ALL_TARGETS (~0)
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/*
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* Control Register pp. 1-8, 1-9 (Write Only)
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*/
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#define CONTROL_REG 0x00
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#define HARD_RESET 0x80 /* Hard Reset - return to POST state */
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#define SOFT_RESET 0x40 /* Soft Reset - Clears Adapter state */
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#define RESET_INTR 0x20 /* Reset/Ack Interrupt */
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#define RESET_SBUS 0x10 /* Drive SCSI bus reset signal */
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/*
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* Status Register pp. 1-9, 1-10 (Read Only)
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*/
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#define STATUS_REG 0x00
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#define DIAG_ACTIVE 0x80 /* Performing Internal Diags */
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#define DIAG_FAIL 0x40 /* Internal Diags failed */
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#define INIT_REQUIRED 0x20 /* MBOXes need initialization */
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#define HA_READY 0x10 /* HA ready for new commands */
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#define CMD_REG_BUSY 0x08 /* HA busy with last cmd byte */
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#define DATAIN_REG_READY 0x04 /* Data-in Byte available */
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#define STATUS_REG_RSVD 0x02
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#define CMD_INVALID 0x01 /* Invalid Command detected */
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/*
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* Command/Parameter Register pp. 1-10, 1-11 (Write Only)
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*/
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#define COMMAND_REG 0x01
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/*
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* Data in Register p. 1-11 (Read Only)
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*/
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#define DATAIN_REG 0x01
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/*
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* Interrupt Status Register pp. 1-12 -> 1-14 (Read Only)
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*/
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#define INTSTAT_REG 0x02
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#define INTR_PENDING 0x80 /* There is a pending INTR */
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#define INTSTAT_REG_RSVD 0x70
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#define SCSI_BUS_RESET 0x08 /* Bus Reset detected */
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#define CMD_COMPLETE 0x04
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#define OMB_READY 0x02 /* Outgoin Mailbox Ready */
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#define IMB_LOADED 0x01 /* Incoming Mailbox loaded */
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/*
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* Definitions for the "undocumented" geometry register
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*/
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typedef enum {
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GEOM_NODISK,
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GEOM_64x32,
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GEOM_128x32,
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GEOM_255x32
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} disk_geom_t;
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#define GEOMETRY_REG 0x03
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#define DISK0_GEOMETRY 0x03
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#define DISK1_GEOMETRY 0x0c
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#define EXTENDED_TRANSLATION 0x10
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#define GEOMETRY_DISK0(g_reg) (greg & DISK0_GEOMETRY)
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#define GEOMETRY_DISK1(g_reg) ((greg & DISK1_GEOMETRY) >> 2)
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#define AHA_NREGS (4)
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/*
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* Opcodes for Adapter commands.
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*/
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typedef enum {
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BOP_NOP = 0x00,
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BOP_INITIALIZE_MBOX = 0x01,
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BOP_START_MBOX = 0x02,
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BOP_EXECUTE_BIOS_CMD = 0x03,
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BOP_INQUIRE_BOARD_ID = 0x04,
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BOP_ENABLE_OMBR_INT = 0x05,
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BOP_SET_SEL_TIMOUT = 0x06,
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BOP_SET_TIME_ON_BUS = 0x07,
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BOP_SET_TIME_OFF_BUS = 0x08,
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BOP_SET_BUS_TRANS_RATE = 0x09,
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BOP_INQUIRE_INST_LDEVS = 0x0A,
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BOP_INQUIRE_CONFIG = 0x0B,
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BOP_ENABLE_TARGET_MODE = 0x0C,
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BOP_INQUIRE_SETUP_INFO = 0x0D,
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BOP_WRITE_LRAM = 0x1A,
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BOP_READ_LRAM = 0x1B,
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BOP_WRITE_CHIP_FIFO = 0x1C,
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BOP_READ_CHIP_FIFO = 0x1D,
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BOP_ECHO_DATA_BYTE = 0x1F,
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BOP_ADAPTER_DIAGNOSTICS = 0x20,
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BOP_SET_ADAPTER_OPTIONS = 0x21,
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BOP_SET_EEPROM = 0x22,
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BOP_RETURN_EEPROM = 0x23,
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BOP_ENABLE_SHADOW_RAM = 0x24,
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BOP_INIT_BIOS_MBOX = 0x25,
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BOP_SET_BIOS_BANK_1 = 0x26,
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BOP_SET_BIOS_BANK_2 = 0x27,
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BOP_RETURN_EXT_BIOS_INFO= 0x28,
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BOP_MBOX_IF_ENABLE = 0x29,
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BOP_SCSI_TERM_STATUS = 0x2C,
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BOP_INQUIRE_SCAM_DEV = 0x2D,
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BOP_SCSI_DEV_TABLE = 0x2E,
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BOP_SCAM_OP = 0x2F,
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BOP_START_BIOS_CMD = 0x82,
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BOP_INQUIRE_ESETUP_INFO = 0x8D
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} aha_op_t;
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/************** Definitions of Multi-byte commands and responses ************/
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struct aha_extbios
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{
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u_int8_t flags; /* Bit 3 == 1 extended bios enabled */
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u_int8_t mailboxlock; /* mail box lock code to unlock it */
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};
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/* This is really a bustech command, but we use it to differentiate between */
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/* the aha and bt */
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typedef struct {
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u_int8_t bus_type;
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u_int8_t bios_addr;
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u_int16_t max_sg;
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u_int8_t num_mboxes;
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u_int8_t mbox_base[4];
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u_int8_t :2,
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sync_neg10MB :1,
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floppy_disable :1,
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floppy_secondary_port :1,
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burst_mode_enabled :1,
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level_trigger_ints :1,
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:1;
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u_int8_t fw_ver_bytes_2_to_4[3];
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u_int8_t wide_bus :1,
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diff_bus :1,
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scam_capable :1,
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ultra_scsi :1,
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auto_term :1,
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:3;
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} esetup_info_data_t;
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typedef struct {
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u_int8_t num_mboxes;
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u_int8_t base_addr[3];
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} init_24b_mbox_params_t;
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typedef struct {
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u_int8_t board_type;
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/* These values are mostly from the aha-1540CP technical reference, but */
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/* with other values from the old aha1542.c driver. */
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#define BOARD_1540_16HEAD_BIOS 0x00
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#define BOARD_1540_64HEAD_BIOS 0x30
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#define BOARD_1542 0x41 /* aha-1540/1542 w/64-h bios */
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#define BOARD_1640 0x42 /* aha-1640 */
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#define BOARD_1740 0x43 /* aha-1740A/1742A/1744 */
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#define BOARD_1542C 0x44 /* aha-1542C */
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#define BOARD_1542CF 0x45 /* aha-1542CF */
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#define BOARD_1542CP 0x46 /* aha-1542CP, plug and play */
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u_int8_t cust_features;
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#define FEATURES_STANDARD 0x30
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u_int8_t firmware_rev_major;
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u_int8_t firmware_rev_minor;
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} board_id_data_t;
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typedef struct {
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u_int8_t dma_chan;
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#define DMA_CHAN_5 0x20
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#define DMA_CHAN_6 0x40
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#define DMA_CHAN_7 0x80
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u_int8_t irq;
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#define IRQ_9 0x01
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#define IRQ_10 0x02
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#define IRQ_11 0x04
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#define IRQ_12 0x08
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#define IRQ_14 0x20
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#define IRQ_15 0x40
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u_int8_t scsi_id;
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} config_data_t;
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typedef struct {
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u_int8_t enable;
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} target_mode_params_t;
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typedef struct {
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u_int8_t offset : 4,
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period : 3,
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sync : 1;
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} targ_syncinfo_t;
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typedef struct {
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u_int8_t initiate_sync : 1,
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parity_enable : 1,
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: 6;
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u_int8_t bus_transfer_rate;
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u_int8_t time_on_bus;
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u_int8_t time_off_bus;
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u_int8_t num_mboxes;
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u_int8_t mbox_base_addr[3];
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targ_syncinfo_t syncinfo[8];
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u_int8_t discinfo;
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u_int8_t customer_sig[20];
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u_int8_t auto_retry;
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u_int8_t board_switches;
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u_int8_t firmware_cksum[2];
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u_int8_t bios_mbox_addr[3];
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} setup_data_t;
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struct aha_isa_port {
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u_int16_t addr;
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u_int8_t probed;
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};
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extern struct aha_isa_port aha_isa_ports[];
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#define AHA_NUM_ISAPORTS 6
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typedef enum {
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BIO_330 = 0,
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BIO_334 = 1,
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BIO_230 = 2,
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BIO_234 = 3,
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BIO_130 = 4,
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BIO_134 = 5,
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BIO_DISABLED = 6,
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BIO_DISABLED2 = 7
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} isa_compat_io_t;
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typedef struct {
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u_int8_t sync_rate[16]; /* Sync in 10ns units */
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} target_sync_info_data_t;
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typedef struct {
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u_int8_t len[3];
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u_int8_t addr[3];
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} aha_sg_t;
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/********************** Mail Box definitions *******************************/
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typedef enum {
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BMBO_FREE = 0x0, /* MBO intry is free */
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BMBO_START = 0x1, /* MBO activate entry */
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BMBO_ABORT = 0x2 /* MBO abort entry */
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} aha_mbo_action_code_t;
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typedef struct aha_mbox_out {
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u_int8_t action_code;
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u_int8_t ccb_addr[3];
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} aha_mbox_out_t;
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typedef enum {
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BMBI_FREE = 0x0, /* MBI entry is free */
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BMBI_OK = 0x1, /* completed without error */
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BMBI_ABORT = 0x2, /* aborted ccb */
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BMBI_NOT_FOUND = 0x3, /* Tried to abort invalid CCB */
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BMBI_ERROR = 0x4 /* Completed with error */
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} aha_mbi_comp_code_t;
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typedef struct aha_mbox_in {
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u_int8_t comp_code;
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u_int8_t ccb_addr[3];
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} aha_mbox_in_t;
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/****************** Hardware CCB definition *********************************/
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typedef enum {
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INITIATOR_CCB = 0x00,
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INITIATOR_SG_CCB = 0x02,
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INITIATOR_CCB_WRESID = 0x03,
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INITIATOR_SG_CCB_WRESID = 0x04,
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INITIATOR_BUS_DEV_RESET = 0x81
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} aha_ccb_opcode_t;
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typedef enum {
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AHASTAT_NOERROR = 0x00,
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AHASTAT_SELTIMEOUT = 0x11,
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AHASTAT_DATARUN_ERROR = 0x12,
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AHASTAT_UNEXPECTED_BUSFREE = 0x13,
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AHASTAT_INVALID_PHASE = 0x14,
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AHASTAT_INVALID_ACTION_CODE = 0x15,
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AHASTAT_INVALID_OPCODE = 0x16,
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AHASTAT_LINKED_CCB_LUN_MISMATCH = 0x17,
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AHASTAT_INVALID_CCB_OR_SG_PARAM = 0x1A,
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AHASTAT_HA_SCSI_BUS_RESET = 0x22, /* stolen from bt */
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AHASTAT_HA_BDR = 0x25 /* Stolen from bt */
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} ahastat_t;
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struct aha_hccb {
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u_int8_t opcode; /* 0 */
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u_int8_t lun : 3, /* 1 */
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datain : 1,
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dataout : 1,
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target : 3;
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u_int8_t cmd_len; /* 2 */
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u_int8_t sense_len; /* 3 */
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u_int8_t data_len[3]; /* 4 */
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u_int8_t data_addr[3]; /* 7 */
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u_int8_t link_ptr[3]; /* 10 */
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u_int8_t link_id; /* 13 */
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u_int8_t ahastat; /* 14 */
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u_int8_t sdstat; /* 15 */
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u_int8_t reserved1; /* 16 */
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u_int8_t reserved2; /* 17 */
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u_int8_t scsi_cdb[16]; /* 18 */
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|
u_int8_t sense_data[SSD_FULL_SIZE];
|
||
|
|
};
|
||
|
|
|
||
|
|
typedef enum {
|
||
|
|
BCCB_FREE = 0x0,
|
||
|
|
BCCB_ACTIVE = 0x1,
|
||
|
|
BCCB_DEVICE_RESET = 0x2,
|
||
|
|
BCCB_RELEASE_SIMQ = 0x4
|
||
|
|
} bccb_flags_t;
|
||
|
|
|
||
|
|
struct aha_ccb {
|
||
|
|
struct aha_hccb hccb; /* hccb assumed to be at 0 */
|
||
|
|
SLIST_ENTRY(aha_ccb) links;
|
||
|
|
u_int32_t flags;
|
||
|
|
union ccb *ccb;
|
||
|
|
bus_dmamap_t dmamap;
|
||
|
|
aha_sg_t *sg_list;
|
||
|
|
u_int32_t sg_list_phys;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct sg_map_node {
|
||
|
|
bus_dmamap_t sg_dmamap;
|
||
|
|
bus_addr_t sg_physaddr;
|
||
|
|
aha_sg_t* sg_vaddr;
|
||
|
|
SLIST_ENTRY(sg_map_node) links;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct aha_softc {
|
||
|
|
bus_space_tag_t tag;
|
||
|
|
bus_space_handle_t bsh;
|
||
|
|
struct cam_sim *sim;
|
||
|
|
struct cam_path *path;
|
||
|
|
aha_mbox_out_t *cur_outbox;
|
||
|
|
aha_mbox_in_t *cur_inbox;
|
||
|
|
aha_mbox_out_t *last_outbox;
|
||
|
|
aha_mbox_in_t *last_inbox;
|
||
|
|
struct aha_ccb *aha_ccb_array;
|
||
|
|
SLIST_HEAD(,aha_ccb) free_aha_ccbs;
|
||
|
|
LIST_HEAD(,ccb_hdr) pending_ccbs;
|
||
|
|
u_int32_t aha_ccb_physbase;
|
||
|
|
aha_mbox_in_t *in_boxes;
|
||
|
|
aha_mbox_out_t *out_boxes;
|
||
|
|
struct scsi_sense_data *sense_buffers;
|
||
|
|
u_int32_t sense_buffers_physbase;
|
||
|
|
struct aha_ccb *recovery_bccb;
|
||
|
|
u_int num_boxes;
|
||
|
|
bus_dma_tag_t parent_dmat; /*
|
||
|
|
* All dmat's derive from
|
||
|
|
* the dmat defined by our
|
||
|
|
* bus.
|
||
|
|
*/
|
||
|
|
bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
|
||
|
|
bus_dma_tag_t mailbox_dmat; /* dmat for our mailboxes */
|
||
|
|
bus_dmamap_t mailbox_dmamap;
|
||
|
|
bus_dma_tag_t ccb_dmat; /* dmat for our ccb array */
|
||
|
|
bus_dmamap_t ccb_dmamap;
|
||
|
|
bus_dma_tag_t sg_dmat; /* dmat for our sg maps */
|
||
|
|
SLIST_HEAD(, sg_map_node) sg_maps;
|
||
|
|
bus_addr_t mailbox_physbase;
|
||
|
|
u_int num_ccbs; /* Number of CCBs malloc'd */
|
||
|
|
u_int max_ccbs; /* Maximum allocatable CCBs */
|
||
|
|
u_int max_sg;
|
||
|
|
u_int unit;
|
||
|
|
u_int scsi_id;
|
||
|
|
u_int32_t extended_trans :1,
|
||
|
|
wide_bus :1,
|
||
|
|
diff_bus :1,
|
||
|
|
ultra_scsi :1,
|
||
|
|
extended_lun :1,
|
||
|
|
strict_rr :1,
|
||
|
|
tag_capable :1,
|
||
|
|
wide_lun_ccb :1,
|
||
|
|
resource_shortage:1,
|
||
|
|
:23;
|
||
|
|
u_int16_t tags_permitted;
|
||
|
|
u_int16_t disc_permitted;
|
||
|
|
u_int16_t sync_permitted;
|
||
|
|
u_int16_t fast_permitted;
|
||
|
|
u_int16_t ultra_permitted;
|
||
|
|
u_int16_t wide_permitted;
|
||
|
|
u_int8_t init_level;
|
||
|
|
volatile u_int8_t command_cmp;
|
||
|
|
volatile u_int8_t latched_status;
|
||
|
|
u_int32_t bios_addr;
|
||
|
|
char firmware_ver[6];
|
||
|
|
char model[32];
|
||
|
|
u_int8_t boardid;
|
||
|
|
};
|
||
|
|
|
||
|
|
extern struct aha_softc *aha_softcs[]; /* XXX Config should handle this */
|
||
|
|
extern u_long aha_unit;
|
||
|
|
|
||
|
|
#define AHA_TEMP_UNIT 0xFF /* Unit for probes */
|
||
|
|
struct aha_softc* aha_alloc(int unit, bus_space_tag_t tag,
|
||
|
|
bus_space_handle_t bsh);
|
||
|
|
void aha_free(struct aha_softc *aha);
|
||
|
|
int aha_probe(struct aha_softc *aha);
|
||
|
|
int aha_fetch_adapter_info(struct aha_softc *aha);
|
||
|
|
int aha_init(struct aha_softc *aha);
|
||
|
|
int aha_attach(struct aha_softc *aha);
|
||
|
|
void aha_intr(void *arg);
|
||
|
|
char * aha_name(struct aha_softc *aha);
|
||
|
|
int aha_check_probed_iop(u_int ioport);
|
||
|
|
void aha_mark_probed_bio(isa_compat_io_t port);
|
||
|
|
void aha_mark_probed_iop(u_int ioport);
|
||
|
|
|
||
|
|
#define DEFAULT_CMD_TIMEOUT 10000 /* 1 sec */
|
||
|
|
int aha_cmd(struct aha_softc *aha, aha_op_t opcode,
|
||
|
|
u_int8_t *params, u_int param_len,
|
||
|
|
u_int8_t *reply_data, u_int reply_len,
|
||
|
|
u_int cmd_timeout);
|
||
|
|
|
||
|
|
#define aha_inb(aha, port) \
|
||
|
|
bus_space_read_1((aha)->tag, (aha)->bsh, port)
|
||
|
|
|
||
|
|
#define aha_outb(aha, port, value) \
|
||
|
|
bus_space_write_1((aha)->tag, (aha)->bsh, port, value)
|
||
|
|
|
||
|
|
#endif /* _AHA_H_ */
|