Merge from projects/mips to head by hand:
r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines
Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the
BSP. Provide a missing prototype.
r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines
Get the sense of this right. We use uintpr_t for bus_addr_t when
we're building everything except octeon && 32-bit. As note before, we
need a clearner way, but at least now the hack is right.
r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines
Add in Cavium's CID. Report what the unknown CID is.
r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines
Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON.
Spell ld script name right.
r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines
Another kludge for 64-bit bus_addr_t with 32-bit pointers...
r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines
- Add cpu_init_interrupts function that is supposed to
prepeare stuff required for spinning out interrupts later
- Add API for managing intrcnt/intrnames arrays
- Some minor style(9) fixes
r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines
For XLR adds extern for its bus space routines
r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines
With this commit our friend RMI will now compile. I have
not tested it and the chances of it running yet are about
ZERO.. but it will now compile. The hard part now begins,
making it run ;-)
r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines
Add some newer MIPS CO cores.
r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines
db_expr_t is really closer to a register_t.
Submitted by: bde@
r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines
- Remove bunch of declared but not defined cach-related variables
- Add mips_picache_linesize and mips_pdcache_linesize variables
r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines
Get rid of the hardcoded constants to define cacheable memory:
SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE
Instead we now keep a copy of the memory regions enumerated by
platform-specific code and use that to determine whether an address
is cacheable or not.
r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines
- Commit missing part of "bt" fix: store PC register in pcb_context struct
in cpu_switch and use it in stack_trace function later. pcb_regs contains
state of the process stored by exception handler and therefor is not
valid for sleeping processes.
r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines
Undo spamage of last MFC.
r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines
_ALIGN has to return u_long, since pointers don't fit into u_int in
64-bit mips.
r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines
- Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe.
Context info could be obtained from other sources (see below) no only from
td_pcb field
- Do not show a0..a3 values unless they're obtained from the stack. These
are only confirmed values.
- Fix bt command in DDB. Previous implementation used thread's trapframe
structure as a source info for trace unwinding, but this structure
is filled only when exception occurs. Valid register values for sleeping
processes are in pcb_context array. For curthread use pc/sp/ra for current
frame
r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines
- Get rid of label_t. It came from NetBSD and was used only in one place
r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines
Does 4 things:
1) Adds future RMI directories
2) Places intr_machdep.c in specfic files.arch pointing to the generic
intr_machdep.c. This allows us to have an architecture dependant
intr_machdep.c (which we will need for RMI) in the machine specific
directory
3) removes intr_machdep.c from files.mips
4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We
may need to look at finding a better place to put this. But first I want to
get this thing compiling.
r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines
- Move stack tracing function to db_trace.c
- Axe unused extern MipsXXX declarations
- Move all declarations for functions in exceptions.S/swtch.S
from trap.c to respective headers
r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines
- Sync caches properly when dealing with sf_buf
r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines
(u_int) is the wrong type here. Use unsigned long instead, even
though that's only less wrong...
r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines
Use unsigned long instead of unsigned for the integer casts here. The
former works for both ILP32 and LP64 programming models, while the
latter fails LP64.
r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines
- Make i/d cache size field 32-bit to prevent overflow
Submited by: Neelkanth Natu
r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines
fix prototype for MipsEmulateBranch.
r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines
Better definitions for a few types for n32/n64.
r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines
Fixed aligned macros...
r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines
- Port busdma code from FreeBSD/arm. This is more mature version
that takes into account all limitation to DMA memory (boundaries,
alignment) and implements bounce pages.
- Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf
r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines
Fix atomic_store_64 prototype for 64-bit systems.
r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines
The MCOUNT macro isn't going to work in 64-bit mode. Add a note to
this effect.
r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines
Provide a macro for PTR_ADDU as well. We may need to implement this
differently for N32... Use PTR_ADDU in DO_AST macro.
r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines
Change the addu here to daddu.
addu paranoina prodded by: jmallet@
r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines
addu and subu are special. We need to use daddu and dsubu here to get
proper behavior.
Submitted by: jmallet@
r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines
The SB1 has cohernet memory, so add it.
Also, Maxmem is better as a long.
Submitted by: Neelkanth Natu
r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines
The SB1 needs a special value for the cache field of the pte.
Submitted by: Neelkanth Natu
r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines
compute the areas to save registers in for 64-bit access correctly.
r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines
First cut at 64-bit types. not 100% sure these are all correct for
N32 ABI.
r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines
Trim unreferenced goo. SDRAM likely should be next, but it is still
referenced.
r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines
First cut at atomics for 64-bit machines and SMP machines.
# Note: Cavium provided a port that has atomics similar to these, but
# that does a syncw; sync; atomic; sync; syncw where we just do the classic
# mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why
# the extra is needed. Since my initial target is one core, I'll defer
# investigation until I bring up multiple cores. syncw is an octeon specific
# instruction.
r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines
Bring in cdefs.h from NetBSD to define ABI goo.
Obtained from: NetBSD
r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines
Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA,
ala sgi, and use it in preference to a bare 'la' so that it gets
translated to a 'dla' for the 64-bit pointer ABIs.
r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines
Use uintptr_t rather than unsigned here for 64-bit correctness.
r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines
Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe
this is correct. While registers are 64-bit, n32 is a 32-bit ABI and
lives in a 32-bit world (with explicit 64-bit registers, however).
Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4
+ SZREG' to reflect the actual offset of the structure in question.
r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines
(1) Use uintptr_t in preference to unsigned. The latter isn't right for
64-bit case, while the former is.
(2) include a SB1 specific coherency mapping
Submitted by: Neelkanth Nath (2)
r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines
db_expr_t should be a intptr_t, not an int. These expressions can be
addresses or numbers, and that's a intptr_t if I ever saw one.
r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines
Define COP0_SYNC for SB1 CPU.
Submitted by: Neelkanth Natu
r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines
Switch to ABI agnostic ta0-ta3. Provide defs for this in the right
places. Provide n32/n64 register name defintions. This should have
no effect for the O32 builds that everybody else uses, but should help
make N64 builds possible (lots of other changes are needed for that).
Obtained from: NetBSD (for the regdef.h changes)
r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines
- Add support for handling TLS area address in kernel space.
From the userland point of view get/set operations are
performed using sysarch(2) call.
r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines
- Add guards to ensure that these files are included only once
r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines
- Mark temp variable as "earlyclobber" in assembler inline in
atomic_fetchadd_32. Without it gcc would use it as input
register for v and sometimes generate following code for
function call like atomic_fetchadd_32(&(fp)->f_count, -1):
801238b4: 2402ffff li v0,-1
801238b8: c2230018 ll v1,24(s1)
801238bc: 00431021 addu v0,v0,v1
801238c0: e2220018 sc v0,24(s1)
801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8>
801238c8: 00000000 nop
Which is definitly wrong because if sc fails v0 is set to 0
and previous value of -1 is overriden hence whole operation
turns to bogus
r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines
bye bye. This is no longer referenced, but much code from it will
resurface for a bus-space implementation.
r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines
Cavium-specific goo is no longer necessary here. Of course, I now
have to write a bus space for cavium, but that shouldn't be too hard.
r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines
Move this to a more approrpiate plae.
r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines
Bring this in from the cavium port.
r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines
- Use restoreintr instead of enableint while accessing pcpu in DO_AST
r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines
- Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default
we assume that there is no FPU, because majority of SoC does
not have it.
r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines
- Add type cast for atomic_cmpset_acq_ptr arguments
r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines
- Remove now unused NetBSDism intr.h
r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines
- Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR
macroses thet check if address belongs to KSEG0, KSEG1 or both
of them respectively.
r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines
- Cast argument to proper type in order to avoid warnings like
"shift value is too large for given type"
r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines
- Use naming convention the same as MIPS spec does: eliminate _sel1 sufix
and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1
- Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes)
r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines
- Define accessor functions for CP0 Config(16) register selects 1, 2, 3.
Content of these registers is defined in MIPS spec and can be used
for obtaining info about CPU capabilities.
r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines
- Make mips_bus_space_generic be of type bus_space_tag_t instead of
struct bus_space and update all relevant places.
r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines
Use FreeBSD/arm approach for handling bus space access: space tag is a pointer
to bus_space structure that defines access methods and hence every bus can
define own accessors. Default space is mips_bus_space_generic. It's a simple
interface to physical memory, values are read with regard to host system
byte order.
2010-01-10 19:50:24 +00:00
|
|
|
/* $NetBSD: bus.h,v 1.11 2003/07/28 17:35:54 thorpej Exp $ */
|
|
|
|
|
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
/*-
|
2017-11-27 15:07:26 +00:00
|
|
|
* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-4-Clause
|
|
|
|
|
*
|
Merge from projects/mips to head by hand:
r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines
Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the
BSP. Provide a missing prototype.
r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines
Get the sense of this right. We use uintpr_t for bus_addr_t when
we're building everything except octeon && 32-bit. As note before, we
need a clearner way, but at least now the hack is right.
r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines
Add in Cavium's CID. Report what the unknown CID is.
r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines
Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON.
Spell ld script name right.
r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines
Another kludge for 64-bit bus_addr_t with 32-bit pointers...
r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines
- Add cpu_init_interrupts function that is supposed to
prepeare stuff required for spinning out interrupts later
- Add API for managing intrcnt/intrnames arrays
- Some minor style(9) fixes
r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines
For XLR adds extern for its bus space routines
r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines
With this commit our friend RMI will now compile. I have
not tested it and the chances of it running yet are about
ZERO.. but it will now compile. The hard part now begins,
making it run ;-)
r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines
Add some newer MIPS CO cores.
r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines
db_expr_t is really closer to a register_t.
Submitted by: bde@
r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines
- Remove bunch of declared but not defined cach-related variables
- Add mips_picache_linesize and mips_pdcache_linesize variables
r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines
Get rid of the hardcoded constants to define cacheable memory:
SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE
Instead we now keep a copy of the memory regions enumerated by
platform-specific code and use that to determine whether an address
is cacheable or not.
r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines
- Commit missing part of "bt" fix: store PC register in pcb_context struct
in cpu_switch and use it in stack_trace function later. pcb_regs contains
state of the process stored by exception handler and therefor is not
valid for sleeping processes.
r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines
Undo spamage of last MFC.
r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines
_ALIGN has to return u_long, since pointers don't fit into u_int in
64-bit mips.
r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines
- Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe.
Context info could be obtained from other sources (see below) no only from
td_pcb field
- Do not show a0..a3 values unless they're obtained from the stack. These
are only confirmed values.
- Fix bt command in DDB. Previous implementation used thread's trapframe
structure as a source info for trace unwinding, but this structure
is filled only when exception occurs. Valid register values for sleeping
processes are in pcb_context array. For curthread use pc/sp/ra for current
frame
r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines
- Get rid of label_t. It came from NetBSD and was used only in one place
r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines
Does 4 things:
1) Adds future RMI directories
2) Places intr_machdep.c in specfic files.arch pointing to the generic
intr_machdep.c. This allows us to have an architecture dependant
intr_machdep.c (which we will need for RMI) in the machine specific
directory
3) removes intr_machdep.c from files.mips
4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We
may need to look at finding a better place to put this. But first I want to
get this thing compiling.
r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines
- Move stack tracing function to db_trace.c
- Axe unused extern MipsXXX declarations
- Move all declarations for functions in exceptions.S/swtch.S
from trap.c to respective headers
r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines
- Sync caches properly when dealing with sf_buf
r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines
(u_int) is the wrong type here. Use unsigned long instead, even
though that's only less wrong...
r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines
Use unsigned long instead of unsigned for the integer casts here. The
former works for both ILP32 and LP64 programming models, while the
latter fails LP64.
r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines
- Make i/d cache size field 32-bit to prevent overflow
Submited by: Neelkanth Natu
r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines
fix prototype for MipsEmulateBranch.
r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines
Better definitions for a few types for n32/n64.
r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines
Fixed aligned macros...
r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines
- Port busdma code from FreeBSD/arm. This is more mature version
that takes into account all limitation to DMA memory (boundaries,
alignment) and implements bounce pages.
- Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf
r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines
Fix atomic_store_64 prototype for 64-bit systems.
r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines
The MCOUNT macro isn't going to work in 64-bit mode. Add a note to
this effect.
r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines
Provide a macro for PTR_ADDU as well. We may need to implement this
differently for N32... Use PTR_ADDU in DO_AST macro.
r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines
Change the addu here to daddu.
addu paranoina prodded by: jmallet@
r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines
addu and subu are special. We need to use daddu and dsubu here to get
proper behavior.
Submitted by: jmallet@
r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines
The SB1 has cohernet memory, so add it.
Also, Maxmem is better as a long.
Submitted by: Neelkanth Natu
r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines
The SB1 needs a special value for the cache field of the pte.
Submitted by: Neelkanth Natu
r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines
compute the areas to save registers in for 64-bit access correctly.
r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines
First cut at 64-bit types. not 100% sure these are all correct for
N32 ABI.
r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines
Trim unreferenced goo. SDRAM likely should be next, but it is still
referenced.
r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines
First cut at atomics for 64-bit machines and SMP machines.
# Note: Cavium provided a port that has atomics similar to these, but
# that does a syncw; sync; atomic; sync; syncw where we just do the classic
# mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why
# the extra is needed. Since my initial target is one core, I'll defer
# investigation until I bring up multiple cores. syncw is an octeon specific
# instruction.
r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines
Bring in cdefs.h from NetBSD to define ABI goo.
Obtained from: NetBSD
r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines
Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA,
ala sgi, and use it in preference to a bare 'la' so that it gets
translated to a 'dla' for the 64-bit pointer ABIs.
r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines
Use uintptr_t rather than unsigned here for 64-bit correctness.
r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines
Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe
this is correct. While registers are 64-bit, n32 is a 32-bit ABI and
lives in a 32-bit world (with explicit 64-bit registers, however).
Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4
+ SZREG' to reflect the actual offset of the structure in question.
r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines
(1) Use uintptr_t in preference to unsigned. The latter isn't right for
64-bit case, while the former is.
(2) include a SB1 specific coherency mapping
Submitted by: Neelkanth Nath (2)
r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines
db_expr_t should be a intptr_t, not an int. These expressions can be
addresses or numbers, and that's a intptr_t if I ever saw one.
r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines
Define COP0_SYNC for SB1 CPU.
Submitted by: Neelkanth Natu
r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines
Switch to ABI agnostic ta0-ta3. Provide defs for this in the right
places. Provide n32/n64 register name defintions. This should have
no effect for the O32 builds that everybody else uses, but should help
make N64 builds possible (lots of other changes are needed for that).
Obtained from: NetBSD (for the regdef.h changes)
r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines
- Add support for handling TLS area address in kernel space.
From the userland point of view get/set operations are
performed using sysarch(2) call.
r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines
- Add guards to ensure that these files are included only once
r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines
- Mark temp variable as "earlyclobber" in assembler inline in
atomic_fetchadd_32. Without it gcc would use it as input
register for v and sometimes generate following code for
function call like atomic_fetchadd_32(&(fp)->f_count, -1):
801238b4: 2402ffff li v0,-1
801238b8: c2230018 ll v1,24(s1)
801238bc: 00431021 addu v0,v0,v1
801238c0: e2220018 sc v0,24(s1)
801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8>
801238c8: 00000000 nop
Which is definitly wrong because if sc fails v0 is set to 0
and previous value of -1 is overriden hence whole operation
turns to bogus
r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines
bye bye. This is no longer referenced, but much code from it will
resurface for a bus-space implementation.
r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines
Cavium-specific goo is no longer necessary here. Of course, I now
have to write a bus space for cavium, but that shouldn't be too hard.
r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines
Move this to a more approrpiate plae.
r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines
Bring this in from the cavium port.
r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines
- Use restoreintr instead of enableint while accessing pcpu in DO_AST
r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines
- Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default
we assume that there is no FPU, because majority of SoC does
not have it.
r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines
- Add type cast for atomic_cmpset_acq_ptr arguments
r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines
- Remove now unused NetBSDism intr.h
r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines
- Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR
macroses thet check if address belongs to KSEG0, KSEG1 or both
of them respectively.
r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines
- Cast argument to proper type in order to avoid warnings like
"shift value is too large for given type"
r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines
- Use naming convention the same as MIPS spec does: eliminate _sel1 sufix
and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1
- Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes)
r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines
- Define accessor functions for CP0 Config(16) register selects 1, 2, 3.
Content of these registers is defined in MIPS spec and can be used
for obtaining info about CPU capabilities.
r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines
- Make mips_bus_space_generic be of type bus_space_tag_t instead of
struct bus_space and update all relevant places.
r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines
Use FreeBSD/arm approach for handling bus space access: space tag is a pointer
to bus_space structure that defines access methods and hence every bus can
define own accessors. Default space is mips_bus_space_generic. It's a simple
interface to physical memory, values are read with regard to host system
byte order.
2010-01-10 19:50:24 +00:00
|
|
|
* Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
* All rights reserved.
|
|
|
|
|
*
|
|
|
|
|
* This code is derived from software contributed to The NetBSD Foundation
|
|
|
|
|
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
|
|
|
|
|
* NASA Ames Research Center.
|
|
|
|
|
*
|
|
|
|
|
* Redistribution and use in source and binary forms, with or without
|
|
|
|
|
* modification, are permitted provided that the following conditions
|
|
|
|
|
* are met:
|
|
|
|
|
* 1. Redistributions of source code must retain the above copyright
|
|
|
|
|
* notice, this list of conditions and the following disclaimer.
|
|
|
|
|
* 2. Redistributions in binary form must reproduce the above copyright
|
|
|
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
|
|
|
* documentation and/or other materials provided with the distribution.
|
|
|
|
|
*
|
|
|
|
|
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
|
|
|
|
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
|
|
|
|
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
|
|
|
|
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
|
|
|
|
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
|
|
|
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
|
|
|
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
|
|
|
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
|
|
|
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
|
|
|
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
|
|
|
* POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
|
*/
|
|
|
|
|
|
Merge from projects/mips to head by hand:
r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines
Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the
BSP. Provide a missing prototype.
r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines
Get the sense of this right. We use uintpr_t for bus_addr_t when
we're building everything except octeon && 32-bit. As note before, we
need a clearner way, but at least now the hack is right.
r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines
Add in Cavium's CID. Report what the unknown CID is.
r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines
Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON.
Spell ld script name right.
r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines
Another kludge for 64-bit bus_addr_t with 32-bit pointers...
r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines
- Add cpu_init_interrupts function that is supposed to
prepeare stuff required for spinning out interrupts later
- Add API for managing intrcnt/intrnames arrays
- Some minor style(9) fixes
r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines
For XLR adds extern for its bus space routines
r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines
With this commit our friend RMI will now compile. I have
not tested it and the chances of it running yet are about
ZERO.. but it will now compile. The hard part now begins,
making it run ;-)
r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines
Add some newer MIPS CO cores.
r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines
db_expr_t is really closer to a register_t.
Submitted by: bde@
r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines
- Remove bunch of declared but not defined cach-related variables
- Add mips_picache_linesize and mips_pdcache_linesize variables
r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines
Get rid of the hardcoded constants to define cacheable memory:
SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE
Instead we now keep a copy of the memory regions enumerated by
platform-specific code and use that to determine whether an address
is cacheable or not.
r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines
- Commit missing part of "bt" fix: store PC register in pcb_context struct
in cpu_switch and use it in stack_trace function later. pcb_regs contains
state of the process stored by exception handler and therefor is not
valid for sleeping processes.
r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines
Undo spamage of last MFC.
r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines
_ALIGN has to return u_long, since pointers don't fit into u_int in
64-bit mips.
r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines
- Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe.
Context info could be obtained from other sources (see below) no only from
td_pcb field
- Do not show a0..a3 values unless they're obtained from the stack. These
are only confirmed values.
- Fix bt command in DDB. Previous implementation used thread's trapframe
structure as a source info for trace unwinding, but this structure
is filled only when exception occurs. Valid register values for sleeping
processes are in pcb_context array. For curthread use pc/sp/ra for current
frame
r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines
- Get rid of label_t. It came from NetBSD and was used only in one place
r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines
Does 4 things:
1) Adds future RMI directories
2) Places intr_machdep.c in specfic files.arch pointing to the generic
intr_machdep.c. This allows us to have an architecture dependant
intr_machdep.c (which we will need for RMI) in the machine specific
directory
3) removes intr_machdep.c from files.mips
4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We
may need to look at finding a better place to put this. But first I want to
get this thing compiling.
r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines
- Move stack tracing function to db_trace.c
- Axe unused extern MipsXXX declarations
- Move all declarations for functions in exceptions.S/swtch.S
from trap.c to respective headers
r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines
- Sync caches properly when dealing with sf_buf
r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines
(u_int) is the wrong type here. Use unsigned long instead, even
though that's only less wrong...
r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines
Use unsigned long instead of unsigned for the integer casts here. The
former works for both ILP32 and LP64 programming models, while the
latter fails LP64.
r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines
- Make i/d cache size field 32-bit to prevent overflow
Submited by: Neelkanth Natu
r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines
fix prototype for MipsEmulateBranch.
r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines
Better definitions for a few types for n32/n64.
r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines
Fixed aligned macros...
r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines
- Port busdma code from FreeBSD/arm. This is more mature version
that takes into account all limitation to DMA memory (boundaries,
alignment) and implements bounce pages.
- Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf
r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines
Fix atomic_store_64 prototype for 64-bit systems.
r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines
The MCOUNT macro isn't going to work in 64-bit mode. Add a note to
this effect.
r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines
Provide a macro for PTR_ADDU as well. We may need to implement this
differently for N32... Use PTR_ADDU in DO_AST macro.
r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines
Change the addu here to daddu.
addu paranoina prodded by: jmallet@
r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines
addu and subu are special. We need to use daddu and dsubu here to get
proper behavior.
Submitted by: jmallet@
r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines
The SB1 has cohernet memory, so add it.
Also, Maxmem is better as a long.
Submitted by: Neelkanth Natu
r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines
The SB1 needs a special value for the cache field of the pte.
Submitted by: Neelkanth Natu
r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines
compute the areas to save registers in for 64-bit access correctly.
r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines
First cut at 64-bit types. not 100% sure these are all correct for
N32 ABI.
r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines
Trim unreferenced goo. SDRAM likely should be next, but it is still
referenced.
r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines
First cut at atomics for 64-bit machines and SMP machines.
# Note: Cavium provided a port that has atomics similar to these, but
# that does a syncw; sync; atomic; sync; syncw where we just do the classic
# mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why
# the extra is needed. Since my initial target is one core, I'll defer
# investigation until I bring up multiple cores. syncw is an octeon specific
# instruction.
r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines
Bring in cdefs.h from NetBSD to define ABI goo.
Obtained from: NetBSD
r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines
Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA,
ala sgi, and use it in preference to a bare 'la' so that it gets
translated to a 'dla' for the 64-bit pointer ABIs.
r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines
Use uintptr_t rather than unsigned here for 64-bit correctness.
r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines
Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe
this is correct. While registers are 64-bit, n32 is a 32-bit ABI and
lives in a 32-bit world (with explicit 64-bit registers, however).
Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4
+ SZREG' to reflect the actual offset of the structure in question.
r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines
(1) Use uintptr_t in preference to unsigned. The latter isn't right for
64-bit case, while the former is.
(2) include a SB1 specific coherency mapping
Submitted by: Neelkanth Nath (2)
r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines
db_expr_t should be a intptr_t, not an int. These expressions can be
addresses or numbers, and that's a intptr_t if I ever saw one.
r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines
Define COP0_SYNC for SB1 CPU.
Submitted by: Neelkanth Natu
r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines
Switch to ABI agnostic ta0-ta3. Provide defs for this in the right
places. Provide n32/n64 register name defintions. This should have
no effect for the O32 builds that everybody else uses, but should help
make N64 builds possible (lots of other changes are needed for that).
Obtained from: NetBSD (for the regdef.h changes)
r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines
- Add support for handling TLS area address in kernel space.
From the userland point of view get/set operations are
performed using sysarch(2) call.
r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines
- Add guards to ensure that these files are included only once
r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines
- Mark temp variable as "earlyclobber" in assembler inline in
atomic_fetchadd_32. Without it gcc would use it as input
register for v and sometimes generate following code for
function call like atomic_fetchadd_32(&(fp)->f_count, -1):
801238b4: 2402ffff li v0,-1
801238b8: c2230018 ll v1,24(s1)
801238bc: 00431021 addu v0,v0,v1
801238c0: e2220018 sc v0,24(s1)
801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8>
801238c8: 00000000 nop
Which is definitly wrong because if sc fails v0 is set to 0
and previous value of -1 is overriden hence whole operation
turns to bogus
r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines
bye bye. This is no longer referenced, but much code from it will
resurface for a bus-space implementation.
r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines
Cavium-specific goo is no longer necessary here. Of course, I now
have to write a bus space for cavium, but that shouldn't be too hard.
r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines
Move this to a more approrpiate plae.
r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines
Bring this in from the cavium port.
r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines
- Use restoreintr instead of enableint while accessing pcpu in DO_AST
r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines
- Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default
we assume that there is no FPU, because majority of SoC does
not have it.
r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines
- Add type cast for atomic_cmpset_acq_ptr arguments
r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines
- Remove now unused NetBSDism intr.h
r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines
- Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR
macroses thet check if address belongs to KSEG0, KSEG1 or both
of them respectively.
r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines
- Cast argument to proper type in order to avoid warnings like
"shift value is too large for given type"
r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines
- Use naming convention the same as MIPS spec does: eliminate _sel1 sufix
and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1
- Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes)
r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines
- Define accessor functions for CP0 Config(16) register selects 1, 2, 3.
Content of these registers is defined in MIPS spec and can be used
for obtaining info about CPU capabilities.
r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines
- Make mips_bus_space_generic be of type bus_space_tag_t instead of
struct bus_space and update all relevant places.
r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines
Use FreeBSD/arm approach for handling bus space access: space tag is a pointer
to bus_space structure that defines access methods and hence every bus can
define own accessors. Default space is mips_bus_space_generic. It's a simple
interface to physical memory, values are read with regard to host system
byte order.
2010-01-10 19:50:24 +00:00
|
|
|
/*-
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
* Copyright (c) 1996 Charles M. Hannum. All rights reserved.
|
|
|
|
|
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
|
|
|
|
|
*
|
|
|
|
|
* Redistribution and use in source and binary forms, with or without
|
|
|
|
|
* modification, are permitted provided that the following conditions
|
|
|
|
|
* are met:
|
|
|
|
|
* 1. Redistributions of source code must retain the above copyright
|
|
|
|
|
* notice, this list of conditions and the following disclaimer.
|
|
|
|
|
* 2. Redistributions in binary form must reproduce the above copyright
|
|
|
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
|
|
|
* documentation and/or other materials provided with the distribution.
|
|
|
|
|
* 3. All advertising materials mentioning features or use of this software
|
|
|
|
|
* must display the following acknowledgement:
|
|
|
|
|
* This product includes software developed by Christopher G. Demetriou
|
|
|
|
|
* for the NetBSD Project.
|
|
|
|
|
* 4. The name of the author may not be used to endorse or promote products
|
|
|
|
|
* derived from this software without specific prior written permission
|
|
|
|
|
*
|
|
|
|
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
|
|
|
|
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
|
|
|
|
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
|
|
|
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
|
|
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
|
|
|
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
|
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
|
|
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
|
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
|
|
|
|
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
|
*
|
|
|
|
|
* $FreeBSD$
|
2010-01-10 20:22:05 +00:00
|
|
|
*/
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
|
|
|
|
|
#ifndef _MACHINE_BUS_H_
|
2010-01-10 20:22:05 +00:00
|
|
|
#define _MACHINE_BUS_H_
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
|
|
|
|
|
#include <machine/_bus.h>
|
2010-01-10 20:22:05 +00:00
|
|
|
|
|
|
|
|
struct bus_space {
|
|
|
|
|
/* cookie */
|
|
|
|
|
void *bs_cookie;
|
|
|
|
|
|
|
|
|
|
/* mapping/unmapping */
|
|
|
|
|
int (*bs_map) (void *, bus_addr_t, bus_size_t,
|
|
|
|
|
int, bus_space_handle_t *);
|
|
|
|
|
void (*bs_unmap) (void *, bus_space_handle_t, bus_size_t);
|
|
|
|
|
int (*bs_subregion) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, bus_size_t, bus_space_handle_t *);
|
|
|
|
|
|
|
|
|
|
/* allocation/deallocation */
|
|
|
|
|
int (*bs_alloc) (void *, bus_addr_t, bus_addr_t,
|
|
|
|
|
bus_size_t, bus_size_t, bus_size_t, int,
|
|
|
|
|
bus_addr_t *, bus_space_handle_t *);
|
|
|
|
|
void (*bs_free) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t);
|
|
|
|
|
|
|
|
|
|
/* get kernel virtual address */
|
|
|
|
|
/* barrier */
|
|
|
|
|
void (*bs_barrier) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, bus_size_t, int);
|
|
|
|
|
|
|
|
|
|
/* read (single) */
|
|
|
|
|
u_int8_t (*bs_r_1) (void *, bus_space_handle_t, bus_size_t);
|
|
|
|
|
u_int16_t (*bs_r_2) (void *, bus_space_handle_t, bus_size_t);
|
|
|
|
|
u_int32_t (*bs_r_4) (void *, bus_space_handle_t, bus_size_t);
|
|
|
|
|
u_int64_t (*bs_r_8) (void *, bus_space_handle_t, bus_size_t);
|
|
|
|
|
|
|
|
|
|
/* read multiple */
|
|
|
|
|
void (*bs_rm_1) (void *, bus_space_handle_t, bus_size_t,
|
|
|
|
|
u_int8_t *, bus_size_t);
|
|
|
|
|
void (*bs_rm_2) (void *, bus_space_handle_t, bus_size_t,
|
|
|
|
|
u_int16_t *, bus_size_t);
|
|
|
|
|
void (*bs_rm_4) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int32_t *, bus_size_t);
|
|
|
|
|
void (*bs_rm_8) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int64_t *, bus_size_t);
|
|
|
|
|
|
|
|
|
|
/* read region */
|
|
|
|
|
void (*bs_rr_1) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int8_t *, bus_size_t);
|
|
|
|
|
void (*bs_rr_2) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int16_t *, bus_size_t);
|
|
|
|
|
void (*bs_rr_4) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int32_t *, bus_size_t);
|
|
|
|
|
void (*bs_rr_8) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int64_t *, bus_size_t);
|
|
|
|
|
|
|
|
|
|
/* write (single) */
|
|
|
|
|
void (*bs_w_1) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int8_t);
|
|
|
|
|
void (*bs_w_2) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int16_t);
|
|
|
|
|
void (*bs_w_4) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int32_t);
|
|
|
|
|
void (*bs_w_8) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int64_t);
|
|
|
|
|
|
|
|
|
|
/* write multiple */
|
|
|
|
|
void (*bs_wm_1) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, const u_int8_t *, bus_size_t);
|
|
|
|
|
void (*bs_wm_2) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, const u_int16_t *, bus_size_t);
|
|
|
|
|
void (*bs_wm_4) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, const u_int32_t *, bus_size_t);
|
|
|
|
|
void (*bs_wm_8) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, const u_int64_t *, bus_size_t);
|
|
|
|
|
|
|
|
|
|
/* write region */
|
|
|
|
|
void (*bs_wr_1) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, const u_int8_t *, bus_size_t);
|
|
|
|
|
void (*bs_wr_2) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, const u_int16_t *, bus_size_t);
|
|
|
|
|
void (*bs_wr_4) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, const u_int32_t *, bus_size_t);
|
|
|
|
|
void (*bs_wr_8) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, const u_int64_t *, bus_size_t);
|
|
|
|
|
|
|
|
|
|
/* set multiple */
|
|
|
|
|
void (*bs_sm_1) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int8_t, bus_size_t);
|
|
|
|
|
void (*bs_sm_2) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int16_t, bus_size_t);
|
|
|
|
|
void (*bs_sm_4) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int32_t, bus_size_t);
|
|
|
|
|
void (*bs_sm_8) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int64_t, bus_size_t);
|
|
|
|
|
|
|
|
|
|
/* set region */
|
|
|
|
|
void (*bs_sr_1) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int8_t, bus_size_t);
|
|
|
|
|
void (*bs_sr_2) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int16_t, bus_size_t);
|
|
|
|
|
void (*bs_sr_4) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int32_t, bus_size_t);
|
|
|
|
|
void (*bs_sr_8) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int64_t, bus_size_t);
|
|
|
|
|
|
|
|
|
|
/* copy */
|
|
|
|
|
void (*bs_c_1) (void *, bus_space_handle_t, bus_size_t,
|
|
|
|
|
bus_space_handle_t, bus_size_t, bus_size_t);
|
|
|
|
|
void (*bs_c_2) (void *, bus_space_handle_t, bus_size_t,
|
|
|
|
|
bus_space_handle_t, bus_size_t, bus_size_t);
|
|
|
|
|
void (*bs_c_4) (void *, bus_space_handle_t, bus_size_t,
|
|
|
|
|
bus_space_handle_t, bus_size_t, bus_size_t);
|
|
|
|
|
void (*bs_c_8) (void *, bus_space_handle_t, bus_size_t,
|
|
|
|
|
bus_space_handle_t, bus_size_t, bus_size_t);
|
|
|
|
|
|
|
|
|
|
/* read stream (single) */
|
|
|
|
|
u_int8_t (*bs_r_1_s) (void *, bus_space_handle_t, bus_size_t);
|
|
|
|
|
u_int16_t (*bs_r_2_s) (void *, bus_space_handle_t, bus_size_t);
|
|
|
|
|
u_int32_t (*bs_r_4_s) (void *, bus_space_handle_t, bus_size_t);
|
|
|
|
|
u_int64_t (*bs_r_8_s) (void *, bus_space_handle_t, bus_size_t);
|
|
|
|
|
|
|
|
|
|
/* read multiple stream */
|
|
|
|
|
void (*bs_rm_1_s) (void *, bus_space_handle_t, bus_size_t,
|
|
|
|
|
u_int8_t *, bus_size_t);
|
|
|
|
|
void (*bs_rm_2_s) (void *, bus_space_handle_t, bus_size_t,
|
|
|
|
|
u_int16_t *, bus_size_t);
|
|
|
|
|
void (*bs_rm_4_s) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int32_t *, bus_size_t);
|
|
|
|
|
void (*bs_rm_8_s) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int64_t *, bus_size_t);
|
|
|
|
|
|
|
|
|
|
/* read region stream */
|
|
|
|
|
void (*bs_rr_1_s) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int8_t *, bus_size_t);
|
|
|
|
|
void (*bs_rr_2_s) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int16_t *, bus_size_t);
|
|
|
|
|
void (*bs_rr_4_s) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int32_t *, bus_size_t);
|
|
|
|
|
void (*bs_rr_8_s) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int64_t *, bus_size_t);
|
|
|
|
|
|
|
|
|
|
/* write stream (single) */
|
|
|
|
|
void (*bs_w_1_s) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int8_t);
|
|
|
|
|
void (*bs_w_2_s) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int16_t);
|
|
|
|
|
void (*bs_w_4_s) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int32_t);
|
|
|
|
|
void (*bs_w_8_s) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, u_int64_t);
|
|
|
|
|
|
|
|
|
|
/* write multiple stream */
|
|
|
|
|
void (*bs_wm_1_s) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, const u_int8_t *, bus_size_t);
|
|
|
|
|
void (*bs_wm_2_s) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, const u_int16_t *, bus_size_t);
|
|
|
|
|
void (*bs_wm_4_s) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, const u_int32_t *, bus_size_t);
|
|
|
|
|
void (*bs_wm_8_s) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, const u_int64_t *, bus_size_t);
|
|
|
|
|
|
|
|
|
|
/* write region stream */
|
|
|
|
|
void (*bs_wr_1_s) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, const u_int8_t *, bus_size_t);
|
|
|
|
|
void (*bs_wr_2_s) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, const u_int16_t *, bus_size_t);
|
|
|
|
|
void (*bs_wr_4_s) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, const u_int32_t *, bus_size_t);
|
|
|
|
|
void (*bs_wr_8_s) (void *, bus_space_handle_t,
|
|
|
|
|
bus_size_t, const u_int64_t *, bus_size_t);
|
|
|
|
|
};
|
|
|
|
|
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
|
|
|
|
|
/*
|
2010-01-10 20:22:05 +00:00
|
|
|
* Utility macros; INTERNAL USE ONLY.
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
*/
|
2010-01-10 20:22:05 +00:00
|
|
|
#define __bs_c(a,b) __CONCAT(a,b)
|
|
|
|
|
#define __bs_opname(op,size) __bs_c(__bs_c(__bs_c(bs_,op),_),size)
|
|
|
|
|
|
|
|
|
|
#define __bs_rs(sz, t, h, o) \
|
|
|
|
|
(*(t)->__bs_opname(r,sz))((t)->bs_cookie, h, o)
|
|
|
|
|
#define __bs_ws(sz, t, h, o, v) \
|
|
|
|
|
(*(t)->__bs_opname(w,sz))((t)->bs_cookie, h, o, v)
|
|
|
|
|
#define __bs_nonsingle(type, sz, t, h, o, a, c) \
|
|
|
|
|
(*(t)->__bs_opname(type,sz))((t)->bs_cookie, h, o, a, c)
|
|
|
|
|
#define __bs_set(type, sz, t, h, o, v, c) \
|
|
|
|
|
(*(t)->__bs_opname(type,sz))((t)->bs_cookie, h, o, v, c)
|
|
|
|
|
#define __bs_copy(sz, t, h1, o1, h2, o2, cnt) \
|
|
|
|
|
(*(t)->__bs_opname(c,sz))((t)->bs_cookie, h1, o1, h2, o2, cnt)
|
|
|
|
|
|
|
|
|
|
#define __bs_opname_s(op,size) __bs_c(__bs_c(__bs_c(__bs_c(bs_,op),_),size),_s)
|
|
|
|
|
#define __bs_rs_s(sz, t, h, o) \
|
|
|
|
|
(*(t)->__bs_opname_s(r,sz))((t)->bs_cookie, h, o)
|
|
|
|
|
#define __bs_ws_s(sz, t, h, o, v) \
|
|
|
|
|
(*(t)->__bs_opname_s(w,sz))((t)->bs_cookie, h, o, v)
|
|
|
|
|
#define __bs_nonsingle_s(type, sz, t, h, o, a, c) \
|
|
|
|
|
(*(t)->__bs_opname_s(type,sz))((t)->bs_cookie, h, o, a, c)
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
|
|
|
|
|
|
2010-01-10 20:22:05 +00:00
|
|
|
/*
|
|
|
|
|
* Mapping and unmapping operations.
|
|
|
|
|
*/
|
|
|
|
|
#define bus_space_map(t, a, s, c, hp) \
|
|
|
|
|
(*(t)->bs_map)((t)->bs_cookie, (a), (s), (c), (hp))
|
|
|
|
|
#define bus_space_unmap(t, h, s) \
|
|
|
|
|
(*(t)->bs_unmap)((t)->bs_cookie, (h), (s))
|
|
|
|
|
#define bus_space_subregion(t, h, o, s, hp) \
|
|
|
|
|
(*(t)->bs_subregion)((t)->bs_cookie, (h), (o), (s), (hp))
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
2010-01-10 20:22:05 +00:00
|
|
|
* Allocation and deallocation operations.
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
*/
|
2010-01-10 20:22:05 +00:00
|
|
|
#define bus_space_alloc(t, rs, re, s, a, b, c, ap, hp) \
|
|
|
|
|
(*(t)->bs_alloc)((t)->bs_cookie, (rs), (re), (s), (a), (b), \
|
|
|
|
|
(c), (ap), (hp))
|
|
|
|
|
#define bus_space_free(t, h, s) \
|
|
|
|
|
(*(t)->bs_free)((t)->bs_cookie, (h), (s))
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
|
2010-01-10 20:22:05 +00:00
|
|
|
/*
|
|
|
|
|
* Bus barrier operations.
|
|
|
|
|
*/
|
|
|
|
|
#define bus_space_barrier(t, h, o, l, f) \
|
|
|
|
|
(*(t)->bs_barrier)((t)->bs_cookie, (h), (o), (l), (f))
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
|
2010-01-10 20:22:05 +00:00
|
|
|
#define BUS_SPACE_BARRIER_READ 0x01
|
|
|
|
|
#define BUS_SPACE_BARRIER_WRITE 0x02
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
|
|
|
|
|
/*
|
2010-01-10 20:22:05 +00:00
|
|
|
* Bus read (single) operations.
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
*/
|
2010-01-10 20:22:05 +00:00
|
|
|
#define bus_space_read_1(t, h, o) __bs_rs(1,(t),(h),(o))
|
|
|
|
|
#define bus_space_read_2(t, h, o) __bs_rs(2,(t),(h),(o))
|
|
|
|
|
#define bus_space_read_4(t, h, o) __bs_rs(4,(t),(h),(o))
|
|
|
|
|
#define bus_space_read_8(t, h, o) __bs_rs(8,(t),(h),(o))
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
|
2010-01-10 20:22:05 +00:00
|
|
|
#define bus_space_read_stream_1(t, h, o) __bs_rs_s(1,(t), (h), (o))
|
|
|
|
|
#define bus_space_read_stream_2(t, h, o) __bs_rs_s(2,(t), (h), (o))
|
|
|
|
|
#define bus_space_read_stream_4(t, h, o) __bs_rs_s(4,(t), (h), (o))
|
|
|
|
|
#define bus_space_read_stream_8(t, h, o) __bs_rs_s(8,8,(t),(h),(o))
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
|
|
|
|
|
/*
|
2010-01-10 20:22:05 +00:00
|
|
|
* Bus read multiple operations.
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
*/
|
2010-01-10 20:22:05 +00:00
|
|
|
#define bus_space_read_multi_1(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle(rm,1,(t),(h),(o),(a),(c))
|
|
|
|
|
#define bus_space_read_multi_2(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle(rm,2,(t),(h),(o),(a),(c))
|
|
|
|
|
#define bus_space_read_multi_4(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle(rm,4,(t),(h),(o),(a),(c))
|
|
|
|
|
#define bus_space_read_multi_8(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle(rm,8,(t),(h),(o),(a),(c))
|
|
|
|
|
|
|
|
|
|
#define bus_space_read_multi_stream_1(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle_s(rm,1,(t),(h),(o),(a),(c))
|
|
|
|
|
#define bus_space_read_multi_stream_2(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle_s(rm,2,(t),(h),(o),(a),(c))
|
|
|
|
|
#define bus_space_read_multi_stream_4(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle_s(rm,4,(t),(h),(o),(a),(c))
|
|
|
|
|
#define bus_space_read_multi_stream_8(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle_s(rm,8,(t),(h),(o),(a),(c))
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
2010-01-10 20:22:05 +00:00
|
|
|
* Bus read region operations.
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
*/
|
2010-01-10 20:22:05 +00:00
|
|
|
#define bus_space_read_region_1(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle(rr,1,(t),(h),(o),(a),(c))
|
|
|
|
|
#define bus_space_read_region_2(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle(rr,2,(t),(h),(o),(a),(c))
|
|
|
|
|
#define bus_space_read_region_4(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle(rr,4,(t),(h),(o),(a),(c))
|
|
|
|
|
#define bus_space_read_region_8(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle(rr,8,(t),(h),(o),(a),(c))
|
|
|
|
|
|
|
|
|
|
#define bus_space_read_region_stream_1(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle_s(rr,1,(t),(h),(o),(a),(c))
|
|
|
|
|
#define bus_space_read_region_stream_2(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle_s(rr,2,(t),(h),(o),(a),(c))
|
|
|
|
|
#define bus_space_read_region_stream_4(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle_s(rr,4,(t),(h),(o),(a),(c))
|
|
|
|
|
#define bus_space_read_region_stream_8(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle_s(rr,8,(t),(h),(o),(a),(c))
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
2010-01-10 20:22:05 +00:00
|
|
|
* Bus write (single) operations.
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
*/
|
2010-01-10 20:22:05 +00:00
|
|
|
#define bus_space_write_1(t, h, o, v) __bs_ws(1,(t),(h),(o),(v))
|
|
|
|
|
#define bus_space_write_2(t, h, o, v) __bs_ws(2,(t),(h),(o),(v))
|
|
|
|
|
#define bus_space_write_4(t, h, o, v) __bs_ws(4,(t),(h),(o),(v))
|
|
|
|
|
#define bus_space_write_8(t, h, o, v) __bs_ws(8,(t),(h),(o),(v))
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
|
2010-01-10 20:22:05 +00:00
|
|
|
#define bus_space_write_stream_1(t, h, o, v) __bs_ws_s(1,(t),(h),(o),(v))
|
|
|
|
|
#define bus_space_write_stream_2(t, h, o, v) __bs_ws_s(2,(t),(h),(o),(v))
|
|
|
|
|
#define bus_space_write_stream_4(t, h, o, v) __bs_ws_s(4,(t),(h),(o),(v))
|
|
|
|
|
#define bus_space_write_stream_8(t, h, o, v) __bs_ws_s(8,(t),(h),(o),(v))
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
2010-01-10 20:22:05 +00:00
|
|
|
* Bus write multiple operations.
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
*/
|
2010-01-10 20:22:05 +00:00
|
|
|
#define bus_space_write_multi_1(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle(wm,1,(t),(h),(o),(a),(c))
|
|
|
|
|
#define bus_space_write_multi_2(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle(wm,2,(t),(h),(o),(a),(c))
|
|
|
|
|
#define bus_space_write_multi_4(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle(wm,4,(t),(h),(o),(a),(c))
|
|
|
|
|
#define bus_space_write_multi_8(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle(wm,8,(t),(h),(o),(a),(c))
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
|
2010-01-10 20:22:05 +00:00
|
|
|
#define bus_space_write_multi_stream_1(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle_s(wm,1,(t),(h),(o),(a),(c))
|
|
|
|
|
#define bus_space_write_multi_stream_2(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle_s(wm,2,(t),(h),(o),(a),(c))
|
|
|
|
|
#define bus_space_write_multi_stream_4(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle_s(wm,4,(t),(h),(o),(a),(c))
|
|
|
|
|
#define bus_space_write_multi_stream_8(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle_s(wm,8,(t),(h),(o),(a),(c))
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
2010-01-10 20:22:05 +00:00
|
|
|
* Bus write region operations.
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
*/
|
2010-01-10 20:22:05 +00:00
|
|
|
#define bus_space_write_region_1(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle(wr,1,(t),(h),(o),(a),(c))
|
|
|
|
|
#define bus_space_write_region_2(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle(wr,2,(t),(h),(o),(a),(c))
|
|
|
|
|
#define bus_space_write_region_4(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle(wr,4,(t),(h),(o),(a),(c))
|
|
|
|
|
#define bus_space_write_region_8(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle(wr,8,(t),(h),(o),(a),(c))
|
|
|
|
|
|
|
|
|
|
#define bus_space_write_region_stream_1(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle_s(wr,1,(t),(h),(o),(a),(c))
|
|
|
|
|
#define bus_space_write_region_stream_2(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle_s(wr,2,(t),(h),(o),(a),(c))
|
|
|
|
|
#define bus_space_write_region_stream_4(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle_s(wr,4,(t),(h),(o),(a),(c))
|
|
|
|
|
#define bus_space_write_region_stream_8(t, h, o, a, c) \
|
|
|
|
|
__bs_nonsingle_s(wr,8,(t),(h),(o),(a),(c))
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
2010-01-10 20:22:05 +00:00
|
|
|
* Set multiple operations.
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
*/
|
2010-12-03 07:09:23 +00:00
|
|
|
#define bus_space_set_multi_1(t, h, o, v, c) \
|
2010-01-10 20:22:05 +00:00
|
|
|
__bs_set(sm,1,(t),(h),(o),(v),(c))
|
2010-12-03 07:09:23 +00:00
|
|
|
#define bus_space_set_multi_2(t, h, o, v, c) \
|
2010-01-10 20:22:05 +00:00
|
|
|
__bs_set(sm,2,(t),(h),(o),(v),(c))
|
2010-12-03 07:09:23 +00:00
|
|
|
#define bus_space_set_multi_4(t, h, o, v, c) \
|
2010-01-10 20:22:05 +00:00
|
|
|
__bs_set(sm,4,(t),(h),(o),(v),(c))
|
2010-12-03 07:09:23 +00:00
|
|
|
#define bus_space_set_multi_8(t, h, o, v, c) \
|
2010-01-10 20:22:05 +00:00
|
|
|
__bs_set(sm,8,(t),(h),(o),(v),(c))
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
2010-01-10 20:22:05 +00:00
|
|
|
* Set region operations.
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
*/
|
2010-01-10 20:22:05 +00:00
|
|
|
#define bus_space_set_region_1(t, h, o, v, c) \
|
|
|
|
|
__bs_set(sr,1,(t),(h),(o),(v),(c))
|
|
|
|
|
#define bus_space_set_region_2(t, h, o, v, c) \
|
|
|
|
|
__bs_set(sr,2,(t),(h),(o),(v),(c))
|
|
|
|
|
#define bus_space_set_region_4(t, h, o, v, c) \
|
|
|
|
|
__bs_set(sr,4,(t),(h),(o),(v),(c))
|
|
|
|
|
#define bus_space_set_region_8(t, h, o, v, c) \
|
|
|
|
|
__bs_set(sr,8,(t),(h),(o),(v),(c))
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
2010-01-10 20:22:05 +00:00
|
|
|
* Copy operations.
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
*/
|
2010-12-03 07:09:23 +00:00
|
|
|
#define bus_space_copy_region_1(t, h1, o1, h2, o2, c) \
|
2010-01-10 20:22:05 +00:00
|
|
|
__bs_copy(1, t, h1, o1, h2, o2, c)
|
2010-12-03 07:09:23 +00:00
|
|
|
#define bus_space_copy_region_2(t, h1, o1, h2, o2, c) \
|
2010-01-10 20:22:05 +00:00
|
|
|
__bs_copy(2, t, h1, o1, h2, o2, c)
|
2010-12-03 07:09:23 +00:00
|
|
|
#define bus_space_copy_region_4(t, h1, o1, h2, o2, c) \
|
2010-01-10 20:22:05 +00:00
|
|
|
__bs_copy(4, t, h1, o1, h2, o2, c)
|
2010-12-03 07:09:23 +00:00
|
|
|
#define bus_space_copy_region_8(t, h1, o1, h2, o2, c) \
|
2010-01-10 20:22:05 +00:00
|
|
|
__bs_copy(8, t, h1, o1, h2, o2, c)
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
|
|
|
|
|
/*
|
2010-01-10 20:22:05 +00:00
|
|
|
* Macros to provide prototypes for all the functions used in the
|
|
|
|
|
* bus_space structure
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
*/
|
|
|
|
|
|
2010-01-10 20:22:05 +00:00
|
|
|
#define bs_map_proto(f) \
|
|
|
|
|
int __bs_c(f,_bs_map) (void *t, bus_addr_t addr, \
|
|
|
|
|
bus_size_t size, int cacheable, bus_space_handle_t *bshp);
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
|
2010-01-10 20:22:05 +00:00
|
|
|
#define bs_unmap_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_unmap) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t size);
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
|
2010-01-10 20:22:05 +00:00
|
|
|
#define bs_subregion_proto(f) \
|
|
|
|
|
int __bs_c(f,_bs_subregion) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, bus_size_t size, \
|
|
|
|
|
bus_space_handle_t *nbshp);
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
|
2010-01-10 20:22:05 +00:00
|
|
|
#define bs_alloc_proto(f) \
|
|
|
|
|
int __bs_c(f,_bs_alloc) (void *t, bus_addr_t rstart, \
|
|
|
|
|
bus_addr_t rend, bus_size_t size, bus_size_t align, \
|
|
|
|
|
bus_size_t boundary, int cacheable, bus_addr_t *addrp, \
|
|
|
|
|
bus_space_handle_t *bshp);
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
|
2010-01-10 20:22:05 +00:00
|
|
|
#define bs_free_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_free) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t size);
|
|
|
|
|
|
|
|
|
|
#define bs_barrier_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_barrier) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, bus_size_t len, int flags);
|
|
|
|
|
|
|
|
|
|
#define bs_r_1_proto(f) \
|
|
|
|
|
u_int8_t __bs_c(f,_bs_r_1) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset);
|
|
|
|
|
|
|
|
|
|
#define bs_r_2_proto(f) \
|
|
|
|
|
u_int16_t __bs_c(f,_bs_r_2) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset);
|
|
|
|
|
|
|
|
|
|
#define bs_r_4_proto(f) \
|
|
|
|
|
u_int32_t __bs_c(f,_bs_r_4) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset);
|
|
|
|
|
|
|
|
|
|
#define bs_r_8_proto(f) \
|
|
|
|
|
u_int64_t __bs_c(f,_bs_r_8) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset);
|
|
|
|
|
|
|
|
|
|
#define bs_r_1_s_proto(f) \
|
|
|
|
|
u_int8_t __bs_c(f,_bs_r_1_s) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset);
|
|
|
|
|
|
|
|
|
|
#define bs_r_2_s_proto(f) \
|
|
|
|
|
u_int16_t __bs_c(f,_bs_r_2_s) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset);
|
|
|
|
|
|
|
|
|
|
#define bs_r_4_s_proto(f) \
|
|
|
|
|
u_int32_t __bs_c(f,_bs_r_4_s) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset);
|
|
|
|
|
|
|
|
|
|
#define bs_w_1_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_w_1) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, u_int8_t value);
|
|
|
|
|
|
|
|
|
|
#define bs_w_2_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_w_2) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, u_int16_t value);
|
|
|
|
|
|
|
|
|
|
#define bs_w_4_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_w_4) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, u_int32_t value);
|
|
|
|
|
|
|
|
|
|
#define bs_w_8_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_w_8) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, u_int64_t value);
|
|
|
|
|
|
|
|
|
|
#define bs_w_1_s_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_w_1_s) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, u_int8_t value);
|
|
|
|
|
|
|
|
|
|
#define bs_w_2_s_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_w_2_s) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, u_int16_t value);
|
|
|
|
|
|
|
|
|
|
#define bs_w_4_s_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_w_4_s) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, u_int32_t value);
|
|
|
|
|
|
|
|
|
|
#define bs_rm_1_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_rm_1) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, u_int8_t *addr, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define bs_rm_2_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_rm_2) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, u_int16_t *addr, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define bs_rm_4_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_rm_4) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, u_int32_t *addr, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define bs_rm_8_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_rm_8) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, u_int64_t *addr, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define bs_wm_1_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_wm_1) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, const u_int8_t *addr, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define bs_wm_2_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_wm_2) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, const u_int16_t *addr, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define bs_wm_4_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_wm_4) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, const u_int32_t *addr, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define bs_wm_8_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_wm_8) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, const u_int64_t *addr, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define bs_rr_1_proto(f) \
|
|
|
|
|
void __bs_c(f, _bs_rr_1) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, u_int8_t *addr, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define bs_rr_2_proto(f) \
|
|
|
|
|
void __bs_c(f, _bs_rr_2) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, u_int16_t *addr, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define bs_rr_4_proto(f) \
|
|
|
|
|
void __bs_c(f, _bs_rr_4) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, u_int32_t *addr, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define bs_rr_8_proto(f) \
|
|
|
|
|
void __bs_c(f, _bs_rr_8) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, u_int64_t *addr, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define bs_wr_1_proto(f) \
|
|
|
|
|
void __bs_c(f, _bs_wr_1) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, const u_int8_t *addr, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define bs_wr_2_proto(f) \
|
|
|
|
|
void __bs_c(f, _bs_wr_2) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, const u_int16_t *addr, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define bs_wr_4_proto(f) \
|
|
|
|
|
void __bs_c(f, _bs_wr_4) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, const u_int32_t *addr, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define bs_wr_8_proto(f) \
|
|
|
|
|
void __bs_c(f, _bs_wr_8) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, const u_int64_t *addr, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define bs_sm_1_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_sm_1) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, u_int8_t value, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define bs_sm_2_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_sm_2) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, u_int16_t value, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define bs_sm_4_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_sm_4) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, u_int32_t value, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define bs_sm_8_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_sm_8) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, u_int64_t value, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define bs_sr_1_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_sr_1) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, u_int8_t value, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define bs_sr_2_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_sr_2) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, u_int16_t value, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define bs_sr_4_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_sr_4) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, u_int32_t value, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define bs_sr_8_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_sr_8) (void *t, bus_space_handle_t bsh, \
|
|
|
|
|
bus_size_t offset, u_int64_t value, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define bs_c_1_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_c_1) (void *t, bus_space_handle_t bsh1, \
|
|
|
|
|
bus_size_t offset1, bus_space_handle_t bsh2, \
|
|
|
|
|
bus_size_t offset2, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define bs_c_2_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_c_2) (void *t, bus_space_handle_t bsh1, \
|
|
|
|
|
bus_size_t offset1, bus_space_handle_t bsh2, \
|
|
|
|
|
bus_size_t offset2, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define bs_c_4_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_c_4) (void *t, bus_space_handle_t bsh1, \
|
|
|
|
|
bus_size_t offset1, bus_space_handle_t bsh2, \
|
|
|
|
|
bus_size_t offset2, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define bs_c_8_proto(f) \
|
|
|
|
|
void __bs_c(f,_bs_c_8) (void *t, bus_space_handle_t bsh1, \
|
|
|
|
|
bus_size_t offset1, bus_space_handle_t bsh2, \
|
|
|
|
|
bus_size_t offset2, bus_size_t count);
|
|
|
|
|
|
|
|
|
|
#define DECLARE_BUS_SPACE_PROTOTYPES(f) \
|
|
|
|
|
bs_map_proto(f); \
|
|
|
|
|
bs_unmap_proto(f); \
|
|
|
|
|
bs_subregion_proto(f); \
|
|
|
|
|
bs_alloc_proto(f); \
|
|
|
|
|
bs_free_proto(f); \
|
|
|
|
|
bs_barrier_proto(f); \
|
|
|
|
|
bs_r_1_proto(f); \
|
|
|
|
|
bs_r_2_proto(f); \
|
|
|
|
|
bs_r_4_proto(f); \
|
|
|
|
|
bs_r_8_proto(f); \
|
|
|
|
|
bs_r_1_s_proto(f); \
|
|
|
|
|
bs_r_2_s_proto(f); \
|
|
|
|
|
bs_r_4_s_proto(f); \
|
|
|
|
|
bs_w_1_proto(f); \
|
|
|
|
|
bs_w_2_proto(f); \
|
|
|
|
|
bs_w_4_proto(f); \
|
|
|
|
|
bs_w_8_proto(f); \
|
|
|
|
|
bs_w_1_s_proto(f); \
|
|
|
|
|
bs_w_2_s_proto(f); \
|
|
|
|
|
bs_w_4_s_proto(f); \
|
|
|
|
|
bs_rm_1_proto(f); \
|
|
|
|
|
bs_rm_2_proto(f); \
|
|
|
|
|
bs_rm_4_proto(f); \
|
|
|
|
|
bs_rm_8_proto(f); \
|
|
|
|
|
bs_wm_1_proto(f); \
|
|
|
|
|
bs_wm_2_proto(f); \
|
|
|
|
|
bs_wm_4_proto(f); \
|
|
|
|
|
bs_wm_8_proto(f); \
|
|
|
|
|
bs_rr_1_proto(f); \
|
|
|
|
|
bs_rr_2_proto(f); \
|
|
|
|
|
bs_rr_4_proto(f); \
|
|
|
|
|
bs_rr_8_proto(f); \
|
|
|
|
|
bs_wr_1_proto(f); \
|
|
|
|
|
bs_wr_2_proto(f); \
|
|
|
|
|
bs_wr_4_proto(f); \
|
|
|
|
|
bs_wr_8_proto(f); \
|
|
|
|
|
bs_sm_1_proto(f); \
|
|
|
|
|
bs_sm_2_proto(f); \
|
|
|
|
|
bs_sm_4_proto(f); \
|
|
|
|
|
bs_sm_8_proto(f); \
|
|
|
|
|
bs_sr_1_proto(f); \
|
|
|
|
|
bs_sr_2_proto(f); \
|
|
|
|
|
bs_sr_4_proto(f); \
|
|
|
|
|
bs_sr_8_proto(f); \
|
|
|
|
|
bs_c_1_proto(f); \
|
|
|
|
|
bs_c_2_proto(f); \
|
|
|
|
|
bs_c_4_proto(f); \
|
|
|
|
|
bs_c_8_proto(f);
|
|
|
|
|
|
|
|
|
|
#define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
|
|
|
|
|
|
|
|
|
|
#define BUS_SPACE_MAXADDR_24BIT 0xFFFFFF
|
|
|
|
|
#define BUS_SPACE_MAXSIZE_24BIT 0xFFFFFF
|
2012-03-12 18:56:16 +00:00
|
|
|
|
|
|
|
|
#define BUS_SPACE_MAXADDR_32BIT 0xFFFFFFFF
|
2010-01-10 20:22:05 +00:00
|
|
|
#define BUS_SPACE_MAXSIZE_32BIT 0xFFFFFFFF
|
2012-03-12 18:56:16 +00:00
|
|
|
|
|
|
|
|
#if defined(__mips_n64)
|
|
|
|
|
#define BUS_SPACE_MAXADDR 0xFFFFFFFFFFFFFFFFUL
|
|
|
|
|
#define BUS_SPACE_MAXSIZE 0xFFFFFFFFFFFFFFFFUL
|
|
|
|
|
#else
|
|
|
|
|
#define BUS_SPACE_MAXADDR 0xFFFFFFFFUL
|
|
|
|
|
#define BUS_SPACE_MAXSIZE 0xFFFFFFFFUL
|
|
|
|
|
#endif
|
|
|
|
|
|
2010-01-10 20:22:05 +00:00
|
|
|
|
2010-04-08 19:34:55 +00:00
|
|
|
#define BUS_SPACE_UNRESTRICTED (~0)
|
|
|
|
|
|
2010-01-10 20:22:05 +00:00
|
|
|
/*
|
|
|
|
|
* declare generic bus space, it suits all needs in
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
*/
|
2010-01-10 20:22:05 +00:00
|
|
|
DECLARE_BUS_SPACE_PROTOTYPES(generic);
|
|
|
|
|
extern bus_space_tag_t mips_bus_space_generic;
|
2013-01-12 15:58:20 +00:00
|
|
|
|
2010-01-10 20:22:05 +00:00
|
|
|
/* Special bus space for RMI processors */
|
2011-07-16 20:31:29 +00:00
|
|
|
#if defined(CPU_RMI) || defined (CPU_NLM)
|
2010-01-10 20:22:05 +00:00
|
|
|
extern bus_space_tag_t rmi_bus_space;
|
2010-03-02 12:11:00 +00:00
|
|
|
extern bus_space_tag_t rmi_pci_bus_space;
|
2011-10-18 08:10:23 +00:00
|
|
|
extern bus_space_tag_t rmi_uart_bus_space;
|
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:27:37 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#include <machine/bus_dma.h>
|
|
|
|
|
|
2010-01-10 20:22:05 +00:00
|
|
|
#endif /* _MACHINE_BUS_H_ */
|
