2015-03-31 11:50:46 +00:00
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/*-
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* Copyright 2013-2015 John Wehle <john@feith.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Amlogic aml8726 UART driver.
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*
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* The current implementation only targets features common to all
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* uarts. For example ... though UART A as a 128 byte FIFO, the
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* others only have a 64 byte FIFO.
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*
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2015-05-06 01:07:59 +00:00
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* Also, it's assumed that the USE_XTAL_CLK feature (available on
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* the aml8726-m6 and later) has not been activated.
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2015-03-31 11:50:46 +00:00
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/sysctl.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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2015-04-11 08:34:41 +00:00
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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2015-03-31 11:50:46 +00:00
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#include <dev/uart/uart.h>
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#include <dev/uart/uart_cpu.h>
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#include <dev/uart/uart_cpu_fdt.h>
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#include <dev/uart/uart_bus.h>
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2015-05-06 01:07:59 +00:00
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#include <arm/amlogic/aml8726/aml8726_soc.h>
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2015-03-31 11:50:46 +00:00
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#include <arm/amlogic/aml8726/aml8726_uart.h>
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#include "uart_if.h"
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#undef uart_getreg
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#undef uart_setreg
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#define uart_getreg(bas, reg) \
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bus_space_read_4((bas)->bst, (bas)->bsh, reg)
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#define uart_setreg(bas, reg, value) \
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bus_space_write_4((bas)->bst, (bas)->bsh, reg, value)
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#define SIGCHG(c, i, s, d) \
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do { \
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if (c) { \
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i |= (i & s) ? s : s | d; \
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} else { \
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i = (i & s) ? (i & ~s) | d : i; \
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} \
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} while (0)
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static int
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aml8726_uart_divisor(int rclk, int baudrate)
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{
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int actual_baud, divisor;
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int error;
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if (baudrate == 0)
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return (0);
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/* integer version of (rclk / baudrate + .5) */
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divisor = ((rclk << 1) + baudrate) / (baudrate << 1);
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2015-05-06 01:07:59 +00:00
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if (divisor == 0)
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2015-03-31 11:50:46 +00:00
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return (0);
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actual_baud = rclk / divisor;
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/* 10 times error in percent: */
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error = (((actual_baud - baudrate) * 2000) / baudrate + 1) >> 1;
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/* 3.0% maximum error tolerance: */
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if (error < -30 || error > 30)
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return (0);
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return (divisor);
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}
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static int
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aml8726_uart_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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uint32_t cr;
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uint32_t mr;
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2015-05-06 01:07:59 +00:00
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uint32_t nbr;
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2015-03-31 11:50:46 +00:00
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int divisor;
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cr = uart_getreg(bas, AML_UART_CONTROL_REG);
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cr &= ~(AML_UART_CONTROL_DB_MASK | AML_UART_CONTROL_SB_MASK |
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AML_UART_CONTROL_P_MASK);
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switch (databits) {
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case 5: cr |= AML_UART_CONTROL_5_DB; break;
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case 6: cr |= AML_UART_CONTROL_6_DB; break;
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case 7: cr |= AML_UART_CONTROL_7_DB; break;
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case 8: cr |= AML_UART_CONTROL_8_DB; break;
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default: return (EINVAL);
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}
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switch (stopbits) {
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case 1: cr |= AML_UART_CONTROL_1_SB; break;
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case 2: cr |= AML_UART_CONTROL_2_SB; break;
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default: return (EINVAL);
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}
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switch (parity) {
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case UART_PARITY_EVEN: cr |= AML_UART_CONTROL_P_EVEN;
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cr |= AML_UART_CONTROL_P_EN;
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break;
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case UART_PARITY_ODD: cr |= AML_UART_CONTROL_P_ODD;
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cr |= AML_UART_CONTROL_P_EN;
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break;
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case UART_PARITY_NONE: break;
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default: return (EINVAL);
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}
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/* Set baudrate. */
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if (baudrate > 0 && bas->rclk != 0) {
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divisor = aml8726_uart_divisor(bas->rclk / 4, baudrate) - 1;
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2015-05-06 01:07:59 +00:00
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switch (aml8726_soc_hw_rev) {
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case AML_SOC_HW_REV_M6:
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case AML_SOC_HW_REV_M8:
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case AML_SOC_HW_REV_M8B:
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if (divisor > (AML_UART_NEW_BAUD_RATE_MASK >>
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AML_UART_NEW_BAUD_RATE_SHIFT))
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return (EINVAL);
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nbr = uart_getreg(bas, AML_UART_NEW_BAUD_REG);
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nbr &= ~(AML_UART_NEW_BAUD_USE_XTAL_CLK |
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AML_UART_NEW_BAUD_RATE_MASK);
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nbr |= AML_UART_NEW_BAUD_RATE_EN |
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(divisor << AML_UART_NEW_BAUD_RATE_SHIFT);
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uart_setreg(bas, AML_UART_NEW_BAUD_REG, nbr);
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divisor = 0;
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break;
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default:
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if (divisor > 0xffff)
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return (EINVAL);
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break;
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}
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2015-03-31 11:50:46 +00:00
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cr &= ~AML_UART_CONTROL_BAUD_MASK;
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cr |= (divisor & AML_UART_CONTROL_BAUD_MASK);
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divisor >>= AML_UART_CONTROL_BAUD_WIDTH;
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mr = uart_getreg(bas, AML_UART_MISC_REG);
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mr &= ~(AML_UART_MISC_OLD_RX_BAUD |
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AML_UART_MISC_BAUD_EXT_MASK);
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mr |= ((divisor << AML_UART_MISC_BAUD_EXT_SHIFT) &
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AML_UART_MISC_BAUD_EXT_MASK);
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uart_setreg(bas, AML_UART_MISC_REG, mr);
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}
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uart_setreg(bas, AML_UART_CONTROL_REG, cr);
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uart_barrier(bas);
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return (0);
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}
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/*
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* Low-level UART interface.
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*/
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static int
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aml8726_uart_probe(struct uart_bas *bas)
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{
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return (0);
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}
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static void
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aml8726_uart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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uint32_t cr;
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uint32_t mr;
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2015-05-06 01:07:59 +00:00
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(void)aml8726_uart_param(bas, baudrate, databits, stopbits, parity);
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2015-03-31 11:50:46 +00:00
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cr = uart_getreg(bas, AML_UART_CONTROL_REG);
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/* Disable all interrupt sources. */
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cr &= ~(AML_UART_CONTROL_TX_INT_EN | AML_UART_CONTROL_RX_INT_EN);
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/* Reset the transmitter and receiver. */
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cr |= (AML_UART_CONTROL_TX_RST | AML_UART_CONTROL_RX_RST);
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/* Enable the transmitter and receiver. */
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cr |= (AML_UART_CONTROL_TX_EN | AML_UART_CONTROL_RX_EN);
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uart_setreg(bas, AML_UART_CONTROL_REG, cr);
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uart_barrier(bas);
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/* Clear RX FIFO level for generating interrupts. */
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mr = uart_getreg(bas, AML_UART_MISC_REG);
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mr &= ~AML_UART_MISC_RECV_IRQ_CNT_MASK;
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uart_setreg(bas, AML_UART_MISC_REG, mr);
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uart_barrier(bas);
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/* Ensure the reset bits are clear. */
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cr &= ~(AML_UART_CONTROL_TX_RST | AML_UART_CONTROL_RX_RST);
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uart_setreg(bas, AML_UART_CONTROL_REG, cr);
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uart_barrier(bas);
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}
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static void
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aml8726_uart_term(struct uart_bas *bas)
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{
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}
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static void
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aml8726_uart_putc(struct uart_bas *bas, int c)
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{
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while ((uart_getreg(bas, AML_UART_STATUS_REG) &
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AML_UART_STATUS_TX_FIFO_FULL) != 0)
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cpu_spinwait();
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uart_setreg(bas, AML_UART_WFIFO_REG, c);
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uart_barrier(bas);
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}
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static int
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aml8726_uart_rxready(struct uart_bas *bas)
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{
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return ((uart_getreg(bas, AML_UART_STATUS_REG) &
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AML_UART_STATUS_RX_FIFO_EMPTY) == 0 ? 1 : 0);
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}
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static int
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aml8726_uart_getc(struct uart_bas *bas, struct mtx *hwmtx)
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{
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int c;
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uart_lock(hwmtx);
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while ((uart_getreg(bas, AML_UART_STATUS_REG) &
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AML_UART_STATUS_RX_FIFO_EMPTY) != 0) {
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uart_unlock(hwmtx);
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DELAY(4);
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uart_lock(hwmtx);
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}
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c = uart_getreg(bas, AML_UART_RFIFO_REG) & 0xff;
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uart_unlock(hwmtx);
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return (c);
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}
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struct uart_ops aml8726_uart_ops = {
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.probe = aml8726_uart_probe,
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.init = aml8726_uart_init,
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.term = aml8726_uart_term,
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.putc = aml8726_uart_putc,
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.rxready = aml8726_uart_rxready,
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.getc = aml8726_uart_getc,
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};
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2015-04-11 08:34:41 +00:00
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static unsigned int
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aml8726_uart_bus_clk(phandle_t node)
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{
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pcell_t prop;
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ssize_t len;
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phandle_t clk_node;
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len = OF_getencprop(node, "clocks", &prop, sizeof(prop));
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if ((len / sizeof(prop)) != 1 || prop == 0 ||
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(clk_node = OF_node_from_xref(prop)) == 0)
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return (0);
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len = OF_getencprop(clk_node, "clock-frequency", &prop, sizeof(prop));
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if ((len / sizeof(prop)) != 1 || prop == 0)
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return (0);
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return ((unsigned int)prop);
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}
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2015-03-31 11:50:46 +00:00
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static int
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aml8726_uart_bus_probe(struct uart_softc *sc)
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{
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int error;
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error = aml8726_uart_probe(&sc->sc_bas);
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if (error)
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return (error);
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sc->sc_rxfifosz = 64;
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sc->sc_txfifosz = 64;
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sc->sc_hwiflow = 1;
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sc->sc_hwoflow = 1;
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device_set_desc(sc->sc_dev, "Amlogic aml8726 UART");
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return (0);
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}
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static int
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aml8726_uart_bus_getsig(struct uart_softc *sc)
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{
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uint32_t new, old, sig;
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/*
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* Treat DSR, DCD, and CTS as always on.
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*/
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do {
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old = sc->sc_hwsig;
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sig = old;
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SIGCHG(1, sig, SER_DSR, SER_DDSR);
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SIGCHG(1, sig, SER_DCD, SER_DDCD);
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SIGCHG(1, sig, SER_CTS, SER_DCTS);
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new = sig & ~SER_MASK_DELTA;
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} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
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return (sig);
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}
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static int
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aml8726_uart_bus_setsig(struct uart_softc *sc, int sig)
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{
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uint32_t new, old;
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do {
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old = sc->sc_hwsig;
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new = old;
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if (sig & SER_DDTR) {
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SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR);
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}
|
|
|
|
if (sig & SER_DRTS) {
|
|
|
|
SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS);
|
|
|
|
}
|
|
|
|
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
aml8726_uart_bus_attach(struct uart_softc *sc)
|
|
|
|
{
|
|
|
|
struct uart_bas *bas;
|
|
|
|
uint32_t cr;
|
|
|
|
uint32_t mr;
|
|
|
|
|
|
|
|
bas = &sc->sc_bas;
|
|
|
|
|
2015-04-11 08:34:41 +00:00
|
|
|
bas->rclk = aml8726_uart_bus_clk(ofw_bus_get_node(sc->sc_dev));
|
|
|
|
|
2015-03-31 11:50:46 +00:00
|
|
|
if (bas->rclk == 0) {
|
2015-04-11 08:34:41 +00:00
|
|
|
device_printf(sc->sc_dev, "missing clocks attribute in FDT\n");
|
2015-03-31 11:50:46 +00:00
|
|
|
return (ENXIO);
|
|
|
|
}
|
|
|
|
|
|
|
|
cr = uart_getreg(bas, AML_UART_CONTROL_REG);
|
|
|
|
/* Disable all interrupt sources. */
|
|
|
|
cr &= ~(AML_UART_CONTROL_TX_INT_EN | AML_UART_CONTROL_RX_INT_EN);
|
|
|
|
/* Ensure the reset bits are clear. */
|
|
|
|
cr &= ~(AML_UART_CONTROL_TX_RST | AML_UART_CONTROL_RX_RST);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Reset the transmitter and receiver only if not acting as a
|
|
|
|
* console, otherwise it means that:
|
|
|
|
*
|
|
|
|
* 1) aml8726_uart_init was already called which did the reset
|
|
|
|
*
|
|
|
|
* 2) there may be console bytes sitting in the transmit fifo
|
|
|
|
*/
|
|
|
|
if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE)
|
|
|
|
;
|
|
|
|
else
|
|
|
|
cr |= (AML_UART_CONTROL_TX_RST | AML_UART_CONTROL_RX_RST);
|
|
|
|
|
|
|
|
/* Default to two wire mode. */
|
|
|
|
cr |= AML_UART_CONTROL_TWO_WIRE_EN;
|
|
|
|
/* Enable the transmitter and receiver. */
|
|
|
|
cr |= (AML_UART_CONTROL_TX_EN | AML_UART_CONTROL_RX_EN);
|
|
|
|
/* Reset error bits. */
|
|
|
|
cr |= AML_UART_CONTROL_CLR_ERR;
|
|
|
|
uart_setreg(bas, AML_UART_CONTROL_REG, cr);
|
|
|
|
uart_barrier(bas);
|
|
|
|
|
|
|
|
/* Set FIFO levels for generating interrupts. */
|
|
|
|
mr = uart_getreg(bas, AML_UART_MISC_REG);
|
|
|
|
mr &= ~AML_UART_MISC_XMIT_IRQ_CNT_MASK;
|
|
|
|
mr |= (0 << AML_UART_MISC_XMIT_IRQ_CNT_SHIFT);
|
|
|
|
mr &= ~AML_UART_MISC_RECV_IRQ_CNT_MASK;
|
|
|
|
mr |= (1 << AML_UART_MISC_RECV_IRQ_CNT_SHIFT);
|
|
|
|
uart_setreg(bas, AML_UART_MISC_REG, mr);
|
|
|
|
uart_barrier(bas);
|
|
|
|
|
|
|
|
aml8726_uart_bus_getsig(sc);
|
|
|
|
|
|
|
|
/* Ensure the reset bits are clear. */
|
|
|
|
cr &= ~(AML_UART_CONTROL_TX_RST | AML_UART_CONTROL_RX_RST);
|
|
|
|
cr &= ~AML_UART_CONTROL_CLR_ERR;
|
|
|
|
/* Enable the receive interrupt. */
|
|
|
|
cr |= AML_UART_CONTROL_RX_INT_EN;
|
|
|
|
uart_setreg(bas, AML_UART_CONTROL_REG, cr);
|
|
|
|
uart_barrier(bas);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
aml8726_uart_bus_detach(struct uart_softc *sc)
|
|
|
|
{
|
|
|
|
struct uart_bas *bas;
|
|
|
|
uint32_t cr;
|
|
|
|
uint32_t mr;
|
|
|
|
|
|
|
|
bas = &sc->sc_bas;
|
|
|
|
|
|
|
|
/* Disable all interrupt sources. */
|
|
|
|
cr = uart_getreg(bas, AML_UART_CONTROL_REG);
|
|
|
|
cr &= ~(AML_UART_CONTROL_TX_INT_EN | AML_UART_CONTROL_RX_INT_EN);
|
|
|
|
uart_setreg(bas, AML_UART_CONTROL_REG, cr);
|
|
|
|
uart_barrier(bas);
|
|
|
|
|
|
|
|
/* Clear RX FIFO level for generating interrupts. */
|
|
|
|
mr = uart_getreg(bas, AML_UART_MISC_REG);
|
|
|
|
mr &= ~AML_UART_MISC_RECV_IRQ_CNT_MASK;
|
|
|
|
uart_setreg(bas, AML_UART_MISC_REG, mr);
|
|
|
|
uart_barrier(bas);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
aml8726_uart_bus_flush(struct uart_softc *sc, int what)
|
|
|
|
{
|
|
|
|
struct uart_bas *bas;
|
|
|
|
uint32_t cr;
|
|
|
|
|
|
|
|
bas = &sc->sc_bas;
|
|
|
|
uart_lock(sc->sc_hwmtx);
|
|
|
|
|
|
|
|
cr = uart_getreg(bas, AML_UART_CONTROL_REG);
|
|
|
|
if (what & UART_FLUSH_TRANSMITTER)
|
|
|
|
cr |= AML_UART_CONTROL_TX_RST;
|
|
|
|
if (what & UART_FLUSH_RECEIVER)
|
|
|
|
cr |= AML_UART_CONTROL_RX_RST;
|
|
|
|
uart_setreg(bas, AML_UART_CONTROL_REG, cr);
|
|
|
|
uart_barrier(bas);
|
|
|
|
|
|
|
|
/* Ensure the reset bits are clear. */
|
|
|
|
cr &= ~(AML_UART_CONTROL_TX_RST | AML_UART_CONTROL_RX_RST);
|
|
|
|
uart_setreg(bas, AML_UART_CONTROL_REG, cr);
|
|
|
|
uart_barrier(bas);
|
|
|
|
|
|
|
|
uart_unlock(sc->sc_hwmtx);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
aml8726_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
|
|
|
|
{
|
|
|
|
struct uart_bas *bas;
|
|
|
|
int baudrate, divisor, error;
|
2015-05-06 01:07:59 +00:00
|
|
|
uint32_t cr, mr, nbr;
|
2015-03-31 11:50:46 +00:00
|
|
|
|
|
|
|
bas = &sc->sc_bas;
|
|
|
|
uart_lock(sc->sc_hwmtx);
|
|
|
|
|
|
|
|
error = 0;
|
|
|
|
switch (request) {
|
|
|
|
case UART_IOCTL_BAUD:
|
|
|
|
cr = uart_getreg(bas, AML_UART_CONTROL_REG);
|
|
|
|
cr &= AML_UART_CONTROL_BAUD_MASK;
|
|
|
|
|
|
|
|
mr = uart_getreg(bas, AML_UART_MISC_REG);
|
|
|
|
mr &= AML_UART_MISC_BAUD_EXT_MASK;
|
|
|
|
|
|
|
|
divisor = ((mr >> AML_UART_MISC_BAUD_EXT_SHIFT) <<
|
|
|
|
AML_UART_CONTROL_BAUD_WIDTH) | cr;
|
|
|
|
|
2015-05-06 01:07:59 +00:00
|
|
|
switch (aml8726_soc_hw_rev) {
|
|
|
|
case AML_SOC_HW_REV_M6:
|
|
|
|
case AML_SOC_HW_REV_M8:
|
|
|
|
case AML_SOC_HW_REV_M8B:
|
|
|
|
nbr = uart_getreg(bas, AML_UART_NEW_BAUD_REG);
|
|
|
|
if ((nbr & AML_UART_NEW_BAUD_RATE_EN) != 0) {
|
|
|
|
divisor = (nbr & AML_UART_NEW_BAUD_RATE_MASK) >>
|
|
|
|
AML_UART_NEW_BAUD_RATE_SHIFT;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2015-03-31 11:50:46 +00:00
|
|
|
baudrate = bas->rclk / 4 / (divisor + 1);
|
|
|
|
if (baudrate > 0)
|
|
|
|
*(int*)data = baudrate;
|
|
|
|
else
|
|
|
|
error = ENXIO;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case UART_IOCTL_IFLOW:
|
|
|
|
case UART_IOCTL_OFLOW:
|
|
|
|
cr = uart_getreg(bas, AML_UART_CONTROL_REG);
|
|
|
|
if (data)
|
|
|
|
cr &= ~AML_UART_CONTROL_TWO_WIRE_EN;
|
|
|
|
else
|
|
|
|
cr |= AML_UART_CONTROL_TWO_WIRE_EN;
|
|
|
|
uart_setreg(bas, AML_UART_CONTROL_REG, cr);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
error = EINVAL;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
uart_unlock(sc->sc_hwmtx);
|
|
|
|
|
|
|
|
return (error);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
aml8726_uart_bus_ipend(struct uart_softc *sc)
|
|
|
|
{
|
|
|
|
struct uart_bas *bas;
|
|
|
|
int ipend;
|
|
|
|
uint32_t sr;
|
|
|
|
uint32_t cr;
|
|
|
|
|
|
|
|
bas = &sc->sc_bas;
|
|
|
|
uart_lock(sc->sc_hwmtx);
|
|
|
|
|
|
|
|
ipend = 0;
|
|
|
|
sr = uart_getreg(bas, AML_UART_STATUS_REG);
|
|
|
|
cr = uart_getreg(bas, AML_UART_CONTROL_REG);
|
|
|
|
|
|
|
|
if ((sr & AML_UART_STATUS_RX_FIFO_OVERFLOW) != 0)
|
|
|
|
ipend |= SER_INT_OVERRUN;
|
|
|
|
|
|
|
|
if ((sr & AML_UART_STATUS_TX_FIFO_EMPTY) != 0 &&
|
|
|
|
(cr & AML_UART_CONTROL_TX_INT_EN) != 0) {
|
|
|
|
ipend |= SER_INT_TXIDLE;
|
|
|
|
|
|
|
|
cr &= ~AML_UART_CONTROL_TX_INT_EN;
|
|
|
|
uart_setreg(bas, AML_UART_CONTROL_REG, cr);
|
|
|
|
uart_barrier(bas);
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((sr & AML_UART_STATUS_RX_FIFO_EMPTY) == 0)
|
|
|
|
ipend |= SER_INT_RXREADY;
|
|
|
|
|
|
|
|
uart_unlock(sc->sc_hwmtx);
|
|
|
|
|
|
|
|
return (ipend);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
aml8726_uart_bus_param(struct uart_softc *sc, int baudrate, int databits,
|
|
|
|
int stopbits, int parity)
|
|
|
|
{
|
|
|
|
struct uart_bas *bas;
|
|
|
|
int error;
|
|
|
|
|
|
|
|
bas = &sc->sc_bas;
|
|
|
|
uart_lock(sc->sc_hwmtx);
|
|
|
|
|
|
|
|
error = aml8726_uart_param(bas, baudrate, databits, stopbits, parity);
|
|
|
|
|
|
|
|
uart_unlock(sc->sc_hwmtx);
|
|
|
|
|
|
|
|
return (error);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
aml8726_uart_bus_receive(struct uart_softc *sc)
|
|
|
|
{
|
|
|
|
struct uart_bas *bas;
|
|
|
|
int xc;
|
|
|
|
uint32_t sr;
|
|
|
|
|
|
|
|
bas = &sc->sc_bas;
|
|
|
|
uart_lock(sc->sc_hwmtx);
|
|
|
|
|
|
|
|
sr = uart_getreg(bas, AML_UART_STATUS_REG);
|
|
|
|
while ((sr & AML_UART_STATUS_RX_FIFO_EMPTY) == 0) {
|
|
|
|
if (uart_rx_full(sc)) {
|
|
|
|
sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
xc = uart_getreg(bas, AML_UART_RFIFO_REG) & 0xff;
|
|
|
|
if (sr & AML_UART_STATUS_FRAME_ERR)
|
|
|
|
xc |= UART_STAT_FRAMERR;
|
|
|
|
if (sr & AML_UART_STATUS_PARITY_ERR)
|
|
|
|
xc |= UART_STAT_PARERR;
|
|
|
|
uart_rx_put(sc, xc);
|
|
|
|
sr = uart_getreg(bas, AML_UART_STATUS_REG);
|
|
|
|
}
|
|
|
|
/* Discard everything left in the RX FIFO. */
|
|
|
|
while ((sr & AML_UART_STATUS_RX_FIFO_EMPTY) == 0) {
|
|
|
|
(void)uart_getreg(bas, AML_UART_RFIFO_REG);
|
|
|
|
sr = uart_getreg(bas, AML_UART_STATUS_REG);
|
|
|
|
}
|
|
|
|
/* Reset error bits */
|
|
|
|
if ((sr & (AML_UART_STATUS_FRAME_ERR | AML_UART_STATUS_PARITY_ERR)) != 0) {
|
|
|
|
uart_setreg(bas, AML_UART_CONTROL_REG,
|
|
|
|
(uart_getreg(bas, AML_UART_CONTROL_REG) |
|
|
|
|
AML_UART_CONTROL_CLR_ERR));
|
|
|
|
uart_barrier(bas);
|
|
|
|
uart_setreg(bas, AML_UART_CONTROL_REG,
|
|
|
|
(uart_getreg(bas, AML_UART_CONTROL_REG) &
|
|
|
|
~AML_UART_CONTROL_CLR_ERR));
|
|
|
|
uart_barrier(bas);
|
|
|
|
}
|
|
|
|
|
|
|
|
uart_unlock(sc->sc_hwmtx);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
aml8726_uart_bus_transmit(struct uart_softc *sc)
|
|
|
|
{
|
|
|
|
struct uart_bas *bas;
|
|
|
|
int i;
|
|
|
|
uint32_t cr;
|
|
|
|
|
|
|
|
bas = &sc->sc_bas;
|
|
|
|
uart_lock(sc->sc_hwmtx);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Wait for sufficient space since aml8726_uart_putc
|
|
|
|
* may have been called after SER_INT_TXIDLE occurred.
|
|
|
|
*/
|
|
|
|
while ((uart_getreg(bas, AML_UART_STATUS_REG) &
|
|
|
|
AML_UART_STATUS_TX_FIFO_EMPTY) == 0)
|
|
|
|
cpu_spinwait();
|
|
|
|
|
|
|
|
for (i = 0; i < sc->sc_txdatasz; i++) {
|
|
|
|
uart_setreg(bas, AML_UART_WFIFO_REG, sc->sc_txbuf[i]);
|
|
|
|
uart_barrier(bas);
|
|
|
|
}
|
|
|
|
|
|
|
|
sc->sc_txbusy = 1;
|
|
|
|
|
|
|
|
cr = uart_getreg(bas, AML_UART_CONTROL_REG);
|
|
|
|
cr |= AML_UART_CONTROL_TX_INT_EN;
|
|
|
|
uart_setreg(bas, AML_UART_CONTROL_REG, cr);
|
|
|
|
uart_barrier(bas);
|
|
|
|
|
|
|
|
uart_unlock(sc->sc_hwmtx);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
aml8726_uart_bus_grab(struct uart_softc *sc)
|
|
|
|
{
|
|
|
|
struct uart_bas *bas;
|
|
|
|
uint32_t cr;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Disable the receive interrupt to avoid a race between
|
|
|
|
* aml8726_uart_getc and aml8726_uart_bus_receive which
|
|
|
|
* can trigger:
|
|
|
|
*
|
|
|
|
* panic: bad stray interrupt
|
|
|
|
*
|
|
|
|
* due to the RX FIFO receiving a character causing an
|
|
|
|
* interrupt which gets serviced after aml8726_uart_getc
|
|
|
|
* has been called (meaning the RX FIFO is now empty).
|
|
|
|
*/
|
|
|
|
|
|
|
|
bas = &sc->sc_bas;
|
|
|
|
uart_lock(sc->sc_hwmtx);
|
|
|
|
|
|
|
|
cr = uart_getreg(bas, AML_UART_CONTROL_REG);
|
|
|
|
cr &= ~AML_UART_CONTROL_RX_INT_EN;
|
|
|
|
uart_setreg(bas, AML_UART_CONTROL_REG, cr);
|
|
|
|
uart_barrier(bas);
|
|
|
|
|
|
|
|
uart_unlock(sc->sc_hwmtx);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
aml8726_uart_bus_ungrab(struct uart_softc *sc)
|
|
|
|
{
|
|
|
|
struct uart_bas *bas;
|
|
|
|
uint32_t cr;
|
|
|
|
uint32_t mr;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The RX FIFO level being set indicates that the device
|
|
|
|
* is currently attached meaning the receive interrupt
|
|
|
|
* should be enabled.
|
|
|
|
*/
|
|
|
|
|
|
|
|
bas = &sc->sc_bas;
|
|
|
|
uart_lock(sc->sc_hwmtx);
|
|
|
|
|
|
|
|
mr = uart_getreg(bas, AML_UART_MISC_REG);
|
|
|
|
mr &= AML_UART_MISC_RECV_IRQ_CNT_MASK;
|
|
|
|
|
|
|
|
if (mr != 0) {
|
|
|
|
cr = uart_getreg(bas, AML_UART_CONTROL_REG);
|
|
|
|
cr |= AML_UART_CONTROL_RX_INT_EN;
|
|
|
|
uart_setreg(bas, AML_UART_CONTROL_REG, cr);
|
|
|
|
uart_barrier(bas);
|
|
|
|
}
|
|
|
|
|
|
|
|
uart_unlock(sc->sc_hwmtx);
|
|
|
|
}
|
|
|
|
|
|
|
|
static kobj_method_t aml8726_uart_methods[] = {
|
|
|
|
KOBJMETHOD(uart_probe, aml8726_uart_bus_probe),
|
|
|
|
KOBJMETHOD(uart_attach, aml8726_uart_bus_attach),
|
|
|
|
KOBJMETHOD(uart_detach, aml8726_uart_bus_detach),
|
|
|
|
KOBJMETHOD(uart_flush, aml8726_uart_bus_flush),
|
|
|
|
KOBJMETHOD(uart_getsig, aml8726_uart_bus_getsig),
|
|
|
|
KOBJMETHOD(uart_setsig, aml8726_uart_bus_setsig),
|
|
|
|
KOBJMETHOD(uart_ioctl, aml8726_uart_bus_ioctl),
|
|
|
|
KOBJMETHOD(uart_ipend, aml8726_uart_bus_ipend),
|
|
|
|
KOBJMETHOD(uart_param, aml8726_uart_bus_param),
|
|
|
|
KOBJMETHOD(uart_receive, aml8726_uart_bus_receive),
|
|
|
|
KOBJMETHOD(uart_transmit, aml8726_uart_bus_transmit),
|
|
|
|
KOBJMETHOD(uart_grab, aml8726_uart_bus_grab),
|
|
|
|
KOBJMETHOD(uart_ungrab, aml8726_uart_bus_ungrab),
|
|
|
|
{ 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
struct uart_class uart_aml8726_class = {
|
|
|
|
"uart",
|
|
|
|
aml8726_uart_methods,
|
|
|
|
sizeof(struct uart_softc),
|
|
|
|
.uc_ops = &aml8726_uart_ops,
|
|
|
|
.uc_range = 24,
|
2015-04-11 17:16:23 +00:00
|
|
|
.uc_rclk = 0,
|
|
|
|
.uc_rshift = 0
|
2015-03-31 11:50:46 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct ofw_compat_data compat_data[] = {
|
2015-04-11 08:34:41 +00:00
|
|
|
{ "amlogic,meson-uart", (uintptr_t)&uart_aml8726_class },
|
2015-03-31 11:50:46 +00:00
|
|
|
{ NULL, (uintptr_t)NULL }
|
|
|
|
};
|
|
|
|
UART_FDT_CLASS_AND_DEVICE(compat_data);
|