81 lines
3.8 KiB
C
81 lines
3.8 KiB
C
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/*
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* Copyright (c) 1993, 1994, 1995
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* Rodney W. Grimes, Milwaukie, Oregon 97222. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer as
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* the first lines of this file unmodified.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Rodney W. Grimes.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY RODNEY W. GRIMES ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL RODNEY W. GRIMES BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/*
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* Definitions for EtherExpress 16
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*/
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#define IEE16_ATTN 0x06 /* channel attention control */
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#define IEE16_IRQ 0x07 /* IRQ configuration */
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#define IEE16_IRQ_ENABLE 0x08 /* enable board interrupts */
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#define IEE16_MEMDEC 0x0a /* memory decode */
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#define IEE16_MCTRL 0x0b /* memory control */
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#define IEE16_MCTRL_FMCS16 0x10 /* MEMCS16- for F000 */
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#define IEE16_MPCTRL 0x0c /* memory page control */
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#define IEE16_CONFIG 0x0d /* config register */
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#define IEE16_BART_LOOPBACK 0x02 /* loopback, 0=none, 1=loopback */
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#define IEE16_BART_IOCHRDY_LATE 0x10 /* iochrdy late control bit */
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#define IEE16_BART_IO_TEST_EN 0x20 /* enable iochrdy timing test */
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#define IEE16_BART_IO_RESULT 0x40 /* result of the iochrdy test */
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#define IEE16_BART_MCS16_TEST 0x80 /* enable memcs16 select test */
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#define IEE16_ECTRL 0x0e /* eeprom control */
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#define IEE16_ECTRL_EESK 0x01 /* EEPROM clock bit */
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#define IEE16_ECTRL_EECS 0x02 /* EEPROM chip select */
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#define IEE16_ECTRL_EEDI 0x04 /* EEPROM data in bit */
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#define IEE16_ECTRL_EEDO 0x08 /* EEPROM data out bit */
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#define IEE16_RESET_ASIC 0x40 /* reset ASIC (bart) pin */
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#define IEE16_RESET_586 0x80 /* reset 82586 pin */
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#define IEE16_ECTRL_MASK 0xb2 /* and'ed with ECTRL to enable read */
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#define IEE16_MECTRL 0x0f /* memory control, 0xe000 seg 'W' */
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#define IEE16_ID_PORT 0x0f /* auto-id port 'R' */
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#define IEE16_ID 0xbaba /* known id of EE16 */
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#define IEE16_EEPROM_READ 0x06 /* EEPROM read opcode */
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#define IEE16_EEPROM_OPSIZE1 0x03 /* size of EEPROM opcodes */
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#define IEE16_EEPROM_ADDR_SIZE 0x06 /* size of EEPROM address */
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/* Locations in the EEPROM */
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#define IEE16_EEPROM_CONFIG1 0x00 /* Configuration register 1 */
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#define IEE16_EEPROM_IRQ 0xE000 /* Encoded IRQ */
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#define IEE16_EEPROM_IRQ_SHIFT 13 /* To shift IRQ to lower bits */
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#define IEE16_EEPROM_LOCK_ADDR 0x01 /* contains the lock bit */
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#define IEE16_EEPROM_LOCKED 0x01 /* means that it is locked */
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#define IEE16_EEPROM_ENET_LOW 0x02 /* Ethernet address, low word */
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#define IEE16_EEPROM_ENET_MID 0x03 /* Ethernet address, middle word */
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#define IEE16_EEPROM_ENET_HIGH 0x04 /* Ethernet address, high word */
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