134 lines
4.1 KiB
C
134 lines
4.1 KiB
C
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/*-
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* Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
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* reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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* NETLOGIC_BSD */
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#ifndef __NLM_XLP_H__
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#define __NLM_XLP_H__
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#include <mips/nlm/hal/pic.h>
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#define XLP_PIC_IRT_UART0_IRQ 9
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#define XLP_PIC_IRT_UART1_IRQ 10
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#define XLP_PIC_IRT_PCIE0_IRQ 11
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#define XLP_PIC_IRT_PCIE1_IRQ 12
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#define XLP_PIC_IRT_PCIE2_IRQ 13
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#define XLP_PIC_IRT_PCIE3_IRQ 14
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#define XLP_PIC_IRT_EHCI0_IRQ 39
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#define XLP_PIC_IRT_EHCI1_IRQ 42
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#define XLP_PIC_IRT_MMC_IRQ 43
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#ifndef LOCORE
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/*
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* FreeBSD can be started with few threads and cores turned off,
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* so have a hardware thread id to FreeBSD cpuid mapping.
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*/
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extern int xlp_ncores;
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extern int xlp_threads_per_core;
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extern uint32_t xlp_hw_thread_mask;
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extern int xlp_cpuid_to_hwtid[];
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extern int xlp_hwtid_to_cpuid[];
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#ifdef SMP
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extern void xlp_enable_threads(int code);
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#endif
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extern uint64_t xlp_pic_base; /* TODO just for node 0 now */
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static __inline__ int
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xlp_irt_to_irq(int irt)
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{
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switch (irt) {
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case XLP_PIC_IRT_MMC_INDEX :
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return XLP_PIC_IRT_MMC_IRQ;
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case XLP_PIC_IRT_EHCI0_INDEX :
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return XLP_PIC_IRT_EHCI0_IRQ;
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case XLP_PIC_IRT_EHCI1_INDEX :
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return XLP_PIC_IRT_EHCI1_IRQ;
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case XLP_PIC_IRT_UART0_INDEX :
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return XLP_PIC_IRT_UART0_IRQ;
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case XLP_PIC_IRT_UART1_INDEX :
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return XLP_PIC_IRT_UART1_IRQ;
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case XLP_PIC_IRT_PCIE_LINK0_INDEX :
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return XLP_PIC_IRT_PCIE0_IRQ;
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case XLP_PIC_IRT_PCIE_LINK1_INDEX :
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return XLP_PIC_IRT_PCIE1_IRQ;
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case XLP_PIC_IRT_PCIE_LINK2_INDEX :
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return XLP_PIC_IRT_PCIE2_IRQ;
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case XLP_PIC_IRT_PCIE_LINK3_INDEX :
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return XLP_PIC_IRT_PCIE3_IRQ;
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default: panic("Bad IRT %d\n", irt);
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}
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}
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static __inline__ int
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xlp_irq_to_irt(int irq)
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{
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switch (irq) {
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case XLP_PIC_IRT_MMC_IRQ :
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return XLP_PIC_IRT_MMC_INDEX;
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case XLP_PIC_IRT_EHCI0_IRQ :
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return XLP_PIC_IRT_EHCI0_INDEX;
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case XLP_PIC_IRT_EHCI1_IRQ :
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return XLP_PIC_IRT_EHCI1_INDEX;
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case XLP_PIC_IRT_UART0_IRQ :
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return XLP_PIC_IRT_UART0_INDEX;
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case XLP_PIC_IRT_UART1_IRQ :
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return XLP_PIC_IRT_UART1_INDEX;
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case XLP_PIC_IRT_PCIE0_IRQ :
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return XLP_PIC_IRT_PCIE_LINK0_INDEX;
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case XLP_PIC_IRT_PCIE1_IRQ :
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return XLP_PIC_IRT_PCIE_LINK1_INDEX;
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case XLP_PIC_IRT_PCIE2_IRQ :
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return XLP_PIC_IRT_PCIE_LINK2_INDEX;
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case XLP_PIC_IRT_PCIE3_IRQ :
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return XLP_PIC_IRT_PCIE_LINK3_INDEX;
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default: panic("Bad IRQ %d\n", irq);
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}
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}
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static __inline__ int
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xlp_irq_is_picintr(int irq)
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{
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switch (irq) {
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case XLP_PIC_IRT_MMC_IRQ : return 1;
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case XLP_PIC_IRT_EHCI0_IRQ : return 1;
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case XLP_PIC_IRT_EHCI1_IRQ : return 1;
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case XLP_PIC_IRT_UART0_IRQ : return 1;
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case XLP_PIC_IRT_UART1_IRQ : return 1;
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case XLP_PIC_IRT_PCIE0_IRQ : return 1;
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case XLP_PIC_IRT_PCIE1_IRQ : return 1;
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case XLP_PIC_IRT_PCIE2_IRQ : return 1;
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case XLP_PIC_IRT_PCIE3_IRQ : return 1;
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default: return 0;
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}
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}
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#endif /* LOCORE */
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#endif /* __NLM_XLP_H__ */
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