362 lines
11 KiB
C
362 lines
11 KiB
C
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/* $FreeBSD$ */
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/*-
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* Copyright (c) 2004, 2005
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* Damien Bergamini <damien.bergamini@free.fr>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#define IPW_NTBD 128
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#define IPW_TBD_SZ (IPW_NTBD * sizeof (struct ipw_bd))
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#define IPW_NDATA (IPW_NTBD / 2)
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#define IPW_NRBD 128
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#define IPW_RBD_SZ (IPW_NRBD * sizeof (struct ipw_bd))
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#define IPW_STATUS_SZ (IPW_NRBD * sizeof (struct ipw_status))
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#define IPW_CSR_INTR 0x0008
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#define IPW_CSR_INTR_MASK 0x000c
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#define IPW_CSR_INDIRECT_ADDR 0x0010
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#define IPW_CSR_INDIRECT_DATA 0x0014
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#define IPW_CSR_AUTOINC_ADDR 0x0018
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#define IPW_CSR_AUTOINC_DATA 0x001c
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#define IPW_CSR_RST 0x0020
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#define IPW_CSR_CTL 0x0024
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#define IPW_CSR_IO 0x0030
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#define IPW_CSR_TX_BASE 0x0200
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#define IPW_CSR_TX_SIZE 0x0204
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#define IPW_CSR_RX_BASE 0x0240
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#define IPW_CSR_STATUS_BASE 0x0244
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#define IPW_CSR_RX_SIZE 0x0248
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#define IPW_CSR_TX_READ 0x0280
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#define IPW_CSR_RX_READ 0x02a0
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#define IPW_CSR_TABLE1_BASE 0x0380
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#define IPW_CSR_TABLE2_BASE 0x0384
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#define IPW_CSR_TX_WRITE 0x0f80
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#define IPW_CSR_RX_WRITE 0x0fa0
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/* possible flags for register IPW_CSR_INTR */
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#define IPW_INTR_TX_TRANSFER 0x00000001
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#define IPW_INTR_RX_TRANSFER 0x00000002
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#define IPW_INTR_STATUS_CHANGE 0x00000010
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#define IPW_INTR_COMMAND_DONE 0x00010000
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#define IPW_INTR_FW_INIT_DONE 0x01000000
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#define IPW_INTR_FATAL_ERROR 0x40000000
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#define IPW_INTR_PARITY_ERROR 0x80000000
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#define IPW_INTR_MASK \
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(IPW_INTR_TX_TRANSFER | IPW_INTR_RX_TRANSFER | \
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IPW_INTR_STATUS_CHANGE | IPW_INTR_COMMAND_DONE | \
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IPW_INTR_FW_INIT_DONE | IPW_INTR_FATAL_ERROR | \
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IPW_INTR_PARITY_ERROR)
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/* possible flags for register IPW_CSR_RST */
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#define IPW_RST_PRINCETON_RESET 0x00000001
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#define IPW_RST_SW_RESET 0x00000080
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#define IPW_RST_MASTER_DISABLED 0x00000100
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#define IPW_RST_STOP_MASTER 0x00000200
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/* possible flags for register IPW_CSR_CTL */
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#define IPW_CTL_CLOCK_READY 0x00000001
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#define IPW_CTL_ALLOW_STANDBY 0x00000002
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#define IPW_CTL_INIT 0x00000004
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/* possible flags for register IPW_CSR_IO */
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#define IPW_IO_GPIO1_ENABLE 0x00000008
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#define IPW_IO_GPIO1_MASK 0x0000000c
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#define IPW_IO_GPIO3_MASK 0x000000c0
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#define IPW_IO_LED_OFF 0x00002000
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#define IPW_IO_RADIO_DISABLED 0x00010000
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#define IPW_STATE_ASSOCIATED 0x0004
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#define IPW_STATE_ASSOCIATION_LOST 0x0008
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#define IPW_STATE_SCAN_COMPLETE 0x0020
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#define IPW_STATE_RADIO_DISABLED 0x0100
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#define IPW_STATE_DISABLED 0x0200
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#define IPW_STATE_SCANNING 0x0800
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/* table1 offsets */
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#define IPW_INFO_LOCK 480
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#define IPW_INFO_APS_CNT 604
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#define IPW_INFO_APS_BASE 608
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#define IPW_INFO_CARD_DISABLED 628
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#define IPW_INFO_CURRENT_CHANNEL 756
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#define IPW_INFO_CURRENT_TX_RATE 768
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/* table2 offsets */
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#define IPW_INFO_CURRENT_SSID 48
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#define IPW_INFO_CURRENT_BSSID 112
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/* supported rates */
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#define IPW_RATE_DS1 1
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#define IPW_RATE_DS2 2
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#define IPW_RATE_DS5 4
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#define IPW_RATE_DS11 8
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/* firmware binary image header */
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struct ipw_firmware_hdr {
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u_int32_t version;
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u_int32_t main_size; /* firmware size */
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u_int32_t ucode_size; /* microcode size */
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} __packed;
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/* buffer descriptor */
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struct ipw_bd {
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u_int32_t physaddr;
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u_int32_t len;
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u_int8_t flags;
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#define IPW_BD_FLAG_TX_FRAME_802_3 0x00
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#define IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT 0x01
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#define IPW_BD_FLAG_TX_FRAME_COMMAND 0x02
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#define IPW_BD_FLAG_TX_FRAME_802_11 0x04
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#define IPW_BD_FLAG_TX_LAST_FRAGMENT 0x08
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u_int8_t nfrag; /* number of fragments */
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u_int8_t reserved[6];
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} __packed;
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/* status */
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struct ipw_status {
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u_int32_t len;
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u_int16_t code;
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#define IPW_STATUS_CODE_COMMAND 0
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#define IPW_STATUS_CODE_NEWSTATE 1
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#define IPW_STATUS_CODE_DATA_802_11 2
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#define IPW_STATUS_CODE_DATA_802_3 3
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#define IPW_STATUS_CODE_NOTIFICATION 4
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u_int8_t flags;
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#define IPW_STATUS_FLAG_DECRYPTED 0x01
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#define IPW_STATUS_FLAG_WEP_ENCRYPTED 0x02
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u_int8_t rssi; /* received signal strength indicator */
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} __packed;
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/* data header */
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struct ipw_hdr {
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u_int32_t type;
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#define IPW_HDR_TYPE_SEND 33
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u_int32_t subtype;
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u_int8_t encrypted;
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u_int8_t encrypt;
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u_int8_t keyidx;
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u_int8_t keysz;
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u_int8_t key[IEEE80211_KEYBUF_SIZE];
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u_int8_t reserved[10];
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u_int8_t src_addr[IEEE80211_ADDR_LEN];
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u_int8_t dst_addr[IEEE80211_ADDR_LEN];
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u_int16_t fragmentsz;
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} __packed;
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/* command */
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struct ipw_cmd {
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u_int32_t type;
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#define IPW_CMD_ENABLE 2
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#define IPW_CMD_SET_CONFIGURATION 6
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#define IPW_CMD_SET_ESSID 8
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#define IPW_CMD_SET_MANDATORY_BSSID 9
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#define IPW_CMD_SET_MAC_ADDRESS 11
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#define IPW_CMD_SET_MODE 12
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#define IPW_CMD_SET_CHANNEL 14
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#define IPW_CMD_SET_RTS_THRESHOLD 15
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#define IPW_CMD_SET_FRAG_THRESHOLD 16
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#define IPW_CMD_SET_POWER_MODE 17
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#define IPW_CMD_SET_TX_RATES 18
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#define IPW_CMD_SET_BASIC_TX_RATES 19
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#define IPW_CMD_SET_WEP_KEY 20
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#define IPW_CMD_SET_WEP_KEY_INDEX 25
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#define IPW_CMD_SET_WEP_FLAGS 26
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#define IPW_CMD_ADD_MULTICAST 27
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#define IPW_CMD_SET_BEACON_INTERVAL 29
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#define IPW_CMD_SET_TX_POWER_INDEX 36
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#define IPW_CMD_BROADCAST_SCAN 43
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#define IPW_CMD_DISABLE 44
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#define IPW_CMD_SET_DESIRED_BSSID 45
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#define IPW_CMD_SET_SCAN_OPTIONS 46
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#define IPW_CMD_PREPARE_POWER_DOWN 58
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#define IPW_CMD_DISABLE_PHY 61
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#define IPW_CMD_SET_SECURITY_INFORMATION 67
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#define IPW_CMD_SET_WPA_IE 69
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u_int32_t subtype;
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u_int32_t seq;
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u_int32_t len;
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u_int8_t data[400];
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u_int32_t status;
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u_int8_t reserved[68];
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} __packed;
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/* possible values for command IPW_CMD_SET_POWER_MODE */
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#define IPW_POWER_MODE_CAM 0
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#define IPW_POWER_AUTOMATIC 6
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/* possible values for command IPW_CMD_SET_MODE */
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#define IPW_MODE_BSS 0
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#define IPW_MODE_IBSS 1
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#define IPW_MODE_MONITOR 2
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/* possible flags for command IPW_CMD_SET_WEP_FLAGS */
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#define IPW_WEPON 0x8
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/* structure for command IPW_CMD_SET_WEP_KEY */
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struct ipw_wep_key {
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u_int8_t idx;
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u_int8_t len;
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u_int8_t key[13];
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} __packed;
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/* structure for command IPW_CMD_SET_SECURITY_INFORMATION */
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struct ipw_security {
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u_int32_t ciphers;
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#define IPW_CIPHER_NONE 0x00000001
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#define IPW_CIPHER_WEP40 0x00000002
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#define IPW_CIPHER_TKIP 0x00000004
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#define IPW_CIPHER_CCMP 0x00000010
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#define IPW_CIPHER_WEP104 0x00000020
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#define IPW_CIPHER_CKIP 0x00000040
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u_int16_t reserved1;
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u_int8_t authmode;
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#define IPW_AUTH_OPEN 0
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#define IPW_AUTH_SHARED 1
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u_int16_t reserved2;
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} __packed;
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/* structure for command IPW_CMD_SET_SCAN_OPTIONS */
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struct ipw_scan_options {
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u_int32_t flags;
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#define IPW_SCAN_DO_NOT_ASSOCIATE 0x00000001
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#define IPW_SCAN_PASSIVE 0x00000008
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u_int32_t channels;
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} __packed;
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/* structure for command IPW_CMD_SET_CONFIGURATION */
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struct ipw_configuration {
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u_int32_t flags;
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#define IPW_CFG_PROMISCUOUS 0x00000004
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#define IPW_CFG_PREAMBLE_AUTO 0x00000010
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#define IPW_CFG_IBSS_AUTO_START 0x00000020
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#define IPW_CFG_802_1x_ENABLE 0x00004000
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#define IPW_CFG_BSS_MASK 0x00008000
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#define IPW_CFG_IBSS_MASK 0x00010000
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u_int32_t bss_chan;
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u_int32_t ibss_chan;
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} __packed;
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/* structure for command IPW_CMD_SET_WPA_IE */
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struct ipw_wpa_ie {
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u_int16_t mask;
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u_int16_t capinfo;
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u_int16_t lintval;
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u_int8_t bssid[IEEE80211_ADDR_LEN];
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u_int32_t len;
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struct ieee80211_ie_wpa ie;
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} __packed;
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/* element in AP table */
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struct ipw_node {
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u_int32_t reserved1[2];
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u_int8_t bssid[IEEE80211_ADDR_LEN];
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u_int8_t chan;
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u_int8_t rates;
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u_int16_t reserved2;
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u_int16_t capinfo;
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u_int16_t reserved3;
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u_int16_t intval;
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u_int8_t reserved4[28];
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u_int8_t essid[IEEE80211_NWID_LEN];
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u_int16_t reserved5;
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u_int8_t esslen;
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u_int8_t reserved6[7];
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u_int8_t rssi;
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} __packed;
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/* EEPROM = Electrically Erasable Programmable Read-Only Memory */
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#define IPW_MEM_EEPROM_CTL 0x00300040
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#define IPW_EEPROM_RADIO 0x11
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#define IPW_EEPROM_MAC 0x21
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#define IPW_EEPROM_CHANNEL_LIST 0x37
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#define IPW_EEPROM_DELAY 1 /* minimum hold time (microsecond) */
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#define IPW_EEPROM_C (1 << 0) /* Serial Clock */
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#define IPW_EEPROM_S (1 << 1) /* Chip Select */
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#define IPW_EEPROM_D (1 << 2) /* Serial data input */
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#define IPW_EEPROM_Q (1 << 4) /* Serial data output */
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#define IPW_EEPROM_SHIFT_D 2
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#define IPW_EEPROM_SHIFT_Q 4
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/*
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* control and status registers access macros
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*/
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#define CSR_READ_1(sc, reg) \
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bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
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#define CSR_READ_2(sc, reg) \
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bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
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#define CSR_READ_4(sc, reg) \
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bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
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#define CSR_WRITE_1(sc, reg, val) \
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bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
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#define CSR_WRITE_2(sc, reg, val) \
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bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
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#define CSR_WRITE_4(sc, reg, val) \
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bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
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#define CSR_WRITE_MULTI_1(sc, reg, buf, len) \
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bus_space_write_multi_1((sc)->sc_st, (sc)->sc_sh, (reg), \
|
||
|
|
(buf), (len))
|
||
|
|
|
||
|
|
/*
|
||
|
|
* indirect memory space access macros
|
||
|
|
*/
|
||
|
|
#define MEM_WRITE_1(sc, addr, val) do { \
|
||
|
|
CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
|
||
|
|
CSR_WRITE_1((sc), IPW_CSR_INDIRECT_DATA, (val)); \
|
||
|
|
} while (/* CONSTCOND */0)
|
||
|
|
|
||
|
|
#define MEM_WRITE_2(sc, addr, val) do { \
|
||
|
|
CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
|
||
|
|
CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \
|
||
|
|
} while (/* CONSTCOND */0)
|
||
|
|
|
||
|
|
#define MEM_WRITE_4(sc, addr, val) do { \
|
||
|
|
CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
|
||
|
|
CSR_WRITE_4((sc), IPW_CSR_INDIRECT_DATA, (val)); \
|
||
|
|
} while (/* CONSTCOND */0)
|
||
|
|
|
||
|
|
#define MEM_WRITE_MULTI_1(sc, addr, buf, len) do { \
|
||
|
|
CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
|
||
|
|
CSR_WRITE_MULTI_1((sc), IPW_CSR_INDIRECT_DATA, (buf), (len)); \
|
||
|
|
} while (/* CONSTCOND */0)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* EEPROM access macro
|
||
|
|
*/
|
||
|
|
#define IPW_EEPROM_CTL(sc, val) do { \
|
||
|
|
MEM_WRITE_4((sc), IPW_MEM_EEPROM_CTL, (val)); \
|
||
|
|
DELAY(IPW_EEPROM_DELAY); \
|
||
|
|
} while (0)
|