94 lines
4.7 KiB
C
94 lines
4.7 KiB
C
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/*
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* Copyright (c) KATO Takenori, 1996. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer as
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* the first lines of this file unmodified.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __PC98_PC98_AIC_98_H__
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#define __PC98_PC98_AIC_98_H__
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/* generic card */
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static int aicport_generic[32] = {
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0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
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0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
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0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
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0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f
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};
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/* PC-9801-100 */
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static int aicport_100[32] = {
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0x00, 0x02, 0x04, 0x06, 0x08, 0x0a, 0x0c, 0x0e,
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0x10, 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e,
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0x20, 0x22, 0x24, 0x26, 0x28, 0x2a, 0x2c, 0x2e,
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0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e
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};
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#define AIC98_GENERIC 0x00
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#define AIC98_100 0x01
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#define AIC_TYPE98(x) ((x >> 16) & 0xff)
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#define SCSISEQ (iobase + aic->aicport[0x00]) /* SCSI sequence control */
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#define SXFRCTL0 (iobase + aic->aicport[0x01]) /* SCSI transfer control 0 */
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#define SXFRCTL1 (iobase + aic->aicport[0x02]) /* SCSI transfer control 1 */
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#define SCSISIGI (iobase + aic->aicport[0x03]) /* SCSI signal in */
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#define SCSISIGO (iobase + aic->aicport[0x03]) /* SCSI signal out */
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#define SCSIRATE (iobase + aic->aicport[0x04]) /* SCSI rate control */
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#define SCSIID (iobase + aic->aicport[0x05]) /* SCSI ID */
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#define SELID (iobase + aic->aicport[0x05]) /* Selection/Reselection ID */
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#define SCSIDAT (iobase + aic->aicport[0x06]) /* SCSI Latched Data */
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#define SCSIBUS (iobase + aic->aicport[0x07]) /* SCSI Data Bus*/
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#define STCNT0 (iobase + aic->aicport[0x08]) /* SCSI transfer count */
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#define STCNT1 (iobase + aic->aicport[0x09)
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#define STCNT2 (iobase + aic->aicport[0x0a)
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#define CLRSINT0 (iobase + aic->aicport[0x0b]) /* Clear SCSI interrupts 0 */
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#define SSTAT0 (iobase + aic->aicport[0x0b]) /* SCSI interrupt status 0 */
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#define CLRSINT1 (iobase + aic->aicport[0x0c]) /* Clear SCSI interrupts 1 */
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#define SSTAT1 (iobase + aic->aicport[0x0c]) /* SCSI status 1 */
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#define SSTAT2 (iobase + aic->aicport[0x0d]) /* SCSI status 2 */
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#define SCSITEST (iobase + aic->aicport[0x0e]) /* SCSI test control */
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#define SSTAT3 (iobase + aic->aicport[0x0e]) /* SCSI status 3 */
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#define CLRSERR (iobase + aic->aicport[0x0f]) /* Clear SCSI errors */
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#define SSTAT4 (iobase + aic->aicport[0x0f]) /* SCSI status 4 */
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#define SIMODE0 (iobase + aic->aicport[0x10]) /* SCSI interrupt mode 0 */
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#define SIMODE1 (iobase + aic->aicport[0x11]) /* SCSI interrupt mode 1 */
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#define DMACNTRL0 (iobase + aic->aicport[0x12]) /* DMA control 0 */
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#define DMACNTRL1 (iobase + aic->aicport[0x13]) /* DMA control 1 */
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#define DMASTAT (iobase + aic->aicport[0x14]) /* DMA status */
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#define FIFOSTAT (iobase + aic->aicport[0x15]) /* FIFO status */
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#define DMADATA (iobase + aic->aicport[0x16]) /* DMA data */
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#define DMADATAL (iobase + aic->aicport[0x16]) /* DMA data low byte */
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#define DMADATAH (iobase + aic->aicport[0x17]) /* DMA data high byte */
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#define BRSTCNTRL (iobase + aic->aicport[0x18]) /* Burst Control */
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#define DMADATALONG (iobase + aic->aicport[0x18)
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#define PORTA (iobase + aic->aicport[0x1a]) /* Port A */
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#define PORTB (iobase + aic->aicport[0x1b]) /* Port B */
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#define REV (iobase + aic->aicport[0x1c]) /* Revision (001 for 6360) */
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#define STACK (iobase + aic->aicport[0x1d]) /* Stack */
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#define TEST (iobase + aic->aicport[0x1e]) /* Test register */
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#define ID (iobase + aic->aicport[0x1f]) /* ID register */
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#endif
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