421 lines
14 KiB
C
421 lines
14 KiB
C
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/*
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* Copyright (c) 2010, LSI Corp.
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* All rights reserved.
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* Author : Manjunath Ranganathaiah
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* Support: freebsdraid@lsi.com
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name of the <ORGANIZATION> nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/* bit's defination */
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#define TWS_BIT0 0x00000001
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#define TWS_BIT1 0x00000002
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#define TWS_BIT2 0x00000004
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#define TWS_BIT3 0x00000008
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#define TWS_BIT4 0x00000010
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#define TWS_BIT5 0x00000020
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#define TWS_BIT6 0x00000040
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#define TWS_BIT7 0x00000080
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#define TWS_BIT8 0x00000100
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#define TWS_BIT9 0x00000200
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#define TWS_BIT10 0x00000400
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#define TWS_BIT11 0x00000800
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#define TWS_BIT12 0x00001000
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#define TWS_BIT13 0x00002000
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#define TWS_BIT14 0x00004000
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#define TWS_BIT15 0x00008000
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#define TWS_BIT16 0x00010000
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#define TWS_BIT17 0x00020000
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#define TWS_BIT18 0x00040000
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#define TWS_BIT19 0x00080000
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#define TWS_BIT20 0x00100000
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#define TWS_BIT21 0x00200000
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#define TWS_BIT22 0x00400000
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#define TWS_BIT23 0x00800000
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#define TWS_BIT24 0x01000000
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#define TWS_BIT25 0x02000000
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#define TWS_BIT26 0x04000000
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#define TWS_BIT27 0x08000000
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#define TWS_BIT28 0x10000000
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#define TWS_BIT29 0x20000000
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#define TWS_BIT30 0x40000000
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#define TWS_BIT31 0x80000000
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#define TWS_SENSE_DATA_LENGTH 18
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#define TWS_ERROR_SPECIFIC_DESC_LEN 98
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/* response codes */
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#define TWS_SENSE_SCSI_CURRENT_ERROR 0x70
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#define TWS_SENSE_SCSI_DEFERRED_ERROR 0x71
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#define TWS_SRC_CTRL_ERROR 3
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#define TWS_SRC_CTRL_EVENT 4
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#define TWS_SRC_FREEBSD_DRIVER 5
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#define TWS_SRC_FREEBSD_OS 8
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enum tws_sense_severity {
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error = 1,
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warning ,
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info,
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debug,
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};
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/*
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* Some errors of interest (in cmd_hdr->status_block.error) when a command
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* is completed by the firmware with an error.
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*/
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#define TWS_ERROR_LOGICAL_UNIT_NOT_SUPPORTED 0x010a
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#define TWS_ERROR_NOT_SUPPORTED 0x010D
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#define TWS_ERROR_UNIT_OFFLINE 0x0128
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#define TWS_ERROR_MORE_DATA 0x0231
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/* AEN codes of interest. */
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#define TWS_AEN_QUEUE_EMPTY 0x00
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#define TWS_AEN_SOFT_RESET 0x01
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#define TWS_AEN_SYNC_TIME_WITH_HOST 0x31
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/* AEN severity */
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#define TWS_SEVERITY_ERROR 0x1
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#define TWS_SEVERITY_WARNING 0x2
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#define TWS_SEVERITY_INFO 0x3
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#define TWS_SEVERITY_DEBUG 0x4
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#define TWS_64BIT_SG_ADDRESSES 0x00000001
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#define TWS_BIT_EXTEND 0x00000002
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#define TWS_BASE_FW_SRL 24
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#define TWS_BASE_FW_BRANCH 0
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#define TWS_BASE_FW_BUILD 1
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#define TWS_CURRENT_FW_SRL 41
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#define TWS_CURRENT_FW_BRANCH 8
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#define TWS_CURRENT_FW_BUILD 4
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#define TWS_CURRENT_ARCH_ID 0x000A
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#define TWS_FIFO_EMPTY 0xFFFFFFFFFFFFFFFFull
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#define TWS_FIFO_EMPTY32 0xFFFFFFFFull
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/* Register offsets from base address. */
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#define TWS_CONTROL_REGISTER_OFFSET 0x0
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#define TWS_STATUS_REGISTER_OFFSET 0x4
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#define TWS_COMMAND_QUEUE_OFFSET 0x8
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#define TWS_RESPONSE_QUEUE_OFFSET 0xC
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#define TWS_COMMAND_QUEUE_OFFSET_LOW 0x20
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#define TWS_COMMAND_QUEUE_OFFSET_HIGH 0x24
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#define TWS_LARGE_RESPONSE_QUEUE_OFFSET 0x30
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/* I2O offsets */
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#define TWS_I2O0_STATUS 0x0
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#define TWS_I2O0_HIBDB 0x20
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#define TWS_I2O0_HISTAT 0x30
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#define TWS_I2O0_HIMASK 0x34
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#define TWS_I2O0_HIBQP 0x40
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#define TWS_I2O0_HOBQP 0x44
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#define TWS_I2O0_CTL 0x74
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#define TWS_I2O0_IOBDB 0x9C
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#define TWS_I2O0_HOBDBC 0xA0
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#define TWS_I2O0_SCRPD3 0xBC
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#define TWS_I2O0_HIBQPL 0xC0 /* 64bit inb port low */
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#define TWS_I2O0_HIBQPH 0xC4 /* 64bit inb port high */
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#define TWS_I2O0_HOBQPL 0xC8 /* 64bit out port low */
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#define TWS_I2O0_HOBQPH 0xCC /* 64bit out port high */
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/* IOP related */
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#define TWS_I2O0_IOPOBQPL 0xD8 /* OBFL */
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#define TWS_I2O0_IOPOBQPH 0xDC /* OBFH */
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#define TWS_I2O0_SRC_ADDRH 0xF8 /* Msg ASA */
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#define TWS_MSG_ACC_MASK 0x20000000
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#define TWS_32BIT_MASK 0xFFFFFFFF
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/* revisit */
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#define TWS_FW_CMD_NOP 0x0
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#define TWS_FW_CMD_INIT_CONNECTION 0x01
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#define TWS_FW_CMD_EXECUTE_SCSI 0x10
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#define TWS_FW_CMD_ATA_PASSTHROUGH 0x11
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#define TWS_FW_CMD_GET_PARAM 0x12
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#define TWS_FW_CMD_SET_PARAM 0x13
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#define BUILD_SGL_OFF__OPCODE(sgl_off, opcode) \
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((sgl_off << 5) & 0xE0) | (opcode & 0x1F) /* 3:5 */
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#define BUILD_RES__OPCODE(res, opcode) \
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((res << 5) & 0xE0) | (opcode & 0x1F) /* 3:5 */
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#define GET_OPCODE(sgl_off__opcode) \
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(sgl_off__opcode & 0x1F) /* 3:5 */
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/* end revisit */
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/* Table #'s and id's of parameters of interest in firmware's param table. */
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#define TWS_PARAM_VERSION_TABLE 0x0402
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#define TWS_PARAM_VERSION_FW 3 /* firmware version [16] */
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#define TWS_PARAM_VERSION_BIOS 4 /* BIOSs version [16] */
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#define TWS_PARAM_CTLR_MODEL 8 /* Controller model [16] */
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#define TWS_PARAM_CONTROLLER_TABLE 0x0403
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#define TWS_PARAM_CONTROLLER_PORT_COUNT 3 /* number of ports [1] */
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#define TWS_PARAM_TIME_TABLE 0x40A
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#define TWS_PARAM_TIME_SCHED_TIME 0x3
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#define TWS_PARAM_PHYS_TABLE 0x0001
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#define TWS_PARAM_CONTROLLER_PHYS_COUNT 2 /* number of phys */
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#define TWS_9K_PARAM_DESCRIPTOR 0x8000
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/* ----------- request ------------- */
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#pragma pack(1)
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struct tws_cmd_init_connect {
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u_int8_t res1__opcode; /* 3:5 */
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u_int8_t size;
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u_int8_t request_id;
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u_int8_t res2;
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u_int8_t status;
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u_int8_t flags;
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u_int16_t message_credits;
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u_int32_t features;
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u_int16_t fw_srl;
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u_int16_t fw_arch_id;
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u_int16_t fw_branch;
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u_int16_t fw_build;
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u_int32_t result;
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};
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/* Structure for downloading firmware onto the controller. */
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struct tws_cmd_download_firmware {
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u_int8_t sgl_off__opcode;/* 3:5 */
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u_int8_t size;
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u_int8_t request_id;
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u_int8_t unit;
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u_int8_t status;
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u_int8_t flags;
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u_int16_t param;
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u_int8_t sgl[1];
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};
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/* Structure for hard resetting the controller. */
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struct tws_cmd_reset_firmware {
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u_int8_t res1__opcode; /* 3:5 */
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u_int8_t size;
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u_int8_t request_id;
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u_int8_t unit;
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u_int8_t status;
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u_int8_t flags;
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u_int8_t res2;
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u_int8_t param;
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};
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/* Structure for sending get/set param commands. */
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struct tws_cmd_param {
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u_int8_t sgl_off__opcode;/* 3:5 */
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u_int8_t size;
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u_int8_t request_id;
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u_int8_t host_id__unit; /* 4:4 */
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u_int8_t status;
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u_int8_t flags;
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u_int16_t param_count;
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u_int8_t sgl[1];
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};
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/* Generic command packet. */
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struct tws_cmd_generic {
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u_int8_t sgl_off__opcode;/* 3:5 */
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u_int8_t size;
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u_int8_t request_id;
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u_int8_t host_id__unit; /* 4:4 */
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u_int8_t status;
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u_int8_t flags;
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u_int16_t count; /* block cnt, parameter cnt, message credits */
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};
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/* Command packet header. */
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struct tws_command_header {
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u_int8_t sense_data[TWS_SENSE_DATA_LENGTH];
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struct { /* status block - additional sense data */
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u_int16_t srcnum;
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u_int8_t reserved;
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u_int8_t status;
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u_int16_t error;
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u_int8_t res__srcid; /* 4:4 */
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u_int8_t res__severity; /* 5:3 */
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} status_block;
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u_int8_t err_specific_desc[TWS_ERROR_SPECIFIC_DESC_LEN];
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struct { /* sense buffer descriptor */
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u_int8_t size_header;
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u_int16_t request_id;
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u_int8_t size_sense;
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} header_desc;
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};
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/* Command - 1024 byte size including header (128+24+896)*/
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union tws_command_giga {
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struct tws_cmd_init_connect init_connect;
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struct tws_cmd_download_firmware download_fw;
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struct tws_cmd_reset_firmware reset_fw;
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struct tws_cmd_param param;
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struct tws_cmd_generic generic;
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u_int8_t padding[1024 - sizeof(struct tws_command_header)];
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};
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/* driver command pkt - 1024 byte size including header(128+24+744+128) */
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/* h/w & f/w supported command size excluding header 768 */
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struct tws_command_apache {
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u_int8_t res__opcode; /* 3:5 */
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u_int8_t unit;
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u_int16_t lun_l4__req_id; /* 4:12 */
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u_int8_t status;
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u_int8_t sgl_offset; /* offset (in bytes) to sg_list,
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from the end of sgl_entries */
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u_int16_t lun_h4__sgl_entries;
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u_int8_t cdb[16];
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u_int8_t sg_list[744]; /* 768 - 24 */
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u_int8_t padding[128]; /* make it 1024 bytes */
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};
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struct tws_command_packet {
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struct tws_command_header hdr;
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union {
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union tws_command_giga pkt_g;
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struct tws_command_apache pkt_a;
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} cmd;
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};
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/* Structure describing payload for get/set param commands. */
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struct tws_getset_param {
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u_int16_t table_id;
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u_int8_t parameter_id;
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u_int8_t reserved;
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u_int16_t parameter_size_bytes;
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u_int16_t parameter_actual_size_bytes;
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u_int8_t data[1];
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};
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struct tws_outbound_response {
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u_int32_t not_mfa :1; /* 1 if the structure is valid else MFA */
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u_int32_t reserved :7; /* reserved bits */
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u_int32_t status :8; /* should be 0 */
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u_int32_t request_id:16; /* request id */
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
/* Scatter/Gather list entry with 32 bit addresses. */
|
||
|
|
struct tws_sg_desc32 {
|
||
|
|
u_int32_t address;
|
||
|
|
u_int32_t length :24;
|
||
|
|
u_int32_t flag :8;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Scatter/Gather list entry with 64 bit addresses. */
|
||
|
|
struct tws_sg_desc64 {
|
||
|
|
u_int64_t address;
|
||
|
|
u_int64_t length :32;
|
||
|
|
u_int64_t reserved :24;
|
||
|
|
u_int64_t flag :8;
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Packet that describes an AEN/error generated by the controller,
|
||
|
|
* shared with user
|
||
|
|
*/
|
||
|
|
struct tws_event_packet {
|
||
|
|
u_int32_t sequence_id;
|
||
|
|
u_int32_t time_stamp_sec;
|
||
|
|
u_int16_t aen_code;
|
||
|
|
u_int8_t severity;
|
||
|
|
u_int8_t retrieved;
|
||
|
|
u_int8_t repeat_count;
|
||
|
|
u_int8_t parameter_len;
|
||
|
|
u_int8_t parameter_data[TWS_ERROR_SPECIFIC_DESC_LEN];
|
||
|
|
u_int32_t event_src;
|
||
|
|
u_int8_t severity_str[20];
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
#pragma pack()
|
||
|
|
|
||
|
|
struct tws_sense {
|
||
|
|
struct tws_command_header *hdr;
|
||
|
|
u_int64_t hdr_pkt_phy;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct tws_request {
|
||
|
|
struct tws_command_packet *cmd_pkt; /* command pkt */
|
||
|
|
u_int64_t cmd_pkt_phy; /* cmd pkt physical address */
|
||
|
|
void *data; /* ptr to data being passed to fw */
|
||
|
|
u_int32_t length; /* length of data being passed to fw */
|
||
|
|
|
||
|
|
u_int32_t state; /* request state */
|
||
|
|
u_int32_t type; /* request type */
|
||
|
|
u_int32_t flags; /* request flags */
|
||
|
|
|
||
|
|
u_int32_t error_code; /* error during request processing */
|
||
|
|
|
||
|
|
u_int32_t request_id; /* request id for tracking with fw */
|
||
|
|
void (*cb)(struct tws_request *); /* callback func */
|
||
|
|
bus_dmamap_t dma_map; /* dma map */
|
||
|
|
union ccb *ccb_ptr; /* pointer to ccb */
|
||
|
|
struct callout_handle thandle; /* handle to req timeout */
|
||
|
|
struct tws_softc *sc; /* pointer back to ctlr softc */
|
||
|
|
|
||
|
|
struct tws_request *next; /* pointer to next request */
|
||
|
|
struct tws_request *prev; /* pointer to prev request */
|
||
|
|
};
|
||
|
|
|
||
|
|
|