2012-08-15 19:34:23 +00:00
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; RUN: llc < %s -march=arm -mattr=+neon -pre-RA-sched=source -disable-post-ra | FileCheck %s
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2011-02-20 12:57:14 +00:00
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define <8 x i8> @sdivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vrecpe.f32
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;CHECK: vmovn.i32
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2012-08-15 19:34:23 +00:00
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;CHECK: vrecpe.f32
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2011-02-20 12:57:14 +00:00
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;CHECK: vmovn.i32
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;CHECK: vmovn.i16
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = sdiv <8 x i8> %tmp1, %tmp2
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ret <8 x i8> %tmp3
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}
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define <8 x i8> @udivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vrecpe.f32
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;CHECK: vrecps.f32
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2012-08-15 19:34:23 +00:00
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;CHECK: vmovn.i32
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2011-02-20 12:57:14 +00:00
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;CHECK: vrecpe.f32
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;CHECK: vrecps.f32
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;CHECK: vmovn.i32
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;CHECK: vqmovun.s16
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = udiv <8 x i8> %tmp1, %tmp2
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @sdivi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vrecpe.f32
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;CHECK: vrecps.f32
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;CHECK: vmovn.i32
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = sdiv <4 x i16> %tmp1, %tmp2
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ret <4 x i16> %tmp3
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}
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define <4 x i16> @udivi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vrecpe.f32
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;CHECK: vrecps.f32
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;CHECK: vrecps.f32
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;CHECK: vmovn.i32
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = udiv <4 x i16> %tmp1, %tmp2
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ret <4 x i16> %tmp3
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}
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