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freebsd-nq/sys/dev/mii/rgephy.c

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Start each of the license/copyright comments with /*-, minor shuffle of lines
2005-01-06 01:43:34 +00:00
/*-
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
* Copyright (c) 2003
* Bill Paul <wpaul@windriver.com>. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
Remove double __FBSDID and move the remaining one into a common place after the license(s) and before the driver comment (the latter only in drivers not having __FBSDID at that location).
2004-05-29 18:09:10 +00:00
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
/*
Add RTL8211C(L) support. Disable advanced link-down power saving in phy reset. Reported by: nork Tested by: nork
2008-07-02 08:10:18 +00:00
* Driver for the RealTek 8169S/8110S/8211B/8211C internal 10/100/1000 PHY.
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
Add some missing <sys/module.h> includes which are masked by the one on death-row in <sys/kernel.h>
2004-05-30 17:57:46 +00:00
#include <sys/module.h>
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
#include <sys/socket.h>
#include <sys/bus.h>
#include <net/if.h>
#include <net/if_arp.h>
#include <net/if_media.h>
#include <dev/mii/mii.h>
#include <dev/mii/miivar.h>
#include "miidevs.h"
#include <dev/mii/rgephyreg.h>
#include "miibus_if.h"
#include <machine/bus.h>
#include <pci/if_rlreg.h>
static int rgephy_probe(device_t);
static int rgephy_attach(device_t);
Add support for RealTek RTL8211B(L) PHY. It's based on the patch made by Michael Eisele and the patch was slightly modified by me. With this change several NVIDIA ethernet controllers(e.g. MCP61) works. RTL8211B(L) is RealTek's new gigabit PHY. The PHY has several features including crossover correction, polarity correction as well as supporting triple speed(10/100/1000bps). Data transfer between MAC and PHY is via RGMII for 1000baseT, MII for 10baseT/100baseTX. Unfortunately, RealTek used the same model number for RTL8211B(L) PHY so there is no way to discriminate between RTL8211B(L) and its predecessors. ATM RTL8211B uses revision number 2 so checking the revision number seems to be only way to identify it. Obtained from: Michael Eisele [1] Tested by: clemens fischer < ino-qc AT spotteswoode DOT de DOT eu DOT org >
2007-10-29 02:17:07 +00:00
struct rgephy_softc {
struct mii_softc mii_sc;
int mii_model;
int mii_revision;
};
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
static device_method_t rgephy_methods[] = {
/* device interface */
DEVMETHOD(device_probe, rgephy_probe),
DEVMETHOD(device_attach, rgephy_attach),
DEVMETHOD(device_detach, mii_phy_detach),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
{ 0, 0 }
};
static devclass_t rgephy_devclass;
static driver_t rgephy_driver = {
"rgephy",
rgephy_methods,
Add support for RealTek RTL8211B(L) PHY. It's based on the patch made by Michael Eisele and the patch was slightly modified by me. With this change several NVIDIA ethernet controllers(e.g. MCP61) works. RTL8211B(L) is RealTek's new gigabit PHY. The PHY has several features including crossover correction, polarity correction as well as supporting triple speed(10/100/1000bps). Data transfer between MAC and PHY is via RGMII for 1000baseT, MII for 10baseT/100baseTX. Unfortunately, RealTek used the same model number for RTL8211B(L) PHY so there is no way to discriminate between RTL8211B(L) and its predecessors. ATM RTL8211B uses revision number 2 so checking the revision number seems to be only way to identify it. Obtained from: Michael Eisele [1] Tested by: clemens fischer < ino-qc AT spotteswoode DOT de DOT eu DOT org >
2007-10-29 02:17:07 +00:00
sizeof(struct rgephy_softc)
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
};
DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0);
static int rgephy_service(struct mii_softc *, struct mii_data *, int);
static void rgephy_status(struct mii_softc *);
- Change these drivers to take advantage and use the generic IEEE 802.3 annex 31B full duplex flow control as well as the IFM_1000_T master support committed in r215297. For atphy(4) and jmphy(4) this includes changing these PHY drivers to no longer unconditionally advertise support for flow control but only if the selected media has IFM_FLOW set (or MIIF_FORCEPAUSE is set). - Rename {atphy,jmphy}_auto() to {atphy,jmphy}_setmedia() as these handle other media types as well. Reviewed by: yongari (plus additional testing) Obtained from: NetBSD (partially), OpenBSD (partially) MFC after: 2 weeks
2010-11-14 13:31:01 +00:00
static int rgephy_mii_phy_auto(struct mii_softc *, int);
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
static void rgephy_reset(struct mii_softc *);
static void rgephy_loop(struct mii_softc *);
static void rgephy_load_dspcode(struct mii_softc *);
Add a helper function mii_phy_dev_probe(), which wraps around the mii_phy_match() API and takes care of the PHY device probe based on the struct mii_phydesc array and the match return value provided. Convert PHY drivers to take advantage of mii_phy_dev_probe(), converting drivers to provide a mii_phydesc table in the first place where necessary. Reviewed by: yongari MFC after: 2 weeks
2006-12-02 15:32:34 +00:00
static const struct mii_phydesc rgephys[] = {
MII_PHY_DESC(xxREALTEK, RTL8169S),
MII_PHY_END
};
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
static int
Use ansi function definitions in preference to K&R to reduce diffs with NetBSD (and cause it looks cooler).
2005-09-30 19:39:27 +00:00
rgephy_probe(device_t dev)
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
{
Add a helper function mii_phy_dev_probe(), which wraps around the mii_phy_match() API and takes care of the PHY device probe based on the struct mii_phydesc array and the match return value provided. Convert PHY drivers to take advantage of mii_phy_dev_probe(), converting drivers to provide a mii_phydesc table in the first place where necessary. Reviewed by: yongari MFC after: 2 weeks
2006-12-02 15:32:34 +00:00
return (mii_phy_dev_probe(dev, rgephys, BUS_PROBE_DEFAULT));
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
}
static int
Use ansi function definitions in preference to K&R to reduce diffs with NetBSD (and cause it looks cooler).
2005-09-30 19:39:27 +00:00
rgephy_attach(device_t dev)
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
{
Add support for RealTek RTL8211B(L) PHY. It's based on the patch made by Michael Eisele and the patch was slightly modified by me. With this change several NVIDIA ethernet controllers(e.g. MCP61) works. RTL8211B(L) is RealTek's new gigabit PHY. The PHY has several features including crossover correction, polarity correction as well as supporting triple speed(10/100/1000bps). Data transfer between MAC and PHY is via RGMII for 1000baseT, MII for 10baseT/100baseTX. Unfortunately, RealTek used the same model number for RTL8211B(L) PHY so there is no way to discriminate between RTL8211B(L) and its predecessors. ATM RTL8211B uses revision number 2 so checking the revision number seems to be only way to identify it. Obtained from: Michael Eisele [1] Tested by: clemens fischer < ino-qc AT spotteswoode DOT de DOT eu DOT org >
2007-10-29 02:17:07 +00:00
struct rgephy_softc *rsc;
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
struct mii_softc *sc;
struct mii_attach_args *ma;
struct mii_data *mii;
Add support for RealTek RTL8211B(L) PHY. It's based on the patch made by Michael Eisele and the patch was slightly modified by me. With this change several NVIDIA ethernet controllers(e.g. MCP61) works. RTL8211B(L) is RealTek's new gigabit PHY. The PHY has several features including crossover correction, polarity correction as well as supporting triple speed(10/100/1000bps). Data transfer between MAC and PHY is via RGMII for 1000baseT, MII for 10baseT/100baseTX. Unfortunately, RealTek used the same model number for RTL8211B(L) PHY so there is no way to discriminate between RTL8211B(L) and its predecessors. ATM RTL8211B uses revision number 2 so checking the revision number seems to be only way to identify it. Obtained from: Michael Eisele [1] Tested by: clemens fischer < ino-qc AT spotteswoode DOT de DOT eu DOT org >
2007-10-29 02:17:07 +00:00
rsc = device_get_softc(dev);
sc = &rsc->mii_sc;
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
ma = device_get_ivars(dev);
sc->mii_dev = device_get_parent(dev);
Use the mii_data provided via mii_attach_args and mii_pdata respectively instead of reaching out for the softc of the parent.
2010-09-27 20:31:03 +00:00
mii = ma->mii_data;
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
Convert the PHY drivers to honor the mii_flags passed down and convert the NIC drivers as well as the PHY drivers to take advantage of the mii_attach() introduced in r213878 to get rid of certain hacks. For the most part these were: - Artificially limiting miibus_{read,write}reg methods to certain PHY addresses; we now let mii_attach() only probe the PHY at the desired address(es) instead. - PHY drivers setting MIIF_* flags based on the NIC driver they hang off from, partly even based on grabbing and using the softc of the parent; we now pass these flags down from the NIC to the PHY drivers via mii_attach(). This got us rid of all such hacks except those of brgphy() in combination with bce(4) and bge(4), which is way beyond what can be expressed with simple flags. While at it, I took the opportunity to change the NIC drivers to pass up the error returned by mii_attach() (previously by mii_phy_probe()) and unify the error message used in this case where and as appropriate as mii_attach() actually can fail for a number of reasons, not just because of no PHY(s) being present at the expected address(es). Reviewed by: jhb, yongari
2010-10-15 14:52:11 +00:00
sc->mii_flags = miibus_get_flags(dev);
- In the spirit of previous simplifications factor out the checks for a different PHY instance being selected and isolation out into the wrappers around the service methods rather than duplicating them over and over again (besides, a PHY driver shouldn't need to care about which instance it actually is). - Centralize the check for the need to isolate a non-zero PHY instance not supporting isolation in mii_mediachg() and just ignore it rather than panicing, which should sufficient given that a) things are likely to just work anyway if one doesn't plug in more than one port at a time and b) refusing to attach in this case just leaves us in a unknown but most likely also not exactly correct configuration (besides several drivers setting MIIF_NOISOLATE didn't care about these anyway, probably due to setting this flag for no real reason). - Minor fixes like removing unnecessary setting of sc->mii_anegticks, using sc->mii_anegticks instead of hardcoded values etc.
2010-10-02 18:53:12 +00:00
sc->mii_inst = mii->mii_instance++;
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
sc->mii_phy = ma->mii_phyno;
sc->mii_service = rgephy_service;
sc->mii_pdata = mii;
Add support for RealTek RTL8211B(L) PHY. It's based on the patch made by Michael Eisele and the patch was slightly modified by me. With this change several NVIDIA ethernet controllers(e.g. MCP61) works. RTL8211B(L) is RealTek's new gigabit PHY. The PHY has several features including crossover correction, polarity correction as well as supporting triple speed(10/100/1000bps). Data transfer between MAC and PHY is via RGMII for 1000baseT, MII for 10baseT/100baseTX. Unfortunately, RealTek used the same model number for RTL8211B(L) PHY so there is no way to discriminate between RTL8211B(L) and its predecessors. ATM RTL8211B uses revision number 2 so checking the revision number seems to be only way to identify it. Obtained from: Michael Eisele [1] Tested by: clemens fischer < ino-qc AT spotteswoode DOT de DOT eu DOT org >
2007-10-29 02:17:07 +00:00
rsc->mii_model = MII_MODEL(ma->mii_id2);
rsc->mii_revision = MII_REV(ma->mii_id2);
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
#if 0
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
- In the spirit of previous simplifications factor out the checks for a different PHY instance being selected and isolation out into the wrappers around the service methods rather than duplicating them over and over again (besides, a PHY driver shouldn't need to care about which instance it actually is). - Centralize the check for the need to isolate a non-zero PHY instance not supporting isolation in mii_mediachg() and just ignore it rather than panicing, which should sufficient given that a) things are likely to just work anyway if one doesn't plug in more than one port at a time and b) refusing to attach in this case just leaves us in a unknown but most likely also not exactly correct configuration (besides several drivers setting MIIF_NOISOLATE didn't care about these anyway, probably due to setting this flag for no real reason). - Minor fixes like removing unnecessary setting of sc->mii_anegticks, using sc->mii_anegticks instead of hardcoded values etc.
2010-10-02 18:53:12 +00:00
MII_MEDIA_100_TX);
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
#endif
- Change these drivers to take advantage and use the generic IEEE 802.3 annex 31B full duplex flow control as well as the IFM_1000_T master support committed in r215297. For atphy(4) and jmphy(4) this includes changing these PHY drivers to no longer unconditionally advertise support for flow control but only if the selected media has IFM_FLOW set (or MIIF_FORCEPAUSE is set). - Rename {atphy,jmphy}_auto() to {atphy,jmphy}_setmedia() as these handle other media types as well. Reviewed by: yongari (plus additional testing) Obtained from: NetBSD (partially), OpenBSD (partially) MFC after: 2 weeks
2010-11-14 13:31:01 +00:00
/* RTL8169S do not report auto-sense; add manually. */
sc->mii_capabilities = (PHY_READ(sc, MII_BMSR) | BMSR_ANEG) &
ma->mii_capmask;
Correct the previous change: - If we want mii_phy_add_media() to add 1000baseT media, we need to supply sc->mii_extcapabilities. - Fix formatting when announcing autonegotiation support.
2006-12-18 02:14:26 +00:00
if (sc->mii_capabilities & BMSR_EXTSTAT)
sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
device_printf(dev, " ");
- Don't set MIIF_NOISOLATE so rgephy(4) can be used in configurations with multiple PHYs and un-comment case IFM_NONE in case MII_MEDIACHG rgephy_service(). There doesn't seem to be a problem with isolating RTL8169S and their internal PHY. - Take advantage of mii_phy_add_media(). [1] Obtained from: NetBSD [1] Tested by: yongari MFC after: 2 weeks
2006-12-02 19:48:53 +00:00
mii_phy_add_media(sc);
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
printf("\n");
#undef ADD
Add support for the RealTek 8169SC/8110SC and RTL8101E devices. The latter is a PCIe 10/100 chip. Finally fix the EEPROM reading code so that we can access the EEPROMs on all devices. In order to access the EEPROM, we must select 'EEPROM programming' mode, and then set the EEPROM chip select bit. Previously, we were setting both bits simultaneously, which doesn't work: they must be set in the right sequence. Always obtain the station address from the EEPROM, now that EEPROM reading works correctly. Make the TX interrupt moderation code based on the internal timer optional and turned off by default. Make the re_diag() routine conditional and off by default. When it is on, only use it for the original 8169, which was the only device that that really needed it. Modify interrupt handling to use a fast interrupt handler and fast taskqeueue. Correct the rgephy driver so that it only applies the DSP fixup for PHY revs 0 and 1. Later chips are fixed and don't need the fixup. Make the rgephy driver advertise both 1000_FD and 1000_HD bits in autoneg mode. A couple of the devices don't autoneg correctly unless configured this way.
2006-06-26 20:31:32 +00:00
rgephy_reset(sc);
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
MIIBUS_MEDIAINIT(sc->mii_dev);
Some style changes to a couple of PHY drivers: - Fix some whitespace nits. - Fix some spelling in comments. - Use MII_ANEGTICKS instead of 5. - Don't define variables in nested scope. - Remove superfluous returns at the end of void functions. - Remove unused static global rgephy_mii_model. - Remove dupe $Id$ in tdkphy(4). - Sort brgphys table. MFC after: 2 weeks
2006-12-02 19:36:25 +00:00
return (0);
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
}
static int
Use ansi function definitions in preference to K&R to reduce diffs with NetBSD (and cause it looks cooler).
2005-09-30 19:39:27 +00:00
rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
{
Add support for RealTek RTL8211B(L) PHY. It's based on the patch made by Michael Eisele and the patch was slightly modified by me. With this change several NVIDIA ethernet controllers(e.g. MCP61) works. RTL8211B(L) is RealTek's new gigabit PHY. The PHY has several features including crossover correction, polarity correction as well as supporting triple speed(10/100/1000bps). Data transfer between MAC and PHY is via RGMII for 1000baseT, MII for 10baseT/100baseTX. Unfortunately, RealTek used the same model number for RTL8211B(L) PHY so there is no way to discriminate between RTL8211B(L) and its predecessors. ATM RTL8211B uses revision number 2 so checking the revision number seems to be only way to identify it. Obtained from: Michael Eisele [1] Tested by: clemens fischer < ino-qc AT spotteswoode DOT de DOT eu DOT org >
2007-10-29 02:17:07 +00:00
struct rgephy_softc *rsc;
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
Due to the poor PHY documentation from RealTek I can't sure but I think the RealTek PHY needs driver to set RGEPHY_BMCR_AUTOEN bit of RGEPHY_MII_BMCR register and proper ANAR register setting for manual media type selection. This fixes long standing manual media type selection bug in rgephy(4). Reported by: Jelte Jansen <jelte AT NLnetLabs DOT nl> Tested by: Jelte Jansen <jelte AT NLnetLabs DOT nl>
2006-08-12 01:38:49 +00:00
int reg, speed, gig, anar;
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
Add support for RealTek RTL8211B(L) PHY. It's based on the patch made by Michael Eisele and the patch was slightly modified by me. With this change several NVIDIA ethernet controllers(e.g. MCP61) works. RTL8211B(L) is RealTek's new gigabit PHY. The PHY has several features including crossover correction, polarity correction as well as supporting triple speed(10/100/1000bps). Data transfer between MAC and PHY is via RGMII for 1000baseT, MII for 10baseT/100baseTX. Unfortunately, RealTek used the same model number for RTL8211B(L) PHY so there is no way to discriminate between RTL8211B(L) and its predecessors. ATM RTL8211B uses revision number 2 so checking the revision number seems to be only way to identify it. Obtained from: Michael Eisele [1] Tested by: clemens fischer < ino-qc AT spotteswoode DOT de DOT eu DOT org >
2007-10-29 02:17:07 +00:00
rsc = (struct rgephy_softc *)sc;
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
switch (cmd) {
case MII_POLLSTAT:
break;
case MII_MEDIACHG:
/*
* If the interface is not up, don't do anything.
*/
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
break;
rgephy_reset(sc); /* XXX hardware bug work-around */
Due to the poor PHY documentation from RealTek I can't sure but I think the RealTek PHY needs driver to set RGEPHY_BMCR_AUTOEN bit of RGEPHY_MII_BMCR register and proper ANAR register setting for manual media type selection. This fixes long standing manual media type selection bug in rgephy(4). Reported by: Jelte Jansen <jelte AT NLnetLabs DOT nl> Tested by: Jelte Jansen <jelte AT NLnetLabs DOT nl>
2006-08-12 01:38:49 +00:00
anar = PHY_READ(sc, RGEPHY_MII_ANAR);
- Change these drivers to take advantage and use the generic IEEE 802.3 annex 31B full duplex flow control as well as the IFM_1000_T master support committed in r215297. For atphy(4) and jmphy(4) this includes changing these PHY drivers to no longer unconditionally advertise support for flow control but only if the selected media has IFM_FLOW set (or MIIF_FORCEPAUSE is set). - Rename {atphy,jmphy}_auto() to {atphy,jmphy}_setmedia() as these handle other media types as well. Reviewed by: yongari (plus additional testing) Obtained from: NetBSD (partially), OpenBSD (partially) MFC after: 2 weeks
2010-11-14 13:31:01 +00:00
anar &= ~(RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP |
RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX |
Due to the poor PHY documentation from RealTek I can't sure but I think the RealTek PHY needs driver to set RGEPHY_BMCR_AUTOEN bit of RGEPHY_MII_BMCR register and proper ANAR register setting for manual media type selection. This fixes long standing manual media type selection bug in rgephy(4). Reported by: Jelte Jansen <jelte AT NLnetLabs DOT nl> Tested by: Jelte Jansen <jelte AT NLnetLabs DOT nl>
2006-08-12 01:38:49 +00:00
RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10);
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
switch (IFM_SUBTYPE(ife->ifm_media)) {
case IFM_AUTO:
#ifdef foo
/*
* If we're already in auto mode, just return.
*/
if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN)
return (0);
#endif
- Change these drivers to take advantage and use the generic IEEE 802.3 annex 31B full duplex flow control as well as the IFM_1000_T master support committed in r215297. For atphy(4) and jmphy(4) this includes changing these PHY drivers to no longer unconditionally advertise support for flow control but only if the selected media has IFM_FLOW set (or MIIF_FORCEPAUSE is set). - Rename {atphy,jmphy}_auto() to {atphy,jmphy}_setmedia() as these handle other media types as well. Reviewed by: yongari (plus additional testing) Obtained from: NetBSD (partially), OpenBSD (partially) MFC after: 2 weeks
2010-11-14 13:31:01 +00:00
(void)rgephy_mii_phy_auto(sc, ife->ifm_media);
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
break;
case IFM_1000_T:
speed = RGEPHY_S1000;
goto setit;
case IFM_100_TX:
speed = RGEPHY_S100;
Due to the poor PHY documentation from RealTek I can't sure but I think the RealTek PHY needs driver to set RGEPHY_BMCR_AUTOEN bit of RGEPHY_MII_BMCR register and proper ANAR register setting for manual media type selection. This fixes long standing manual media type selection bug in rgephy(4). Reported by: Jelte Jansen <jelte AT NLnetLabs DOT nl> Tested by: Jelte Jansen <jelte AT NLnetLabs DOT nl>
2006-08-12 01:38:49 +00:00
anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX;
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
goto setit;
case IFM_10_T:
speed = RGEPHY_S10;
Due to the poor PHY documentation from RealTek I can't sure but I think the RealTek PHY needs driver to set RGEPHY_BMCR_AUTOEN bit of RGEPHY_MII_BMCR register and proper ANAR register setting for manual media type selection. This fixes long standing manual media type selection bug in rgephy(4). Reported by: Jelte Jansen <jelte AT NLnetLabs DOT nl> Tested by: Jelte Jansen <jelte AT NLnetLabs DOT nl>
2006-08-12 01:38:49 +00:00
anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10;
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
setit:
rgephy_loop(sc);
if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
speed |= RGEPHY_BMCR_FDX;
gig = RGEPHY_1000CTL_AFD;
Due to the poor PHY documentation from RealTek I can't sure but I think the RealTek PHY needs driver to set RGEPHY_BMCR_AUTOEN bit of RGEPHY_MII_BMCR register and proper ANAR register setting for manual media type selection. This fixes long standing manual media type selection bug in rgephy(4). Reported by: Jelte Jansen <jelte AT NLnetLabs DOT nl> Tested by: Jelte Jansen <jelte AT NLnetLabs DOT nl>
2006-08-12 01:38:49 +00:00
anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10);
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
} else {
gig = RGEPHY_1000CTL_AHD;
Due to the poor PHY documentation from RealTek I can't sure but I think the RealTek PHY needs driver to set RGEPHY_BMCR_AUTOEN bit of RGEPHY_MII_BMCR register and proper ANAR register setting for manual media type selection. This fixes long standing manual media type selection bug in rgephy(4). Reported by: Jelte Jansen <jelte AT NLnetLabs DOT nl> Tested by: Jelte Jansen <jelte AT NLnetLabs DOT nl>
2006-08-12 01:38:49 +00:00
anar &=
~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD);
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
}
Due to the poor PHY documentation from RealTek I can't sure but I think the RealTek PHY needs driver to set RGEPHY_BMCR_AUTOEN bit of RGEPHY_MII_BMCR register and proper ANAR register setting for manual media type selection. This fixes long standing manual media type selection bug in rgephy(4). Reported by: Jelte Jansen <jelte AT NLnetLabs DOT nl> Tested by: Jelte Jansen <jelte AT NLnetLabs DOT nl>
2006-08-12 01:38:49 +00:00
if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) {
PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0);
PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
PHY_WRITE(sc, RGEPHY_MII_BMCR, speed |
- Change these drivers to take advantage and use the generic IEEE 802.3 annex 31B full duplex flow control as well as the IFM_1000_T master support committed in r215297. For atphy(4) and jmphy(4) this includes changing these PHY drivers to no longer unconditionally advertise support for flow control but only if the selected media has IFM_FLOW set (or MIIF_FORCEPAUSE is set). - Rename {atphy,jmphy}_auto() to {atphy,jmphy}_setmedia() as these handle other media types as well. Reviewed by: yongari (plus additional testing) Obtained from: NetBSD (partially), OpenBSD (partially) MFC after: 2 weeks
2010-11-14 13:31:01 +00:00
RGEPHY_BMCR_AUTOEN |
RGEPHY_BMCR_STARTNEG);
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
break;
Due to the poor PHY documentation from RealTek I can't sure but I think the RealTek PHY needs driver to set RGEPHY_BMCR_AUTOEN bit of RGEPHY_MII_BMCR register and proper ANAR register setting for manual media type selection. This fixes long standing manual media type selection bug in rgephy(4). Reported by: Jelte Jansen <jelte AT NLnetLabs DOT nl> Tested by: Jelte Jansen <jelte AT NLnetLabs DOT nl>
2006-08-12 01:38:49 +00:00
}
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
- Change these drivers to take advantage and use the generic IEEE 802.3 annex 31B full duplex flow control as well as the IFM_1000_T master support committed in r215297. For atphy(4) and jmphy(4) this includes changing these PHY drivers to no longer unconditionally advertise support for flow control but only if the selected media has IFM_FLOW set (or MIIF_FORCEPAUSE is set). - Rename {atphy,jmphy}_auto() to {atphy,jmphy}_setmedia() as these handle other media types as well. Reviewed by: yongari (plus additional testing) Obtained from: NetBSD (partially), OpenBSD (partially) MFC after: 2 weeks
2010-11-14 13:31:01 +00:00
if ((ife->ifm_media & IFM_FLOW) != 0 ||
(sc->mii_flags & MIIF_FORCEPAUSE) != 0)
anar |= RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP;
gig |= RGEPHY_1000CTL_MSE;
if ((ife->ifm_media & IFM_ETH_MASTER) != 0)
gig |= RGEPHY_1000CTL_MSC;
PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig);
PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
Due to the poor PHY documentation from RealTek I can't sure but I think the RealTek PHY needs driver to set RGEPHY_BMCR_AUTOEN bit of RGEPHY_MII_BMCR register and proper ANAR register setting for manual media type selection. This fixes long standing manual media type selection bug in rgephy(4). Reported by: Jelte Jansen <jelte AT NLnetLabs DOT nl> Tested by: Jelte Jansen <jelte AT NLnetLabs DOT nl>
2006-08-12 01:38:49 +00:00
PHY_WRITE(sc, RGEPHY_MII_BMCR, speed |
RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
break;
case IFM_NONE:
- Change these drivers to take advantage and use the generic IEEE 802.3 annex 31B full duplex flow control as well as the IFM_1000_T master support committed in r215297. For atphy(4) and jmphy(4) this includes changing these PHY drivers to no longer unconditionally advertise support for flow control but only if the selected media has IFM_FLOW set (or MIIF_FORCEPAUSE is set). - Rename {atphy,jmphy}_auto() to {atphy,jmphy}_setmedia() as these handle other media types as well. Reviewed by: yongari (plus additional testing) Obtained from: NetBSD (partially), OpenBSD (partially) MFC after: 2 weeks
2010-11-14 13:31:01 +00:00
PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN);
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
break;
default:
return (EINVAL);
}
break;
case MII_TICK:
/*
* Is the interface even up?
*/
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
return (0);
/*
* Only used for autonegotiation.
*/
o RTL8169S/8110S integrated PHY and RTL8211B are gigabit PHYs so set mii_anegticks to MII_ANEGTICKS_GIGE and use it. Previously it used to MII_ANEGTICKS which may not be enough to wait before retrying autonegotiation process at 1000bps. o Reset autonegotation timer if media option is not IFM_AUTO or we got a valid link. o Announce link loss right after it happends. o Autonegiation is retried every mii_anegticks seconds. o Report link state changes right after setting autonegotiation.
2007-10-29 02:06:15 +00:00
if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
sc->mii_ticks = 0;
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
break;
o RTL8169S/8110S integrated PHY and RTL8211B are gigabit PHYs so set mii_anegticks to MII_ANEGTICKS_GIGE and use it. Previously it used to MII_ANEGTICKS which may not be enough to wait before retrying autonegotiation process at 1000bps. o Reset autonegotation timer if media option is not IFM_AUTO or we got a valid link. o Announce link loss right after it happends. o Autonegiation is retried every mii_anegticks seconds. o Report link state changes right after setting autonegotiation.
2007-10-29 02:06:15 +00:00
}
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
/*
* Check to see if we have link. If we do, we don't
* need to restart the autonegotiation process. Read
* the BMSR twice in case it's latched.
*/
Add support for RealTek RTL8211B(L) PHY. It's based on the patch made by Michael Eisele and the patch was slightly modified by me. With this change several NVIDIA ethernet controllers(e.g. MCP61) works. RTL8211B(L) is RealTek's new gigabit PHY. The PHY has several features including crossover correction, polarity correction as well as supporting triple speed(10/100/1000bps). Data transfer between MAC and PHY is via RGMII for 1000baseT, MII for 10baseT/100baseTX. Unfortunately, RealTek used the same model number for RTL8211B(L) PHY so there is no way to discriminate between RTL8211B(L) and its predecessors. ATM RTL8211B uses revision number 2 so checking the revision number seems to be only way to identify it. Obtained from: Michael Eisele [1] Tested by: clemens fischer < ino-qc AT spotteswoode DOT de DOT eu DOT org >
2007-10-29 02:17:07 +00:00
if (rsc->mii_revision >= 2) {
/* RTL8211B(L) */
reg = PHY_READ(sc, RGEPHY_MII_SSR);
if (reg & RGEPHY_SSR_LINK) {
sc->mii_ticks = 0;
break;
}
} else {
reg = PHY_READ(sc, RL_GMEDIASTAT);
if (reg & RL_GMEDIASTAT_LINK) {
sc->mii_ticks = 0;
break;
}
o RTL8169S/8110S integrated PHY and RTL8211B are gigabit PHYs so set mii_anegticks to MII_ANEGTICKS_GIGE and use it. Previously it used to MII_ANEGTICKS which may not be enough to wait before retrying autonegotiation process at 1000bps. o Reset autonegotation timer if media option is not IFM_AUTO or we got a valid link. o Announce link loss right after it happends. o Autonegiation is retried every mii_anegticks seconds. o Report link state changes right after setting autonegotiation.
2007-10-29 02:06:15 +00:00
}
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
o RTL8169S/8110S integrated PHY and RTL8211B are gigabit PHYs so set mii_anegticks to MII_ANEGTICKS_GIGE and use it. Previously it used to MII_ANEGTICKS which may not be enough to wait before retrying autonegotiation process at 1000bps. o Reset autonegotation timer if media option is not IFM_AUTO or we got a valid link. o Announce link loss right after it happends. o Autonegiation is retried every mii_anegticks seconds. o Report link state changes right after setting autonegotiation.
2007-10-29 02:06:15 +00:00
/* Announce link loss right after it happens. */
if (sc->mii_ticks++ == 0)
Correct the phy_service() routine case MII_TICK to correctly track the falling edge of a media state change. This is in preparation for media state change notification to the routing socket. No objections by: sam, wpaul, ru, bms Brucification by: bde
2004-05-03 13:01:34 +00:00
break;
Some style changes to a couple of PHY drivers: - Fix some whitespace nits. - Fix some spelling in comments. - Use MII_ANEGTICKS instead of 5. - Don't define variables in nested scope. - Remove superfluous returns at the end of void functions. - Remove unused static global rgephy_mii_model. - Remove dupe $Id$ in tdkphy(4). - Sort brgphys table. MFC after: 2 weeks
2006-12-02 19:36:25 +00:00
o RTL8169S/8110S integrated PHY and RTL8211B are gigabit PHYs so set mii_anegticks to MII_ANEGTICKS_GIGE and use it. Previously it used to MII_ANEGTICKS which may not be enough to wait before retrying autonegotiation process at 1000bps. o Reset autonegotation timer if media option is not IFM_AUTO or we got a valid link. o Announce link loss right after it happends. o Autonegiation is retried every mii_anegticks seconds. o Report link state changes right after setting autonegotiation.
2007-10-29 02:06:15 +00:00
/* Only retry autonegotiation every mii_anegticks seconds. */
if (sc->mii_ticks <= sc->mii_anegticks)
return (0);
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
sc->mii_ticks = 0;
- Change these drivers to take advantage and use the generic IEEE 802.3 annex 31B full duplex flow control as well as the IFM_1000_T master support committed in r215297. For atphy(4) and jmphy(4) this includes changing these PHY drivers to no longer unconditionally advertise support for flow control but only if the selected media has IFM_FLOW set (or MIIF_FORCEPAUSE is set). - Rename {atphy,jmphy}_auto() to {atphy,jmphy}_setmedia() as these handle other media types as well. Reviewed by: yongari (plus additional testing) Obtained from: NetBSD (partially), OpenBSD (partially) MFC after: 2 weeks
2010-11-14 13:31:01 +00:00
rgephy_mii_phy_auto(sc, ife->ifm_media);
o RTL8169S/8110S integrated PHY and RTL8211B are gigabit PHYs so set mii_anegticks to MII_ANEGTICKS_GIGE and use it. Previously it used to MII_ANEGTICKS which may not be enough to wait before retrying autonegotiation process at 1000bps. o Reset autonegotation timer if media option is not IFM_AUTO or we got a valid link. o Announce link loss right after it happends. o Autonegiation is retried every mii_anegticks seconds. o Report link state changes right after setting autonegotiation.
2007-10-29 02:06:15 +00:00
break;
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
}
/* Update the media status. */
rgephy_status(sc);
/*
* Callback if something changed. Note that we need to poke
Clean up dead code.
2003-09-11 08:28:38 +00:00
* the DSP on the RealTek PHYs if the media changes.
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
*
*/
Some style changes to a couple of PHY drivers: - Fix some whitespace nits. - Fix some spelling in comments. - Use MII_ANEGTICKS instead of 5. - Don't define variables in nested scope. - Remove superfluous returns at the end of void functions. - Remove unused static global rgephy_mii_model. - Remove dupe $Id$ in tdkphy(4). - Sort brgphys table. MFC after: 2 weeks
2006-12-02 19:36:25 +00:00
if (sc->mii_media_active != mii->mii_media_active ||
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
sc->mii_media_status != mii->mii_media_status ||
cmd == MII_MEDIACHG) {
rgephy_load_dspcode(sc);
}
Correct the phy_service() routine case MII_TICK to correctly track the falling edge of a media state change. This is in preparation for media state change notification to the routing socket. No objections by: sam, wpaul, ru, bms Brucification by: bde
2004-05-03 13:01:34 +00:00
mii_phy_update(sc, cmd);
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
return (0);
}
static void
Use ansi function definitions in preference to K&R to reduce diffs with NetBSD (and cause it looks cooler).
2005-09-30 19:39:27 +00:00
rgephy_status(struct mii_softc *sc)
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
{
Add support for RealTek RTL8211B(L) PHY. It's based on the patch made by Michael Eisele and the patch was slightly modified by me. With this change several NVIDIA ethernet controllers(e.g. MCP61) works. RTL8211B(L) is RealTek's new gigabit PHY. The PHY has several features including crossover correction, polarity correction as well as supporting triple speed(10/100/1000bps). Data transfer between MAC and PHY is via RGMII for 1000baseT, MII for 10baseT/100baseTX. Unfortunately, RealTek used the same model number for RTL8211B(L) PHY so there is no way to discriminate between RTL8211B(L) and its predecessors. ATM RTL8211B uses revision number 2 so checking the revision number seems to be only way to identify it. Obtained from: Michael Eisele [1] Tested by: clemens fischer < ino-qc AT spotteswoode DOT de DOT eu DOT org >
2007-10-29 02:17:07 +00:00
struct rgephy_softc *rsc;
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
struct mii_data *mii = sc->mii_pdata;
Clean up dead code.
2003-09-11 08:28:38 +00:00
int bmsr, bmcr;
Add support for RealTek RTL8211B(L) PHY. It's based on the patch made by Michael Eisele and the patch was slightly modified by me. With this change several NVIDIA ethernet controllers(e.g. MCP61) works. RTL8211B(L) is RealTek's new gigabit PHY. The PHY has several features including crossover correction, polarity correction as well as supporting triple speed(10/100/1000bps). Data transfer between MAC and PHY is via RGMII for 1000baseT, MII for 10baseT/100baseTX. Unfortunately, RealTek used the same model number for RTL8211B(L) PHY so there is no way to discriminate between RTL8211B(L) and its predecessors. ATM RTL8211B uses revision number 2 so checking the revision number seems to be only way to identify it. Obtained from: Michael Eisele [1] Tested by: clemens fischer < ino-qc AT spotteswoode DOT de DOT eu DOT org >
2007-10-29 02:17:07 +00:00
uint16_t ssr;
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
mii->mii_media_status = IFM_AVALID;
mii->mii_media_active = IFM_ETHER;
Add support for RealTek RTL8211B(L) PHY. It's based on the patch made by Michael Eisele and the patch was slightly modified by me. With this change several NVIDIA ethernet controllers(e.g. MCP61) works. RTL8211B(L) is RealTek's new gigabit PHY. The PHY has several features including crossover correction, polarity correction as well as supporting triple speed(10/100/1000bps). Data transfer between MAC and PHY is via RGMII for 1000baseT, MII for 10baseT/100baseTX. Unfortunately, RealTek used the same model number for RTL8211B(L) PHY so there is no way to discriminate between RTL8211B(L) and its predecessors. ATM RTL8211B uses revision number 2 so checking the revision number seems to be only way to identify it. Obtained from: Michael Eisele [1] Tested by: clemens fischer < ino-qc AT spotteswoode DOT de DOT eu DOT org >
2007-10-29 02:17:07 +00:00
rsc = (struct rgephy_softc *)sc;
if (rsc->mii_revision >= 2) {
ssr = PHY_READ(sc, RGEPHY_MII_SSR);
if (ssr & RGEPHY_SSR_LINK)
mii->mii_media_status |= IFM_ACTIVE;
} else {
bmsr = PHY_READ(sc, RL_GMEDIASTAT);
if (bmsr & RL_GMEDIASTAT_LINK)
mii->mii_media_status |= IFM_ACTIVE;
}
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);
Add detection of isolation state. PR: kern/76710
2008-03-05 01:15:10 +00:00
if (bmcr & RGEPHY_BMCR_ISO) {
mii->mii_media_active |= IFM_NONE;
mii->mii_media_status = 0;
return;
}
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
if (bmcr & RGEPHY_BMCR_LOOP)
mii->mii_media_active |= IFM_LOOP;
if (bmcr & RGEPHY_BMCR_AUTOEN) {
if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) {
/* Erg, still trying, I guess... */
mii->mii_media_active |= IFM_NONE;
return;
}
}
Add support for RealTek RTL8211B(L) PHY. It's based on the patch made by Michael Eisele and the patch was slightly modified by me. With this change several NVIDIA ethernet controllers(e.g. MCP61) works. RTL8211B(L) is RealTek's new gigabit PHY. The PHY has several features including crossover correction, polarity correction as well as supporting triple speed(10/100/1000bps). Data transfer between MAC and PHY is via RGMII for 1000baseT, MII for 10baseT/100baseTX. Unfortunately, RealTek used the same model number for RTL8211B(L) PHY so there is no way to discriminate between RTL8211B(L) and its predecessors. ATM RTL8211B uses revision number 2 so checking the revision number seems to be only way to identify it. Obtained from: Michael Eisele [1] Tested by: clemens fischer < ino-qc AT spotteswoode DOT de DOT eu DOT org >
2007-10-29 02:17:07 +00:00
if (rsc->mii_revision >= 2) {
ssr = PHY_READ(sc, RGEPHY_MII_SSR);
switch (ssr & RGEPHY_SSR_SPD_MASK) {
case RGEPHY_SSR_S1000:
mii->mii_media_active |= IFM_1000_T;
break;
case RGEPHY_SSR_S100:
mii->mii_media_active |= IFM_100_TX;
break;
case RGEPHY_SSR_S10:
mii->mii_media_active |= IFM_10_T;
break;
default:
mii->mii_media_active |= IFM_NONE;
break;
}
if (ssr & RGEPHY_SSR_FDX)
mii->mii_media_active |= IFM_FDX;
else
mii->mii_media_active |= IFM_HDX;
} else {
bmsr = PHY_READ(sc, RL_GMEDIASTAT);
if (bmsr & RL_GMEDIASTAT_1000MBPS)
mii->mii_media_active |= IFM_1000_T;
else if (bmsr & RL_GMEDIASTAT_100MBPS)
mii->mii_media_active |= IFM_100_TX;
else if (bmsr & RL_GMEDIASTAT_10MBPS)
mii->mii_media_active |= IFM_10_T;
else
mii->mii_media_active |= IFM_NONE;
if (bmsr & RL_GMEDIASTAT_FDX)
mii->mii_media_active |= IFM_FDX;
else
mii->mii_media_active |= IFM_HDX;
}
- Change these drivers to take advantage and use the generic IEEE 802.3 annex 31B full duplex flow control as well as the IFM_1000_T master support committed in r215297. For atphy(4) and jmphy(4) this includes changing these PHY drivers to no longer unconditionally advertise support for flow control but only if the selected media has IFM_FLOW set (or MIIF_FORCEPAUSE is set). - Rename {atphy,jmphy}_auto() to {atphy,jmphy}_setmedia() as these handle other media types as well. Reviewed by: yongari (plus additional testing) Obtained from: NetBSD (partially), OpenBSD (partially) MFC after: 2 weeks
2010-11-14 13:31:01 +00:00
if ((mii->mii_media_active & IFM_FDX) != 0)
mii->mii_media_active |= mii_phy_flowstatus(sc);
if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
(PHY_READ(sc, RGEPHY_MII_1000STS) & RGEPHY_1000STS_MSR) != 0)
mii->mii_media_active |= IFM_ETH_MASTER;
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
}
static int
- Change these drivers to take advantage and use the generic IEEE 802.3 annex 31B full duplex flow control as well as the IFM_1000_T master support committed in r215297. For atphy(4) and jmphy(4) this includes changing these PHY drivers to no longer unconditionally advertise support for flow control but only if the selected media has IFM_FLOW set (or MIIF_FORCEPAUSE is set). - Rename {atphy,jmphy}_auto() to {atphy,jmphy}_setmedia() as these handle other media types as well. Reviewed by: yongari (plus additional testing) Obtained from: NetBSD (partially), OpenBSD (partially) MFC after: 2 weeks
2010-11-14 13:31:01 +00:00
rgephy_mii_phy_auto(struct mii_softc *sc, int media)
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
{
- Change these drivers to take advantage and use the generic IEEE 802.3 annex 31B full duplex flow control as well as the IFM_1000_T master support committed in r215297. For atphy(4) and jmphy(4) this includes changing these PHY drivers to no longer unconditionally advertise support for flow control but only if the selected media has IFM_FLOW set (or MIIF_FORCEPAUSE is set). - Rename {atphy,jmphy}_auto() to {atphy,jmphy}_setmedia() as these handle other media types as well. Reviewed by: yongari (plus additional testing) Obtained from: NetBSD (partially), OpenBSD (partially) MFC after: 2 weeks
2010-11-14 13:31:01 +00:00
int anar;
Some style changes to a couple of PHY drivers: - Fix some whitespace nits. - Fix some spelling in comments. - Use MII_ANEGTICKS instead of 5. - Don't define variables in nested scope. - Remove superfluous returns at the end of void functions. - Remove unused static global rgephy_mii_model. - Remove dupe $Id$ in tdkphy(4). - Sort brgphys table. MFC after: 2 weeks
2006-12-02 19:36:25 +00:00
- Change these drivers to take advantage and use the generic IEEE 802.3 annex 31B full duplex flow control as well as the IFM_1000_T master support committed in r215297. For atphy(4) and jmphy(4) this includes changing these PHY drivers to no longer unconditionally advertise support for flow control but only if the selected media has IFM_FLOW set (or MIIF_FORCEPAUSE is set). - Rename {atphy,jmphy}_auto() to {atphy,jmphy}_setmedia() as these handle other media types as well. Reviewed by: yongari (plus additional testing) Obtained from: NetBSD (partially), OpenBSD (partially) MFC after: 2 weeks
2010-11-14 13:31:01 +00:00
rgephy_loop(sc);
rgephy_reset(sc);
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
- Change these drivers to take advantage and use the generic IEEE 802.3 annex 31B full duplex flow control as well as the IFM_1000_T master support committed in r215297. For atphy(4) and jmphy(4) this includes changing these PHY drivers to no longer unconditionally advertise support for flow control but only if the selected media has IFM_FLOW set (or MIIF_FORCEPAUSE is set). - Rename {atphy,jmphy}_auto() to {atphy,jmphy}_setmedia() as these handle other media types as well. Reviewed by: yongari (plus additional testing) Obtained from: NetBSD (partially), OpenBSD (partially) MFC after: 2 weeks
2010-11-14 13:31:01 +00:00
anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
if ((media & IFM_FLOW) != 0 || (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
anar |= RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP;
PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
DELAY(1000);
- Change these drivers to take advantage and use the generic IEEE 802.3 annex 31B full duplex flow control as well as the IFM_1000_T master support committed in r215297. For atphy(4) and jmphy(4) this includes changing these PHY drivers to no longer unconditionally advertise support for flow control but only if the selected media has IFM_FLOW set (or MIIF_FORCEPAUSE is set). - Rename {atphy,jmphy}_auto() to {atphy,jmphy}_setmedia() as these handle other media types as well. Reviewed by: yongari (plus additional testing) Obtained from: NetBSD (partially), OpenBSD (partially) MFC after: 2 weeks
2010-11-14 13:31:01 +00:00
PHY_WRITE(sc, RGEPHY_MII_1000CTL,
RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD);
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
DELAY(1000);
- Change these drivers to take advantage and use the generic IEEE 802.3 annex 31B full duplex flow control as well as the IFM_1000_T master support committed in r215297. For atphy(4) and jmphy(4) this includes changing these PHY drivers to no longer unconditionally advertise support for flow control but only if the selected media has IFM_FLOW set (or MIIF_FORCEPAUSE is set). - Rename {atphy,jmphy}_auto() to {atphy,jmphy}_setmedia() as these handle other media types as well. Reviewed by: yongari (plus additional testing) Obtained from: NetBSD (partially), OpenBSD (partially) MFC after: 2 weeks
2010-11-14 13:31:01 +00:00
PHY_WRITE(sc, RGEPHY_MII_BMCR,
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
DELAY(100);
return (EJUSTRETURN);
}
static void
rgephy_loop(struct mii_softc *sc)
{
Add support for RealTek RTL8211B(L) PHY. It's based on the patch made by Michael Eisele and the patch was slightly modified by me. With this change several NVIDIA ethernet controllers(e.g. MCP61) works. RTL8211B(L) is RealTek's new gigabit PHY. The PHY has several features including crossover correction, polarity correction as well as supporting triple speed(10/100/1000bps). Data transfer between MAC and PHY is via RGMII for 1000baseT, MII for 10baseT/100baseTX. Unfortunately, RealTek used the same model number for RTL8211B(L) PHY so there is no way to discriminate between RTL8211B(L) and its predecessors. ATM RTL8211B uses revision number 2 so checking the revision number seems to be only way to identify it. Obtained from: Michael Eisele [1] Tested by: clemens fischer < ino-qc AT spotteswoode DOT de DOT eu DOT org >
2007-10-29 02:17:07 +00:00
struct rgephy_softc *rsc;
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
int i;
Add support for RealTek RTL8211B(L) PHY. It's based on the patch made by Michael Eisele and the patch was slightly modified by me. With this change several NVIDIA ethernet controllers(e.g. MCP61) works. RTL8211B(L) is RealTek's new gigabit PHY. The PHY has several features including crossover correction, polarity correction as well as supporting triple speed(10/100/1000bps). Data transfer between MAC and PHY is via RGMII for 1000baseT, MII for 10baseT/100baseTX. Unfortunately, RealTek used the same model number for RTL8211B(L) PHY so there is no way to discriminate between RTL8211B(L) and its predecessors. ATM RTL8211B uses revision number 2 so checking the revision number seems to be only way to identify it. Obtained from: Michael Eisele [1] Tested by: clemens fischer < ino-qc AT spotteswoode DOT de DOT eu DOT org >
2007-10-29 02:17:07 +00:00
rsc = (struct rgephy_softc *)sc;
if (rsc->mii_revision < 2) {
PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
DELAY(1000);
}
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
for (i = 0; i < 15000; i++) {
Some style changes to a couple of PHY drivers: - Fix some whitespace nits. - Fix some spelling in comments. - Use MII_ANEGTICKS instead of 5. - Don't define variables in nested scope. - Remove superfluous returns at the end of void functions. - Remove unused static global rgephy_mii_model. - Remove dupe $Id$ in tdkphy(4). - Sort brgphys table. MFC after: 2 weeks
2006-12-02 19:36:25 +00:00
if (!(PHY_READ(sc, RGEPHY_MII_BMSR) & RGEPHY_BMSR_LINK)) {
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
#if 0
device_printf(sc->mii_dev, "looped %d\n", i);
#endif
break;
}
DELAY(10);
}
}
#define PHY_SETBIT(x, y, z) \
PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
#define PHY_CLRBIT(x, y, z) \
PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
Clean up dead code.
2003-09-11 08:28:38 +00:00
/*
* Initialize RealTek PHY per the datasheet. The DSP in the PHYs of
* existing revisions of the 8169S/8110S chips need to be tuned in
Add support for the RealTek 8169SC/8110SC and RTL8101E devices. The latter is a PCIe 10/100 chip. Finally fix the EEPROM reading code so that we can access the EEPROMs on all devices. In order to access the EEPROM, we must select 'EEPROM programming' mode, and then set the EEPROM chip select bit. Previously, we were setting both bits simultaneously, which doesn't work: they must be set in the right sequence. Always obtain the station address from the EEPROM, now that EEPROM reading works correctly. Make the TX interrupt moderation code based on the internal timer optional and turned off by default. Make the re_diag() routine conditional and off by default. When it is on, only use it for the original 8169, which was the only device that that really needed it. Modify interrupt handling to use a fast interrupt handler and fast taskqeueue. Correct the rgephy driver so that it only applies the DSP fixup for PHY revs 0 and 1. Later chips are fixed and don't need the fixup. Make the rgephy driver advertise both 1000_FD and 1000_HD bits in autoneg mode. A couple of the devices don't autoneg correctly unless configured this way.
2006-06-26 20:31:32 +00:00
* order to reliably negotiate a 1000Mbps link. This is only needed
* for rev 0 and rev 1 of the PHY. Later versions work without
* any fixups.
Clean up dead code.
2003-09-11 08:28:38 +00:00
*/
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
static void
rgephy_load_dspcode(struct mii_softc *sc)
{
Add support for RealTek RTL8211B(L) PHY. It's based on the patch made by Michael Eisele and the patch was slightly modified by me. With this change several NVIDIA ethernet controllers(e.g. MCP61) works. RTL8211B(L) is RealTek's new gigabit PHY. The PHY has several features including crossover correction, polarity correction as well as supporting triple speed(10/100/1000bps). Data transfer between MAC and PHY is via RGMII for 1000baseT, MII for 10baseT/100baseTX. Unfortunately, RealTek used the same model number for RTL8211B(L) PHY so there is no way to discriminate between RTL8211B(L) and its predecessors. ATM RTL8211B uses revision number 2 so checking the revision number seems to be only way to identify it. Obtained from: Michael Eisele [1] Tested by: clemens fischer < ino-qc AT spotteswoode DOT de DOT eu DOT org >
2007-10-29 02:17:07 +00:00
struct rgephy_softc *rsc;
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
int val;
Add support for the RealTek 8169SC/8110SC and RTL8101E devices. The latter is a PCIe 10/100 chip. Finally fix the EEPROM reading code so that we can access the EEPROMs on all devices. In order to access the EEPROM, we must select 'EEPROM programming' mode, and then set the EEPROM chip select bit. Previously, we were setting both bits simultaneously, which doesn't work: they must be set in the right sequence. Always obtain the station address from the EEPROM, now that EEPROM reading works correctly. Make the TX interrupt moderation code based on the internal timer optional and turned off by default. Make the re_diag() routine conditional and off by default. When it is on, only use it for the original 8169, which was the only device that that really needed it. Modify interrupt handling to use a fast interrupt handler and fast taskqeueue. Correct the rgephy driver so that it only applies the DSP fixup for PHY revs 0 and 1. Later chips are fixed and don't need the fixup. Make the rgephy driver advertise both 1000_FD and 1000_HD bits in autoneg mode. A couple of the devices don't autoneg correctly unless configured this way.
2006-06-26 20:31:32 +00:00
Add support for RealTek RTL8211B(L) PHY. It's based on the patch made by Michael Eisele and the patch was slightly modified by me. With this change several NVIDIA ethernet controllers(e.g. MCP61) works. RTL8211B(L) is RealTek's new gigabit PHY. The PHY has several features including crossover correction, polarity correction as well as supporting triple speed(10/100/1000bps). Data transfer between MAC and PHY is via RGMII for 1000baseT, MII for 10baseT/100baseTX. Unfortunately, RealTek used the same model number for RTL8211B(L) PHY so there is no way to discriminate between RTL8211B(L) and its predecessors. ATM RTL8211B uses revision number 2 so checking the revision number seems to be only way to identify it. Obtained from: Michael Eisele [1] Tested by: clemens fischer < ino-qc AT spotteswoode DOT de DOT eu DOT org >
2007-10-29 02:17:07 +00:00
rsc = (struct rgephy_softc *)sc;
if (rsc->mii_revision >= 2)
Add support for the RealTek 8169SC/8110SC and RTL8101E devices. The latter is a PCIe 10/100 chip. Finally fix the EEPROM reading code so that we can access the EEPROMs on all devices. In order to access the EEPROM, we must select 'EEPROM programming' mode, and then set the EEPROM chip select bit. Previously, we were setting both bits simultaneously, which doesn't work: they must be set in the right sequence. Always obtain the station address from the EEPROM, now that EEPROM reading works correctly. Make the TX interrupt moderation code based on the internal timer optional and turned off by default. Make the re_diag() routine conditional and off by default. When it is on, only use it for the original 8169, which was the only device that that really needed it. Modify interrupt handling to use a fast interrupt handler and fast taskqeueue. Correct the rgephy driver so that it only applies the DSP fixup for PHY revs 0 and 1. Later chips are fixed and don't need the fixup. Make the rgephy driver advertise both 1000_FD and 1000_HD bits in autoneg mode. A couple of the devices don't autoneg correctly unless configured this way.
2006-06-26 20:31:32 +00:00
return;
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
PHY_WRITE(sc, 31, 0x0001);
PHY_WRITE(sc, 21, 0x1000);
PHY_WRITE(sc, 24, 0x65C7);
PHY_CLRBIT(sc, 4, 0x0800);
val = PHY_READ(sc, 4) & 0xFFF;
PHY_WRITE(sc, 4, val);
PHY_WRITE(sc, 3, 0x00A1);
PHY_WRITE(sc, 2, 0x0008);
PHY_WRITE(sc, 1, 0x1020);
PHY_WRITE(sc, 0, 0x1000);
PHY_SETBIT(sc, 4, 0x0800);
PHY_CLRBIT(sc, 4, 0x0800);
val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
PHY_WRITE(sc, 4, val);
PHY_WRITE(sc, 3, 0xFF41);
PHY_WRITE(sc, 2, 0xDE60);
PHY_WRITE(sc, 1, 0x0140);
PHY_WRITE(sc, 0, 0x0077);
val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
PHY_WRITE(sc, 4, val);
PHY_WRITE(sc, 3, 0xDF01);
PHY_WRITE(sc, 2, 0xDF20);
PHY_WRITE(sc, 1, 0xFF95);
PHY_WRITE(sc, 0, 0xFA00);
val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
PHY_WRITE(sc, 4, val);
PHY_WRITE(sc, 3, 0xFF41);
PHY_WRITE(sc, 2, 0xDE20);
PHY_WRITE(sc, 1, 0x0140);
PHY_WRITE(sc, 0, 0x00BB);
val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
PHY_WRITE(sc, 4, val);
PHY_WRITE(sc, 3, 0xDF01);
PHY_WRITE(sc, 2, 0xDF20);
PHY_WRITE(sc, 1, 0xFF95);
PHY_WRITE(sc, 0, 0xBF00);
PHY_SETBIT(sc, 4, 0x0800);
PHY_CLRBIT(sc, 4, 0x0800);
PHY_WRITE(sc, 31, 0x0000);
Some style changes to a couple of PHY drivers: - Fix some whitespace nits. - Fix some spelling in comments. - Use MII_ANEGTICKS instead of 5. - Don't define variables in nested scope. - Remove superfluous returns at the end of void functions. - Remove unused static global rgephy_mii_model. - Remove dupe $Id$ in tdkphy(4). - Sort brgphys table. MFC after: 2 weeks
2006-12-02 19:36:25 +00:00
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
DELAY(40);
}
static void
rgephy_reset(struct mii_softc *sc)
{
Add RTL8211C(L) support. Disable advanced link-down power saving in phy reset. Reported by: nork Tested by: nork
2008-07-02 08:10:18 +00:00
struct rgephy_softc *rsc;
uint16_t ssr;
rsc = (struct rgephy_softc *)sc;
if (rsc->mii_revision == 3) {
/* RTL8211C(L) */
ssr = PHY_READ(sc, RGEPHY_MII_SSR);
if ((ssr & RGEPHY_SSR_ALDPS) != 0) {
ssr &= ~RGEPHY_SSR_ALDPS;
PHY_WRITE(sc, RGEPHY_MII_SSR, ssr);
}
}
Some style changes to a couple of PHY drivers: - Fix some whitespace nits. - Fix some spelling in comments. - Use MII_ANEGTICKS instead of 5. - Don't define variables in nested scope. - Remove superfluous returns at the end of void functions. - Remove unused static global rgephy_mii_model. - Remove dupe $Id$ in tdkphy(4). - Sort brgphys table. MFC after: 2 weeks
2006-12-02 19:36:25 +00:00
Add a PHY driver to support the built-in gigE PHY in the 8169S/8110S ethernet chips. This driver is pretty simple, however it contains special DSP initialization code which is needed in order to get the chip to negotiate a gigE link. (This special initialization may not be needed in subsequent chip revs.) Also: - Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS) - Deal with shared interrupts in re_intr(): if interface isn't up, return. - Fix another bug in re_gmii_writereg() (properly apply data field mask) - Allow PHY driver to read the RL_GMEDIASTAT register via the re_gmii_readreg() register (this is register needed to determine real time link/media status).
2003-09-11 03:53:46 +00:00
mii_phy_reset(sc);
DELAY(1000);
rgephy_load_dspcode(sc);
}
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