2005-01-06 01:43:34 +00:00
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/*-
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2000-09-16 20:02:28 +00:00
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* Product specific probe and attach routines for:
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* 27/284X and aic7770 motherboard SCSI controllers
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*
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2017-11-27 14:52:40 +00:00
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* SPDX-License-Identifier: BSD-3-Clause
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*
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2001-01-27 20:54:24 +00:00
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* Copyright (c) 1994-1998, 2000, 2001 Justin T. Gibbs.
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2000-09-16 20:02:28 +00:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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2002-04-24 16:58:51 +00:00
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* substantially similar to the "NO WARRANTY" disclaimer below
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* ("Disclaimer") and any redistribution must be conditioned upon
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* including a substantially similar Disclaimer requirement for further
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* binary redistribution.
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* 3. Neither the names of the above-listed copyright holders nor the names
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* of any contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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2000-09-16 20:02:28 +00:00
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*
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2001-01-27 20:54:24 +00:00
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* Alternatively, this software may be distributed under the terms of the
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2002-04-24 16:58:51 +00:00
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* GNU General Public License ("GPL") version 2 as published by the Free
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* Software Foundation.
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2001-01-27 20:54:24 +00:00
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*
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2002-04-24 16:58:51 +00:00
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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2000-09-16 20:02:28 +00:00
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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2002-04-24 16:58:51 +00:00
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGES.
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2000-09-16 20:02:28 +00:00
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*
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ahc_eisa.c:
ahc_pci.c:
ahd_pci.c:
aic7xxx.c:
aic79xx.c:
aic_osm_lib.c:
aic_osm_lib.h:
Use common OSM routines from aic_osm_lib for bus dma operations,
delay routines, accessing CCBs, byte swapping, etc.
aic7xxx_pci.c:
Provide a better description for the 2915/30LP on attach.
aic7xxx.c:
aic79xx.c:
aic7770.c:
aic79xx_pci.c:
aic7xxx_pci.c:
aic7xxx_93cx6.c:
Move FBSDID behind an ifdef so that these core files will
still compile under other OSes.
aic79xx.h:
aic79xx_pci.c:
aic79xx.seq:
To speed up non-packetized CDB delivery in Rev B, all CDB
acks are "released" to the output sync as soon as the
command phase starts. There is only one problem with this
approach. If the target changes phase before all data are
sent, we have left over acks that can go out on the bus in
a data phase. Due to other chip contraints, this only
happens if the target goes to data-in, but if the acks go
out before we can test SDONE, we'll think that the transfer
has completed successfully. Work around this by taking
advantage of the 400ns or 800ns dead time between command
phase and the REQ of the new phase. If the transfer has
completed successfully, SCSIEN should fall *long* before we
see a phase change. We thus treat any phasemiss that
occurs before SCSIEN falls as an incomplete transfer.
aic79xx.h:
Add the AHD_FAST_CDB_DELIVERY feature.
aic79xx_pci.c:
Set AHD_FAST_CDB_DELIVERY for all Rev. B parts.
aic79xx.seq:
Test for PHASEMIS in the command phase for
all AHD_FAST_CDB_DELIVERY controlelrs.
ahd_pci.c:
ahc_pci.c:
aic7xxx.h:
aic79xx.h:
Move definition of controller BAR offsets to core header files.
aic7xxx.c:
aic79xx.c:
In the softc free routine, leave removal of a softc from the
global list of softcs to the OSM (the caller of this routine).
This allows us to avoid holding the softc list_lock during device
destruction where we may have to sleep waiting for our recovery
thread to halt.
ahc_pci.c:
Use ahc_pci_test_register access to validate I/O mapped in
addition to the tests already performed for memory mapped
access.
Remove unused ahc_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
ahd_pci.c:
Remove reduntant definition of controller BAR offsets. These
are also defined in aic79xx.h.
Remove unused ahd_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
aic7xxx.c:
aic79xx.c:
aic79xx.h:
aic7xxx.h:
aic7xxx_osm.c:
aic79xx_osm.c:
Move timeout handling to the driver cores. In the case
of the aic79xx driver, the algorithm has been enhanced
to try target resets before performing a bus reset. For
the aic7xxx driver, the algorithm is unchanged. Although
the drivers do not currently sleep during recovery (recovery
is timeout driven), the cores do expect all processing to
be performed via a recovery thread. Our timeout handlers
are now little stubs that wakeup the recovery thread.
aic79xx.c:
aic79xx.h:
aic79xx_inline.h:
Change shared_data allocation to use a map_node so
that the sentinel hscb can use this map node in
ahd_swap_with_next_hscb. This routine now swaps
the hscb_map pointer in additon to the hscb
contents so that any sync operations occur on
the correct map.
physaddr -> busaddr
Pointed out by: Jason Thorpe <thorpej@wasabisystems.com>
aic79xx.c:
Make more use of the in/out/w/l/q macros for accessing
byte registers in the chip.
Correct some issues in the ahd_flush_qoutfifo() routine.
o Run the qoutfifo only once the command channel
DMA engine has been halted. This closes a window
where we might have missed some entries.
o Change ahd_run_data_fifo() to not loop to completion.
If we happen to start on the wrong FIFO and the other
FIFO has a snapshot savepointers, we might deadlock.
This required our delay between FIFO tests to be
moved to the ahd_flush_qoutfifo() routine.
o Update/add comments.
o Remove spurious test for COMPLETE_DMA list being empty
when completing transactions from the GSFIFO with
residuals. The SCB must be put on the COMPLETE_DMA
scb list unconditionally.
o When halting command channel DMA activity, we must
disable the DMA channel in all cases but an update
of the QOUTFIFO. The latter case is required so
that the sequencer will update its position in the
QOUTFIFO. Previously, we left the channel enabled
for all "push" DMAs. This left us vulnerable to
the sequencer handling an SCB push long after that
SCB was already processed manually by this routine.
o Correct the polarity of tests involving
ahd_scb_active_in_fifo(). This routine returns
non-zero for true.
Return to processing bad status completions through
the qoutfifo. This reduces the time that the sequencer
is kept paused when handling transactions with bad
status or underruns.
When waiting for the controller to quiece selections,
add a delay to our loop. Otherwise we may fail to wait
long enough for the sequencer to comply.
On H2A4 hardware, use the slow slewrate for non-paced
transfers. This mirrors what the Adaptec Windows
drivers do.
On the Rev B. only slow down the CRC timing for
older U160 devices that might need the slower timing.
We define "older" as devices that do not support
packetized protocol.
Wait up to 5000 * 5us for the SEEPROM to become unbusy.
Write ops seem to take much longer than read ops.
aic79xx.seq:
For controllers with the FAINT_LED bug, turn the diagnostic
led feature on during selection and reselection. This covers
the non-packetized case. The LED will be disabled for
non-packetized transfers once we return to the top level idle
loop. Add more comments about the busy LED workaround.
Extend a critical section around the entire
command channel idle loop process. Previously
the portion of this handler that directly manipulated
the linked list of completed SCBs was not protected.
This is the likely cause of the recent reports of
commands being completed twice by the driver.
Extend critical sections across the test for,
and the longjump to, longjump routines. This
prevents the firmware from trying to jump to
a longjmp handler that was just cleared by the
host.
Improve the locations of several critical section
begin and end points. Typically these changes
remove instructions that did not need to be
inside a critical section.
Close the "busfree after selection, but before busfree
interrupts can be enabled" race to just a single sequencer
instruction. We now test the BSY line explicitly before
clearing the busfree status and enabling the busfree
interrupt.
Close a race condition in the processing of HS_MAILBOX
updates. We now clear the "updated" status before the
copy. This ensures that we don't accidentally clear
the status incorrectly when the host sneaks in an update
just after our last copy, but before we clear the status.
This race has never been observed.
Don't re-enable SCSIEN if we lose the race to disable SCSIEN
in our interrupt handler's workaround for the RevA data-valid
too early issue.
aic79xx_inline.h:
Add comments indicating that the order in which bytes are
read or written in ahd_inw and ahd_outw is important. This
allows us to use these inlines when accessing registers with
side-effects.
aic79xx_pci.c:
The 29320 and the 29320B are 7902 not 7901 based products.
Correct the driver banner.
aic7xxx.h:
Enable the use of the auto-access pause feature
on the aic7870 and aic7880. It was disabled due
to an oversight.
aic7xxx.reg:
Move TARG_IMMEDIATE_SCB to alias LAST_MSG to
avoid leaving garbage in MWI_RESIDUAL. This
prevents spurious overflows whn operating target
mode on controllers that require the MWI_RESIDUAL
work-around.
aic7xxx.seq:
AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag.
Reference the correct softc field when testing
for its presence.
Set the NOT_IDENTIFIED and NO_CDB_SENT bits
in SEQ_FLAGS to indicate that the nexus is
invalid in await busfree.
aic7xxx_93cx6.c:
Add support for the C56/C66 versions of the EWEN and EWDS
commands.
aic7xxx.c:
aic7xxx_pci.c:
Move test for the validity of left over BIOS data
to ahc_test_register_access(). This guarantees that
any left over CHIPRST value is not clobbered by our
register access test and lost to the test that was
in ahc_reset.
2003-12-17 00:02:10 +00:00
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* $Id: //depot/aic7xxx/aic7xxx/aic7770.c#34 $
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2000-09-16 20:02:28 +00:00
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*/
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2002-04-24 16:58:51 +00:00
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#ifdef __linux__
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#include "aic7xxx_osm.h"
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#include "aic7xxx_inline.h"
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#include "aic7xxx_93cx6.h"
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#else
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ahc_eisa.c:
ahc_pci.c:
ahd_pci.c:
aic7xxx.c:
aic79xx.c:
aic_osm_lib.c:
aic_osm_lib.h:
Use common OSM routines from aic_osm_lib for bus dma operations,
delay routines, accessing CCBs, byte swapping, etc.
aic7xxx_pci.c:
Provide a better description for the 2915/30LP on attach.
aic7xxx.c:
aic79xx.c:
aic7770.c:
aic79xx_pci.c:
aic7xxx_pci.c:
aic7xxx_93cx6.c:
Move FBSDID behind an ifdef so that these core files will
still compile under other OSes.
aic79xx.h:
aic79xx_pci.c:
aic79xx.seq:
To speed up non-packetized CDB delivery in Rev B, all CDB
acks are "released" to the output sync as soon as the
command phase starts. There is only one problem with this
approach. If the target changes phase before all data are
sent, we have left over acks that can go out on the bus in
a data phase. Due to other chip contraints, this only
happens if the target goes to data-in, but if the acks go
out before we can test SDONE, we'll think that the transfer
has completed successfully. Work around this by taking
advantage of the 400ns or 800ns dead time between command
phase and the REQ of the new phase. If the transfer has
completed successfully, SCSIEN should fall *long* before we
see a phase change. We thus treat any phasemiss that
occurs before SCSIEN falls as an incomplete transfer.
aic79xx.h:
Add the AHD_FAST_CDB_DELIVERY feature.
aic79xx_pci.c:
Set AHD_FAST_CDB_DELIVERY for all Rev. B parts.
aic79xx.seq:
Test for PHASEMIS in the command phase for
all AHD_FAST_CDB_DELIVERY controlelrs.
ahd_pci.c:
ahc_pci.c:
aic7xxx.h:
aic79xx.h:
Move definition of controller BAR offsets to core header files.
aic7xxx.c:
aic79xx.c:
In the softc free routine, leave removal of a softc from the
global list of softcs to the OSM (the caller of this routine).
This allows us to avoid holding the softc list_lock during device
destruction where we may have to sleep waiting for our recovery
thread to halt.
ahc_pci.c:
Use ahc_pci_test_register access to validate I/O mapped in
addition to the tests already performed for memory mapped
access.
Remove unused ahc_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
ahd_pci.c:
Remove reduntant definition of controller BAR offsets. These
are also defined in aic79xx.h.
Remove unused ahd_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
aic7xxx.c:
aic79xx.c:
aic79xx.h:
aic7xxx.h:
aic7xxx_osm.c:
aic79xx_osm.c:
Move timeout handling to the driver cores. In the case
of the aic79xx driver, the algorithm has been enhanced
to try target resets before performing a bus reset. For
the aic7xxx driver, the algorithm is unchanged. Although
the drivers do not currently sleep during recovery (recovery
is timeout driven), the cores do expect all processing to
be performed via a recovery thread. Our timeout handlers
are now little stubs that wakeup the recovery thread.
aic79xx.c:
aic79xx.h:
aic79xx_inline.h:
Change shared_data allocation to use a map_node so
that the sentinel hscb can use this map node in
ahd_swap_with_next_hscb. This routine now swaps
the hscb_map pointer in additon to the hscb
contents so that any sync operations occur on
the correct map.
physaddr -> busaddr
Pointed out by: Jason Thorpe <thorpej@wasabisystems.com>
aic79xx.c:
Make more use of the in/out/w/l/q macros for accessing
byte registers in the chip.
Correct some issues in the ahd_flush_qoutfifo() routine.
o Run the qoutfifo only once the command channel
DMA engine has been halted. This closes a window
where we might have missed some entries.
o Change ahd_run_data_fifo() to not loop to completion.
If we happen to start on the wrong FIFO and the other
FIFO has a snapshot savepointers, we might deadlock.
This required our delay between FIFO tests to be
moved to the ahd_flush_qoutfifo() routine.
o Update/add comments.
o Remove spurious test for COMPLETE_DMA list being empty
when completing transactions from the GSFIFO with
residuals. The SCB must be put on the COMPLETE_DMA
scb list unconditionally.
o When halting command channel DMA activity, we must
disable the DMA channel in all cases but an update
of the QOUTFIFO. The latter case is required so
that the sequencer will update its position in the
QOUTFIFO. Previously, we left the channel enabled
for all "push" DMAs. This left us vulnerable to
the sequencer handling an SCB push long after that
SCB was already processed manually by this routine.
o Correct the polarity of tests involving
ahd_scb_active_in_fifo(). This routine returns
non-zero for true.
Return to processing bad status completions through
the qoutfifo. This reduces the time that the sequencer
is kept paused when handling transactions with bad
status or underruns.
When waiting for the controller to quiece selections,
add a delay to our loop. Otherwise we may fail to wait
long enough for the sequencer to comply.
On H2A4 hardware, use the slow slewrate for non-paced
transfers. This mirrors what the Adaptec Windows
drivers do.
On the Rev B. only slow down the CRC timing for
older U160 devices that might need the slower timing.
We define "older" as devices that do not support
packetized protocol.
Wait up to 5000 * 5us for the SEEPROM to become unbusy.
Write ops seem to take much longer than read ops.
aic79xx.seq:
For controllers with the FAINT_LED bug, turn the diagnostic
led feature on during selection and reselection. This covers
the non-packetized case. The LED will be disabled for
non-packetized transfers once we return to the top level idle
loop. Add more comments about the busy LED workaround.
Extend a critical section around the entire
command channel idle loop process. Previously
the portion of this handler that directly manipulated
the linked list of completed SCBs was not protected.
This is the likely cause of the recent reports of
commands being completed twice by the driver.
Extend critical sections across the test for,
and the longjump to, longjump routines. This
prevents the firmware from trying to jump to
a longjmp handler that was just cleared by the
host.
Improve the locations of several critical section
begin and end points. Typically these changes
remove instructions that did not need to be
inside a critical section.
Close the "busfree after selection, but before busfree
interrupts can be enabled" race to just a single sequencer
instruction. We now test the BSY line explicitly before
clearing the busfree status and enabling the busfree
interrupt.
Close a race condition in the processing of HS_MAILBOX
updates. We now clear the "updated" status before the
copy. This ensures that we don't accidentally clear
the status incorrectly when the host sneaks in an update
just after our last copy, but before we clear the status.
This race has never been observed.
Don't re-enable SCSIEN if we lose the race to disable SCSIEN
in our interrupt handler's workaround for the RevA data-valid
too early issue.
aic79xx_inline.h:
Add comments indicating that the order in which bytes are
read or written in ahd_inw and ahd_outw is important. This
allows us to use these inlines when accessing registers with
side-effects.
aic79xx_pci.c:
The 29320 and the 29320B are 7902 not 7901 based products.
Correct the driver banner.
aic7xxx.h:
Enable the use of the auto-access pause feature
on the aic7870 and aic7880. It was disabled due
to an oversight.
aic7xxx.reg:
Move TARG_IMMEDIATE_SCB to alias LAST_MSG to
avoid leaving garbage in MWI_RESIDUAL. This
prevents spurious overflows whn operating target
mode on controllers that require the MWI_RESIDUAL
work-around.
aic7xxx.seq:
AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag.
Reference the correct softc field when testing
for its presence.
Set the NOT_IDENTIFIED and NO_CDB_SENT bits
in SEQ_FLAGS to indicate that the nexus is
invalid in await busfree.
aic7xxx_93cx6.c:
Add support for the C56/C66 versions of the EWEN and EWDS
commands.
aic7xxx.c:
aic7xxx_pci.c:
Move test for the validity of left over BIOS data
to ahc_test_register_access(). This guarantees that
any left over CHIPRST value is not clobbered by our
register access test and lost to the test that was
in ahc_reset.
2003-12-17 00:02:10 +00:00
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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2002-04-24 16:58:51 +00:00
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#include <dev/aic7xxx/aic7xxx_osm.h>
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2000-09-16 20:02:28 +00:00
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#include <dev/aic7xxx/aic7xxx_inline.h>
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#include <dev/aic7xxx/aic7xxx_93cx6.h>
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2002-04-24 16:58:51 +00:00
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#endif
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2000-09-16 20:02:28 +00:00
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#define ID_AIC7770 0x04907770
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#define ID_AHA_274x 0x04907771
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#define ID_AHA_284xB 0x04907756 /* BIOS enabled */
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#define ID_AHA_284x 0x04907757 /* BIOS disabled*/
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2002-11-30 18:00:43 +00:00
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#define ID_OLV_274x 0x04907782 /* Olivetti OEM */
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#define ID_OLV_274xD 0x04907783 /* Olivetti OEM (Differential) */
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2000-09-16 20:02:28 +00:00
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2003-05-03 23:55:38 +00:00
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static int aic7770_chip_init(struct ahc_softc *ahc);
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static int aic7770_suspend(struct ahc_softc *ahc);
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static int aic7770_resume(struct ahc_softc *ahc);
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2002-08-31 06:40:32 +00:00
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static int aha2840_load_seeprom(struct ahc_softc *ahc);
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2000-09-16 20:02:28 +00:00
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static ahc_device_setup_t ahc_aic7770_VL_setup;
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2017-02-16 21:57:19 +00:00
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static ahc_device_setup_t ahc_aic7770_EISA_setup; /* Really just ISA */
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2000-09-16 20:02:28 +00:00
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static ahc_device_setup_t ahc_aic7770_setup;
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2003-06-06 23:40:48 +00:00
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struct aic7770_identity aic7770_ident_table[] =
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2000-09-16 20:02:28 +00:00
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{
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{
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ID_AHA_274x,
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0xFFFFFFFF,
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"Adaptec 274X SCSI adapter",
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ahc_aic7770_EISA_setup
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},
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{
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ID_AHA_284xB,
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0xFFFFFFFE,
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"Adaptec 284X SCSI adapter",
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ahc_aic7770_VL_setup
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},
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2003-06-06 23:40:48 +00:00
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{
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ID_AHA_284x,
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0xFFFFFFFE,
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"Adaptec 284X SCSI adapter (BIOS Disabled)",
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ahc_aic7770_VL_setup
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},
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2002-11-30 18:00:43 +00:00
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{
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ID_OLV_274x,
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0xFFFFFFFF,
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"Adaptec (Olivetti OEM) 274X SCSI adapter",
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ahc_aic7770_EISA_setup
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},
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{
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ID_OLV_274xD,
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0xFFFFFFFF,
|
|
|
|
|
"Adaptec (Olivetti OEM) 274X Differential SCSI adapter",
|
|
|
|
|
ahc_aic7770_EISA_setup
|
|
|
|
|
},
|
2000-09-16 20:02:28 +00:00
|
|
|
/* Generic chip probes for devices we don't know 'exactly' */
|
|
|
|
|
{
|
|
|
|
|
ID_AIC7770,
|
|
|
|
|
0xFFFFFFFF,
|
|
|
|
|
"Adaptec aic7770 SCSI adapter",
|
|
|
|
|
ahc_aic7770_EISA_setup
|
|
|
|
|
}
|
|
|
|
|
};
|
|
|
|
|
const int ahc_num_aic7770_devs = NUM_ELEMENTS(aic7770_ident_table);
|
|
|
|
|
|
|
|
|
|
struct aic7770_identity *
|
|
|
|
|
aic7770_find_device(uint32_t id)
|
|
|
|
|
{
|
|
|
|
|
struct aic7770_identity *entry;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < ahc_num_aic7770_devs; i++) {
|
|
|
|
|
entry = &aic7770_ident_table[i];
|
|
|
|
|
if (entry->full_id == (id & entry->id_mask))
|
|
|
|
|
return (entry);
|
|
|
|
|
}
|
|
|
|
|
return (NULL);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int
|
2002-04-24 16:58:51 +00:00
|
|
|
aic7770_config(struct ahc_softc *ahc, struct aic7770_identity *entry, u_int io)
|
2000-09-16 20:02:28 +00:00
|
|
|
{
|
|
|
|
|
int error;
|
2002-08-31 06:40:32 +00:00
|
|
|
int have_seeprom;
|
2000-09-16 20:02:28 +00:00
|
|
|
u_int hostconf;
|
This is an MFC candidate.
ahc_eisa.c:
Change aic7770_map_int to take an additional irq parameter.
Although we can get the irq from the eisa dev under FreeBSD,
we can't do this under linux, so the OSM interface must supply
this.
ahc_pci.c:
Move ahc_power_state_change() to the OSM. This allows us to
use a platform supplied function that does the same thing.
-current will move to the FreeBSD native API in the near
future.
aic7770.c:
Sync up with core changes to support Linux EISA.
We now store a 2 bit primary channel number rather
than a bit flag that only allows b to be the primary
channel. Adjust for this change.
aic7xxx.c:
Namespace and staticization cleanup. All exported symbols
use an "ahc_" prefix to avoid collisions with other modules.
Correct a logic bug that prevented us from dropping
ATN during some exceptional conditions during message
processing.
Take advantage of a new flag managed by the sequencer
that indicates if an SCB fetch is in progress. If so,
the currently selected SCB needs to be returned to the
free list to prevent an SCB leak. This leak is a rarity
and would only occur if a bus reset or timeout resulting
in a bus reset occurred in the middle of an SCB fetch.
Don't attempt to perform ULTRA transfers on ultra capable
adapters missing the external precision resistor required
for ultra speeds. I've never encountered an adapter
configured this way, but better safe than sorry.
Handle the case of 5MHz user sync rate set as "0" instead of 0x1c
in scratch ram.
If we lookup a period of 0 in our table (async), clear the scsi offset.
aic7xxx.h:
Adjust for the primary channel being represented as
a 2 bit integer in the flags member of the ahc softc.
Cleanup the flags definitions so that comment blocks are
not cramped.
Update seeprom definitions to correctly reflect the fact
that the primary channel is represented as a 2 bit integer.
Add AHC_ULTRA_DIASABLED softc flag to denote controllers
missing the external precision resistor.
aic7xxx.reg:
Add DFCACHETH to the definition of DFSTATUS for completness sake.
Add SEQ_FLAGS2 which currently only contains the SCB_DMA
(SCB DMA in progress) flag.
aic7xxx.seq:
Correct a problem when one lun has a disconnected untagged
transaction and another lun has disconnected tagged transactions.
Just because an entry is found in the untagged table doesn't
mean that it will match. If the match on the lun fails, cleanup
the SCB (return it to the disconnected list or free it), and snoop
for a tag message. Before this change, we reported an unsolicited
reselection. This bug was introduced about a month ago during an
overly aggressive optimization pass on the reselection code.
When cleaning up an SCB, we can't just blindly free the SCB. In
the paging case, if the SCB came off of the disconnected list, its
state may never have been updated in host memory. So, check the
disconnected bit in SCB_CONTROL and return the SCB to the disconnected
list if appropriate.
Manage the SCB_DMA flag of SEQ_FLAGS2.
More carefully shutdown the S/G dma engine in all cases by using
a subroutine. Supposedly not doing this can cause an arbiter hang
on some ULTRA2 chips.
Formatting cleanup.
On some chips, at least the aic7856, the transition from
MREQPEND to HDONE can take a full 4 clock cycles. Test
HDONE one more time to avoid this race. We only want our
FIFO hung recovery code to execute when the engine is
really hung.
aic7xxx_93cx6.c:
Sync perforce ids.
aic7xxx_freebsd.c:
Adjust for the primary channel being a 2 bit integer
rather than a flag for 'B' channel being the primary.
Namespace cleanup.
Unpause the sequencer in one error recovery path that
neglected to do so. This could have caused us to perform
a bus reset when a recovery message might have otherwise been
successful.
aic7xxx_freebsd.h:
Use AHC_PCI_CONFIG for controlling compilation of PCI
support consistently throughout the driver.
Move ahc_power_state_change() to OSM.
aic7xxx_inline.h
Namespace cleanup.
Adjust our interrupt handler so it will work in the edge
interrupt case. We must process all interrupt sources
when the interrupt fires or risk not ever getting an
interrupt again. This involves marking the fact
that we are relying on an edge interrupt in ahc->flags
and checking for this condition in addition to the
AHC_ALL_INTERRUPTS flag. This fixes hangs on the
284X and any other aic7770 installation where level
interrupts are not available.
aic7xxx_pci.c:
Move the powerstate manipulation code into the OSM. Several
OSes now provide this functionality natively.
Take another shot at using the data stored in scratch ram
if the SCB2 signature is correct and no SEEPROM data is
available. In the past this failed if external SCB ram
was configured because the memory port was locked. We
now release the memory port prior to testing the values
in SCB2 and re-acquire it prior to doing termination control.
Adjust for new 2 bit primary channel setting.
Trust the STPWLEVEL setting on v 3.X BIOSes too.
Configure any 785X ID in the same fashion and assume
that any device with a rev id of 1 or higher has the
PCI 2.1 retry bug.
2001-03-11 06:34:17 +00:00
|
|
|
u_int irq;
|
|
|
|
|
u_int intdef;
|
2000-09-16 20:02:28 +00:00
|
|
|
|
2001-07-18 21:39:48 +00:00
|
|
|
error = entry->setup(ahc);
|
2002-08-31 06:40:32 +00:00
|
|
|
have_seeprom = 0;
|
2000-09-16 20:02:28 +00:00
|
|
|
if (error != 0)
|
|
|
|
|
return (error);
|
|
|
|
|
|
2002-04-24 16:58:51 +00:00
|
|
|
error = aic7770_map_registers(ahc, io);
|
2000-09-16 20:02:28 +00:00
|
|
|
if (error != 0)
|
|
|
|
|
return (error);
|
|
|
|
|
|
2002-04-24 16:58:51 +00:00
|
|
|
/*
|
|
|
|
|
* Before we continue probing the card, ensure that
|
|
|
|
|
* its interrupts are *disabled*. We don't want
|
|
|
|
|
* a misstep to hang the machine in an interrupt
|
|
|
|
|
* storm.
|
|
|
|
|
*/
|
|
|
|
|
ahc_intr_enable(ahc, FALSE);
|
|
|
|
|
|
2001-07-18 21:39:48 +00:00
|
|
|
ahc->description = entry->name;
|
|
|
|
|
error = ahc_softc_init(ahc);
|
2003-05-03 23:55:38 +00:00
|
|
|
if (error != 0)
|
|
|
|
|
return (error);
|
|
|
|
|
|
|
|
|
|
ahc->bus_chip_init = aic7770_chip_init;
|
|
|
|
|
ahc->bus_suspend = aic7770_suspend;
|
|
|
|
|
ahc->bus_resume = aic7770_resume;
|
2000-09-16 20:02:28 +00:00
|
|
|
|
2003-06-06 23:48:19 +00:00
|
|
|
error = ahc_reset(ahc, /*reinit*/FALSE);
|
2000-09-16 20:02:28 +00:00
|
|
|
if (error != 0)
|
|
|
|
|
return (error);
|
|
|
|
|
|
This is an MFC candidate.
ahc_eisa.c:
Change aic7770_map_int to take an additional irq parameter.
Although we can get the irq from the eisa dev under FreeBSD,
we can't do this under linux, so the OSM interface must supply
this.
ahc_pci.c:
Move ahc_power_state_change() to the OSM. This allows us to
use a platform supplied function that does the same thing.
-current will move to the FreeBSD native API in the near
future.
aic7770.c:
Sync up with core changes to support Linux EISA.
We now store a 2 bit primary channel number rather
than a bit flag that only allows b to be the primary
channel. Adjust for this change.
aic7xxx.c:
Namespace and staticization cleanup. All exported symbols
use an "ahc_" prefix to avoid collisions with other modules.
Correct a logic bug that prevented us from dropping
ATN during some exceptional conditions during message
processing.
Take advantage of a new flag managed by the sequencer
that indicates if an SCB fetch is in progress. If so,
the currently selected SCB needs to be returned to the
free list to prevent an SCB leak. This leak is a rarity
and would only occur if a bus reset or timeout resulting
in a bus reset occurred in the middle of an SCB fetch.
Don't attempt to perform ULTRA transfers on ultra capable
adapters missing the external precision resistor required
for ultra speeds. I've never encountered an adapter
configured this way, but better safe than sorry.
Handle the case of 5MHz user sync rate set as "0" instead of 0x1c
in scratch ram.
If we lookup a period of 0 in our table (async), clear the scsi offset.
aic7xxx.h:
Adjust for the primary channel being represented as
a 2 bit integer in the flags member of the ahc softc.
Cleanup the flags definitions so that comment blocks are
not cramped.
Update seeprom definitions to correctly reflect the fact
that the primary channel is represented as a 2 bit integer.
Add AHC_ULTRA_DIASABLED softc flag to denote controllers
missing the external precision resistor.
aic7xxx.reg:
Add DFCACHETH to the definition of DFSTATUS for completness sake.
Add SEQ_FLAGS2 which currently only contains the SCB_DMA
(SCB DMA in progress) flag.
aic7xxx.seq:
Correct a problem when one lun has a disconnected untagged
transaction and another lun has disconnected tagged transactions.
Just because an entry is found in the untagged table doesn't
mean that it will match. If the match on the lun fails, cleanup
the SCB (return it to the disconnected list or free it), and snoop
for a tag message. Before this change, we reported an unsolicited
reselection. This bug was introduced about a month ago during an
overly aggressive optimization pass on the reselection code.
When cleaning up an SCB, we can't just blindly free the SCB. In
the paging case, if the SCB came off of the disconnected list, its
state may never have been updated in host memory. So, check the
disconnected bit in SCB_CONTROL and return the SCB to the disconnected
list if appropriate.
Manage the SCB_DMA flag of SEQ_FLAGS2.
More carefully shutdown the S/G dma engine in all cases by using
a subroutine. Supposedly not doing this can cause an arbiter hang
on some ULTRA2 chips.
Formatting cleanup.
On some chips, at least the aic7856, the transition from
MREQPEND to HDONE can take a full 4 clock cycles. Test
HDONE one more time to avoid this race. We only want our
FIFO hung recovery code to execute when the engine is
really hung.
aic7xxx_93cx6.c:
Sync perforce ids.
aic7xxx_freebsd.c:
Adjust for the primary channel being a 2 bit integer
rather than a flag for 'B' channel being the primary.
Namespace cleanup.
Unpause the sequencer in one error recovery path that
neglected to do so. This could have caused us to perform
a bus reset when a recovery message might have otherwise been
successful.
aic7xxx_freebsd.h:
Use AHC_PCI_CONFIG for controlling compilation of PCI
support consistently throughout the driver.
Move ahc_power_state_change() to OSM.
aic7xxx_inline.h
Namespace cleanup.
Adjust our interrupt handler so it will work in the edge
interrupt case. We must process all interrupt sources
when the interrupt fires or risk not ever getting an
interrupt again. This involves marking the fact
that we are relying on an edge interrupt in ahc->flags
and checking for this condition in addition to the
AHC_ALL_INTERRUPTS flag. This fixes hangs on the
284X and any other aic7770 installation where level
interrupts are not available.
aic7xxx_pci.c:
Move the powerstate manipulation code into the OSM. Several
OSes now provide this functionality natively.
Take another shot at using the data stored in scratch ram
if the SCB2 signature is correct and no SEEPROM data is
available. In the past this failed if external SCB ram
was configured because the memory port was locked. We
now release the memory port prior to testing the values
in SCB2 and re-acquire it prior to doing termination control.
Adjust for new 2 bit primary channel setting.
Trust the STPWLEVEL setting on v 3.X BIOSes too.
Configure any 785X ID in the same fashion and assume
that any device with a rev id of 1 or higher has the
PCI 2.1 retry bug.
2001-03-11 06:34:17 +00:00
|
|
|
/* Make sure we have a valid interrupt vector */
|
|
|
|
|
intdef = ahc_inb(ahc, INTDEF);
|
|
|
|
|
irq = intdef & VECTOR;
|
|
|
|
|
switch (irq) {
|
|
|
|
|
case 9:
|
|
|
|
|
case 10:
|
|
|
|
|
case 11:
|
|
|
|
|
case 12:
|
|
|
|
|
case 14:
|
|
|
|
|
case 15:
|
|
|
|
|
break;
|
|
|
|
|
default:
|
ahc_eisa.c:
ahc_pci.c:
ahd_pci.c:
aic7xxx.c:
aic79xx.c:
aic_osm_lib.c:
aic_osm_lib.h:
Use common OSM routines from aic_osm_lib for bus dma operations,
delay routines, accessing CCBs, byte swapping, etc.
aic7xxx_pci.c:
Provide a better description for the 2915/30LP on attach.
aic7xxx.c:
aic79xx.c:
aic7770.c:
aic79xx_pci.c:
aic7xxx_pci.c:
aic7xxx_93cx6.c:
Move FBSDID behind an ifdef so that these core files will
still compile under other OSes.
aic79xx.h:
aic79xx_pci.c:
aic79xx.seq:
To speed up non-packetized CDB delivery in Rev B, all CDB
acks are "released" to the output sync as soon as the
command phase starts. There is only one problem with this
approach. If the target changes phase before all data are
sent, we have left over acks that can go out on the bus in
a data phase. Due to other chip contraints, this only
happens if the target goes to data-in, but if the acks go
out before we can test SDONE, we'll think that the transfer
has completed successfully. Work around this by taking
advantage of the 400ns or 800ns dead time between command
phase and the REQ of the new phase. If the transfer has
completed successfully, SCSIEN should fall *long* before we
see a phase change. We thus treat any phasemiss that
occurs before SCSIEN falls as an incomplete transfer.
aic79xx.h:
Add the AHD_FAST_CDB_DELIVERY feature.
aic79xx_pci.c:
Set AHD_FAST_CDB_DELIVERY for all Rev. B parts.
aic79xx.seq:
Test for PHASEMIS in the command phase for
all AHD_FAST_CDB_DELIVERY controlelrs.
ahd_pci.c:
ahc_pci.c:
aic7xxx.h:
aic79xx.h:
Move definition of controller BAR offsets to core header files.
aic7xxx.c:
aic79xx.c:
In the softc free routine, leave removal of a softc from the
global list of softcs to the OSM (the caller of this routine).
This allows us to avoid holding the softc list_lock during device
destruction where we may have to sleep waiting for our recovery
thread to halt.
ahc_pci.c:
Use ahc_pci_test_register access to validate I/O mapped in
addition to the tests already performed for memory mapped
access.
Remove unused ahc_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
ahd_pci.c:
Remove reduntant definition of controller BAR offsets. These
are also defined in aic79xx.h.
Remove unused ahd_power_state_change() function. The PCI
layer in both 4.X and 5.X now offer this functionality.
aic7xxx.c:
aic79xx.c:
aic79xx.h:
aic7xxx.h:
aic7xxx_osm.c:
aic79xx_osm.c:
Move timeout handling to the driver cores. In the case
of the aic79xx driver, the algorithm has been enhanced
to try target resets before performing a bus reset. For
the aic7xxx driver, the algorithm is unchanged. Although
the drivers do not currently sleep during recovery (recovery
is timeout driven), the cores do expect all processing to
be performed via a recovery thread. Our timeout handlers
are now little stubs that wakeup the recovery thread.
aic79xx.c:
aic79xx.h:
aic79xx_inline.h:
Change shared_data allocation to use a map_node so
that the sentinel hscb can use this map node in
ahd_swap_with_next_hscb. This routine now swaps
the hscb_map pointer in additon to the hscb
contents so that any sync operations occur on
the correct map.
physaddr -> busaddr
Pointed out by: Jason Thorpe <thorpej@wasabisystems.com>
aic79xx.c:
Make more use of the in/out/w/l/q macros for accessing
byte registers in the chip.
Correct some issues in the ahd_flush_qoutfifo() routine.
o Run the qoutfifo only once the command channel
DMA engine has been halted. This closes a window
where we might have missed some entries.
o Change ahd_run_data_fifo() to not loop to completion.
If we happen to start on the wrong FIFO and the other
FIFO has a snapshot savepointers, we might deadlock.
This required our delay between FIFO tests to be
moved to the ahd_flush_qoutfifo() routine.
o Update/add comments.
o Remove spurious test for COMPLETE_DMA list being empty
when completing transactions from the GSFIFO with
residuals. The SCB must be put on the COMPLETE_DMA
scb list unconditionally.
o When halting command channel DMA activity, we must
disable the DMA channel in all cases but an update
of the QOUTFIFO. The latter case is required so
that the sequencer will update its position in the
QOUTFIFO. Previously, we left the channel enabled
for all "push" DMAs. This left us vulnerable to
the sequencer handling an SCB push long after that
SCB was already processed manually by this routine.
o Correct the polarity of tests involving
ahd_scb_active_in_fifo(). This routine returns
non-zero for true.
Return to processing bad status completions through
the qoutfifo. This reduces the time that the sequencer
is kept paused when handling transactions with bad
status or underruns.
When waiting for the controller to quiece selections,
add a delay to our loop. Otherwise we may fail to wait
long enough for the sequencer to comply.
On H2A4 hardware, use the slow slewrate for non-paced
transfers. This mirrors what the Adaptec Windows
drivers do.
On the Rev B. only slow down the CRC timing for
older U160 devices that might need the slower timing.
We define "older" as devices that do not support
packetized protocol.
Wait up to 5000 * 5us for the SEEPROM to become unbusy.
Write ops seem to take much longer than read ops.
aic79xx.seq:
For controllers with the FAINT_LED bug, turn the diagnostic
led feature on during selection and reselection. This covers
the non-packetized case. The LED will be disabled for
non-packetized transfers once we return to the top level idle
loop. Add more comments about the busy LED workaround.
Extend a critical section around the entire
command channel idle loop process. Previously
the portion of this handler that directly manipulated
the linked list of completed SCBs was not protected.
This is the likely cause of the recent reports of
commands being completed twice by the driver.
Extend critical sections across the test for,
and the longjump to, longjump routines. This
prevents the firmware from trying to jump to
a longjmp handler that was just cleared by the
host.
Improve the locations of several critical section
begin and end points. Typically these changes
remove instructions that did not need to be
inside a critical section.
Close the "busfree after selection, but before busfree
interrupts can be enabled" race to just a single sequencer
instruction. We now test the BSY line explicitly before
clearing the busfree status and enabling the busfree
interrupt.
Close a race condition in the processing of HS_MAILBOX
updates. We now clear the "updated" status before the
copy. This ensures that we don't accidentally clear
the status incorrectly when the host sneaks in an update
just after our last copy, but before we clear the status.
This race has never been observed.
Don't re-enable SCSIEN if we lose the race to disable SCSIEN
in our interrupt handler's workaround for the RevA data-valid
too early issue.
aic79xx_inline.h:
Add comments indicating that the order in which bytes are
read or written in ahd_inw and ahd_outw is important. This
allows us to use these inlines when accessing registers with
side-effects.
aic79xx_pci.c:
The 29320 and the 29320B are 7902 not 7901 based products.
Correct the driver banner.
aic7xxx.h:
Enable the use of the auto-access pause feature
on the aic7870 and aic7880. It was disabled due
to an oversight.
aic7xxx.reg:
Move TARG_IMMEDIATE_SCB to alias LAST_MSG to
avoid leaving garbage in MWI_RESIDUAL. This
prevents spurious overflows whn operating target
mode on controllers that require the MWI_RESIDUAL
work-around.
aic7xxx.seq:
AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag.
Reference the correct softc field when testing
for its presence.
Set the NOT_IDENTIFIED and NO_CDB_SENT bits
in SEQ_FLAGS to indicate that the nexus is
invalid in await busfree.
aic7xxx_93cx6.c:
Add support for the C56/C66 versions of the EWEN and EWDS
commands.
aic7xxx.c:
aic7xxx_pci.c:
Move test for the validity of left over BIOS data
to ahc_test_register_access(). This guarantees that
any left over CHIPRST value is not clobbered by our
register access test and lost to the test that was
in ahc_reset.
2003-12-17 00:02:10 +00:00
|
|
|
printf("aic7770_config: invalid irq setting %d\n", intdef);
|
This is an MFC candidate.
ahc_eisa.c:
Change aic7770_map_int to take an additional irq parameter.
Although we can get the irq from the eisa dev under FreeBSD,
we can't do this under linux, so the OSM interface must supply
this.
ahc_pci.c:
Move ahc_power_state_change() to the OSM. This allows us to
use a platform supplied function that does the same thing.
-current will move to the FreeBSD native API in the near
future.
aic7770.c:
Sync up with core changes to support Linux EISA.
We now store a 2 bit primary channel number rather
than a bit flag that only allows b to be the primary
channel. Adjust for this change.
aic7xxx.c:
Namespace and staticization cleanup. All exported symbols
use an "ahc_" prefix to avoid collisions with other modules.
Correct a logic bug that prevented us from dropping
ATN during some exceptional conditions during message
processing.
Take advantage of a new flag managed by the sequencer
that indicates if an SCB fetch is in progress. If so,
the currently selected SCB needs to be returned to the
free list to prevent an SCB leak. This leak is a rarity
and would only occur if a bus reset or timeout resulting
in a bus reset occurred in the middle of an SCB fetch.
Don't attempt to perform ULTRA transfers on ultra capable
adapters missing the external precision resistor required
for ultra speeds. I've never encountered an adapter
configured this way, but better safe than sorry.
Handle the case of 5MHz user sync rate set as "0" instead of 0x1c
in scratch ram.
If we lookup a period of 0 in our table (async), clear the scsi offset.
aic7xxx.h:
Adjust for the primary channel being represented as
a 2 bit integer in the flags member of the ahc softc.
Cleanup the flags definitions so that comment blocks are
not cramped.
Update seeprom definitions to correctly reflect the fact
that the primary channel is represented as a 2 bit integer.
Add AHC_ULTRA_DIASABLED softc flag to denote controllers
missing the external precision resistor.
aic7xxx.reg:
Add DFCACHETH to the definition of DFSTATUS for completness sake.
Add SEQ_FLAGS2 which currently only contains the SCB_DMA
(SCB DMA in progress) flag.
aic7xxx.seq:
Correct a problem when one lun has a disconnected untagged
transaction and another lun has disconnected tagged transactions.
Just because an entry is found in the untagged table doesn't
mean that it will match. If the match on the lun fails, cleanup
the SCB (return it to the disconnected list or free it), and snoop
for a tag message. Before this change, we reported an unsolicited
reselection. This bug was introduced about a month ago during an
overly aggressive optimization pass on the reselection code.
When cleaning up an SCB, we can't just blindly free the SCB. In
the paging case, if the SCB came off of the disconnected list, its
state may never have been updated in host memory. So, check the
disconnected bit in SCB_CONTROL and return the SCB to the disconnected
list if appropriate.
Manage the SCB_DMA flag of SEQ_FLAGS2.
More carefully shutdown the S/G dma engine in all cases by using
a subroutine. Supposedly not doing this can cause an arbiter hang
on some ULTRA2 chips.
Formatting cleanup.
On some chips, at least the aic7856, the transition from
MREQPEND to HDONE can take a full 4 clock cycles. Test
HDONE one more time to avoid this race. We only want our
FIFO hung recovery code to execute when the engine is
really hung.
aic7xxx_93cx6.c:
Sync perforce ids.
aic7xxx_freebsd.c:
Adjust for the primary channel being a 2 bit integer
rather than a flag for 'B' channel being the primary.
Namespace cleanup.
Unpause the sequencer in one error recovery path that
neglected to do so. This could have caused us to perform
a bus reset when a recovery message might have otherwise been
successful.
aic7xxx_freebsd.h:
Use AHC_PCI_CONFIG for controlling compilation of PCI
support consistently throughout the driver.
Move ahc_power_state_change() to OSM.
aic7xxx_inline.h
Namespace cleanup.
Adjust our interrupt handler so it will work in the edge
interrupt case. We must process all interrupt sources
when the interrupt fires or risk not ever getting an
interrupt again. This involves marking the fact
that we are relying on an edge interrupt in ahc->flags
and checking for this condition in addition to the
AHC_ALL_INTERRUPTS flag. This fixes hangs on the
284X and any other aic7770 installation where level
interrupts are not available.
aic7xxx_pci.c:
Move the powerstate manipulation code into the OSM. Several
OSes now provide this functionality natively.
Take another shot at using the data stored in scratch ram
if the SCB2 signature is correct and no SEEPROM data is
available. In the past this failed if external SCB ram
was configured because the memory port was locked. We
now release the memory port prior to testing the values
in SCB2 and re-acquire it prior to doing termination control.
Adjust for new 2 bit primary channel setting.
Trust the STPWLEVEL setting on v 3.X BIOSes too.
Configure any 785X ID in the same fashion and assume
that any device with a rev id of 1 or higher has the
PCI 2.1 retry bug.
2001-03-11 06:34:17 +00:00
|
|
|
return (ENXIO);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if ((intdef & EDGE_TRIG) != 0)
|
|
|
|
|
ahc->flags |= AHC_EDGE_INTERRUPT;
|
|
|
|
|
|
2001-07-18 21:39:48 +00:00
|
|
|
switch (ahc->chip & (AHC_EISA|AHC_VL)) {
|
2000-09-16 20:02:28 +00:00
|
|
|
case AHC_EISA:
|
|
|
|
|
{
|
|
|
|
|
u_int biosctrl;
|
|
|
|
|
u_int scsiconf;
|
|
|
|
|
u_int scsiconf1;
|
|
|
|
|
|
|
|
|
|
biosctrl = ahc_inb(ahc, HA_274_BIOSCTRL);
|
|
|
|
|
scsiconf = ahc_inb(ahc, SCSICONF);
|
|
|
|
|
scsiconf1 = ahc_inb(ahc, SCSICONF + 1);
|
|
|
|
|
|
|
|
|
|
/* Get the primary channel information */
|
|
|
|
|
if ((biosctrl & CHANNEL_B_PRIMARY) != 0)
|
This is an MFC candidate.
ahc_eisa.c:
Change aic7770_map_int to take an additional irq parameter.
Although we can get the irq from the eisa dev under FreeBSD,
we can't do this under linux, so the OSM interface must supply
this.
ahc_pci.c:
Move ahc_power_state_change() to the OSM. This allows us to
use a platform supplied function that does the same thing.
-current will move to the FreeBSD native API in the near
future.
aic7770.c:
Sync up with core changes to support Linux EISA.
We now store a 2 bit primary channel number rather
than a bit flag that only allows b to be the primary
channel. Adjust for this change.
aic7xxx.c:
Namespace and staticization cleanup. All exported symbols
use an "ahc_" prefix to avoid collisions with other modules.
Correct a logic bug that prevented us from dropping
ATN during some exceptional conditions during message
processing.
Take advantage of a new flag managed by the sequencer
that indicates if an SCB fetch is in progress. If so,
the currently selected SCB needs to be returned to the
free list to prevent an SCB leak. This leak is a rarity
and would only occur if a bus reset or timeout resulting
in a bus reset occurred in the middle of an SCB fetch.
Don't attempt to perform ULTRA transfers on ultra capable
adapters missing the external precision resistor required
for ultra speeds. I've never encountered an adapter
configured this way, but better safe than sorry.
Handle the case of 5MHz user sync rate set as "0" instead of 0x1c
in scratch ram.
If we lookup a period of 0 in our table (async), clear the scsi offset.
aic7xxx.h:
Adjust for the primary channel being represented as
a 2 bit integer in the flags member of the ahc softc.
Cleanup the flags definitions so that comment blocks are
not cramped.
Update seeprom definitions to correctly reflect the fact
that the primary channel is represented as a 2 bit integer.
Add AHC_ULTRA_DIASABLED softc flag to denote controllers
missing the external precision resistor.
aic7xxx.reg:
Add DFCACHETH to the definition of DFSTATUS for completness sake.
Add SEQ_FLAGS2 which currently only contains the SCB_DMA
(SCB DMA in progress) flag.
aic7xxx.seq:
Correct a problem when one lun has a disconnected untagged
transaction and another lun has disconnected tagged transactions.
Just because an entry is found in the untagged table doesn't
mean that it will match. If the match on the lun fails, cleanup
the SCB (return it to the disconnected list or free it), and snoop
for a tag message. Before this change, we reported an unsolicited
reselection. This bug was introduced about a month ago during an
overly aggressive optimization pass on the reselection code.
When cleaning up an SCB, we can't just blindly free the SCB. In
the paging case, if the SCB came off of the disconnected list, its
state may never have been updated in host memory. So, check the
disconnected bit in SCB_CONTROL and return the SCB to the disconnected
list if appropriate.
Manage the SCB_DMA flag of SEQ_FLAGS2.
More carefully shutdown the S/G dma engine in all cases by using
a subroutine. Supposedly not doing this can cause an arbiter hang
on some ULTRA2 chips.
Formatting cleanup.
On some chips, at least the aic7856, the transition from
MREQPEND to HDONE can take a full 4 clock cycles. Test
HDONE one more time to avoid this race. We only want our
FIFO hung recovery code to execute when the engine is
really hung.
aic7xxx_93cx6.c:
Sync perforce ids.
aic7xxx_freebsd.c:
Adjust for the primary channel being a 2 bit integer
rather than a flag for 'B' channel being the primary.
Namespace cleanup.
Unpause the sequencer in one error recovery path that
neglected to do so. This could have caused us to perform
a bus reset when a recovery message might have otherwise been
successful.
aic7xxx_freebsd.h:
Use AHC_PCI_CONFIG for controlling compilation of PCI
support consistently throughout the driver.
Move ahc_power_state_change() to OSM.
aic7xxx_inline.h
Namespace cleanup.
Adjust our interrupt handler so it will work in the edge
interrupt case. We must process all interrupt sources
when the interrupt fires or risk not ever getting an
interrupt again. This involves marking the fact
that we are relying on an edge interrupt in ahc->flags
and checking for this condition in addition to the
AHC_ALL_INTERRUPTS flag. This fixes hangs on the
284X and any other aic7770 installation where level
interrupts are not available.
aic7xxx_pci.c:
Move the powerstate manipulation code into the OSM. Several
OSes now provide this functionality natively.
Take another shot at using the data stored in scratch ram
if the SCB2 signature is correct and no SEEPROM data is
available. In the past this failed if external SCB ram
was configured because the memory port was locked. We
now release the memory port prior to testing the values
in SCB2 and re-acquire it prior to doing termination control.
Adjust for new 2 bit primary channel setting.
Trust the STPWLEVEL setting on v 3.X BIOSes too.
Configure any 785X ID in the same fashion and assume
that any device with a rev id of 1 or higher has the
PCI 2.1 retry bug.
2001-03-11 06:34:17 +00:00
|
|
|
ahc->flags |= 1;
|
2000-09-16 20:02:28 +00:00
|
|
|
|
|
|
|
|
if ((biosctrl & BIOSMODE) == BIOSDISABLED) {
|
|
|
|
|
ahc->flags |= AHC_USEDEFAULTS;
|
|
|
|
|
} else {
|
|
|
|
|
if ((ahc->features & AHC_WIDE) != 0) {
|
|
|
|
|
ahc->our_id = scsiconf1 & HWSCSIID;
|
|
|
|
|
if (scsiconf & TERM_ENB)
|
|
|
|
|
ahc->flags |= AHC_TERM_ENB_A;
|
|
|
|
|
} else {
|
|
|
|
|
ahc->our_id = scsiconf & HSCSIID;
|
|
|
|
|
ahc->our_id_b = scsiconf1 & HSCSIID;
|
|
|
|
|
if (scsiconf & TERM_ENB)
|
|
|
|
|
ahc->flags |= AHC_TERM_ENB_A;
|
|
|
|
|
if (scsiconf1 & TERM_ENB)
|
|
|
|
|
ahc->flags |= AHC_TERM_ENB_B;
|
|
|
|
|
}
|
|
|
|
|
}
|
2002-08-31 06:40:32 +00:00
|
|
|
if ((ahc_inb(ahc, HA_274_BIOSGLOBAL) & HA_274_EXTENDED_TRANS))
|
|
|
|
|
ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B;
|
2000-09-16 20:02:28 +00:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case AHC_VL:
|
|
|
|
|
{
|
2002-08-31 06:40:32 +00:00
|
|
|
have_seeprom = aha2840_load_seeprom(ahc);
|
2000-09-16 20:02:28 +00:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
2002-08-31 06:40:32 +00:00
|
|
|
if (have_seeprom == 0) {
|
|
|
|
|
free(ahc->seep_config, M_DEVBUF);
|
|
|
|
|
ahc->seep_config = NULL;
|
|
|
|
|
}
|
2000-09-16 20:02:28 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Ensure autoflush is enabled
|
|
|
|
|
*/
|
|
|
|
|
ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~AUTOFLUSHDIS);
|
|
|
|
|
|
|
|
|
|
/* Setup the FIFO threshold and the bus off time */
|
|
|
|
|
hostconf = ahc_inb(ahc, HOSTCONF);
|
|
|
|
|
ahc_outb(ahc, BUSSPD, hostconf & DFTHRSH);
|
|
|
|
|
ahc_outb(ahc, BUSTIME, (hostconf << 2) & BOFF);
|
|
|
|
|
|
2003-05-03 23:55:38 +00:00
|
|
|
ahc->bus_softc.aic7770_softc.busspd = hostconf & DFTHRSH;
|
|
|
|
|
ahc->bus_softc.aic7770_softc.bustime = (hostconf << 2) & BOFF;
|
|
|
|
|
|
2000-09-16 20:02:28 +00:00
|
|
|
/*
|
|
|
|
|
* Generic aic7xxx initialization.
|
|
|
|
|
*/
|
|
|
|
|
error = ahc_init(ahc);
|
|
|
|
|
if (error != 0)
|
|
|
|
|
return (error);
|
|
|
|
|
|
2002-08-31 06:40:32 +00:00
|
|
|
error = aic7770_map_int(ahc, irq);
|
|
|
|
|
if (error != 0)
|
|
|
|
|
return (error);
|
|
|
|
|
|
2007-04-17 06:26:25 +00:00
|
|
|
ahc_lock(ahc);
|
2001-01-22 21:03:48 +00:00
|
|
|
/*
|
|
|
|
|
* Link this softc in with all other ahc instances.
|
|
|
|
|
*/
|
|
|
|
|
ahc_softc_insert(ahc);
|
|
|
|
|
|
2000-09-16 20:02:28 +00:00
|
|
|
/*
|
|
|
|
|
* Enable the board's BUS drivers
|
|
|
|
|
*/
|
|
|
|
|
ahc_outb(ahc, BCTL, ENABLE);
|
|
|
|
|
|
2007-04-17 06:26:25 +00:00
|
|
|
ahc_unlock(ahc);
|
2001-03-29 00:36:35 +00:00
|
|
|
|
2000-09-16 20:02:28 +00:00
|
|
|
return (0);
|
|
|
|
|
}
|
|
|
|
|
|
2003-05-03 23:55:38 +00:00
|
|
|
static int
|
|
|
|
|
aic7770_chip_init(struct ahc_softc *ahc)
|
|
|
|
|
{
|
|
|
|
|
ahc_outb(ahc, BUSSPD, ahc->bus_softc.aic7770_softc.busspd);
|
|
|
|
|
ahc_outb(ahc, BUSTIME, ahc->bus_softc.aic7770_softc.bustime);
|
|
|
|
|
ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~AUTOFLUSHDIS);
|
|
|
|
|
ahc_outb(ahc, BCTL, ENABLE);
|
|
|
|
|
return (ahc_chip_init(ahc));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
aic7770_suspend(struct ahc_softc *ahc)
|
|
|
|
|
{
|
|
|
|
|
return (ahc_suspend(ahc));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
aic7770_resume(struct ahc_softc *ahc)
|
|
|
|
|
{
|
|
|
|
|
return (ahc_resume(ahc));
|
|
|
|
|
}
|
|
|
|
|
|
2000-09-16 20:02:28 +00:00
|
|
|
/*
|
|
|
|
|
* Read the 284x SEEPROM.
|
|
|
|
|
*/
|
2002-08-31 06:40:32 +00:00
|
|
|
static int
|
2000-09-16 20:02:28 +00:00
|
|
|
aha2840_load_seeprom(struct ahc_softc *ahc)
|
|
|
|
|
{
|
2002-08-31 06:40:32 +00:00
|
|
|
struct seeprom_descriptor sd;
|
|
|
|
|
struct seeprom_config *sc;
|
|
|
|
|
int have_seeprom;
|
|
|
|
|
uint8_t scsi_conf;
|
2000-09-16 20:02:28 +00:00
|
|
|
|
|
|
|
|
sd.sd_ahc = ahc;
|
|
|
|
|
sd.sd_control_offset = SEECTL_2840;
|
|
|
|
|
sd.sd_status_offset = STATUS_2840;
|
|
|
|
|
sd.sd_dataout_offset = STATUS_2840;
|
|
|
|
|
sd.sd_chip = C46;
|
|
|
|
|
sd.sd_MS = 0;
|
|
|
|
|
sd.sd_RDY = EEPROM_TF;
|
|
|
|
|
sd.sd_CS = CS_2840;
|
|
|
|
|
sd.sd_CK = CK_2840;
|
|
|
|
|
sd.sd_DO = DO_2840;
|
|
|
|
|
sd.sd_DI = DI_2840;
|
2002-08-31 06:40:32 +00:00
|
|
|
sc = ahc->seep_config;
|
2000-09-16 20:02:28 +00:00
|
|
|
|
|
|
|
|
if (bootverbose)
|
|
|
|
|
printf("%s: Reading SEEPROM...", ahc_name(ahc));
|
2002-09-30 19:55:42 +00:00
|
|
|
have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc,
|
2003-05-03 23:55:38 +00:00
|
|
|
/*start_addr*/0, sizeof(*sc)/2);
|
2000-09-16 20:02:28 +00:00
|
|
|
|
|
|
|
|
if (have_seeprom) {
|
|
|
|
|
|
2002-08-31 06:40:32 +00:00
|
|
|
if (ahc_verify_cksum(sc) == 0) {
|
2000-09-16 20:02:28 +00:00
|
|
|
if(bootverbose)
|
|
|
|
|
printf ("checksum error\n");
|
|
|
|
|
have_seeprom = 0;
|
|
|
|
|
} else if (bootverbose) {
|
|
|
|
|
printf("done.\n");
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (!have_seeprom) {
|
|
|
|
|
if (bootverbose)
|
|
|
|
|
printf("%s: No SEEPROM available\n", ahc_name(ahc));
|
|
|
|
|
ahc->flags |= AHC_USEDEFAULTS;
|
|
|
|
|
} else {
|
|
|
|
|
/*
|
|
|
|
|
* Put the data we've collected down into SRAM
|
|
|
|
|
* where ahc_init will find it.
|
|
|
|
|
*/
|
2002-08-31 06:40:32 +00:00
|
|
|
int i;
|
|
|
|
|
int max_targ;
|
2000-09-16 20:02:28 +00:00
|
|
|
uint16_t discenable;
|
|
|
|
|
|
2002-08-31 06:40:32 +00:00
|
|
|
max_targ = (ahc->features & AHC_WIDE) != 0 ? 16 : 8;
|
2000-09-16 20:02:28 +00:00
|
|
|
discenable = 0;
|
|
|
|
|
for (i = 0; i < max_targ; i++){
|
2002-08-31 06:40:32 +00:00
|
|
|
uint8_t target_settings;
|
|
|
|
|
|
|
|
|
|
target_settings = (sc->device_flags[i] & CFXFER) << 4;
|
|
|
|
|
if (sc->device_flags[i] & CFSYNCH)
|
2000-09-16 20:02:28 +00:00
|
|
|
target_settings |= SOFS;
|
2002-08-31 06:40:32 +00:00
|
|
|
if (sc->device_flags[i] & CFWIDEB)
|
2000-09-16 20:02:28 +00:00
|
|
|
target_settings |= WIDEXFER;
|
2002-08-31 06:40:32 +00:00
|
|
|
if (sc->device_flags[i] & CFDISC)
|
2000-09-16 20:02:28 +00:00
|
|
|
discenable |= (0x01 << i);
|
|
|
|
|
ahc_outb(ahc, TARG_SCSIRATE + i, target_settings);
|
|
|
|
|
}
|
|
|
|
|
ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff));
|
|
|
|
|
ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff));
|
|
|
|
|
|
2002-08-31 06:40:32 +00:00
|
|
|
ahc->our_id = sc->brtime_id & CFSCSIID;
|
2000-09-16 20:02:28 +00:00
|
|
|
|
|
|
|
|
scsi_conf = (ahc->our_id & 0x7);
|
2002-08-31 06:40:32 +00:00
|
|
|
if (sc->adapter_control & CFSPARITY)
|
2000-09-16 20:02:28 +00:00
|
|
|
scsi_conf |= ENSPCHK;
|
2002-08-31 06:40:32 +00:00
|
|
|
if (sc->adapter_control & CFRESETB)
|
2000-09-16 20:02:28 +00:00
|
|
|
scsi_conf |= RESET_SCSI;
|
|
|
|
|
|
2002-08-31 06:40:32 +00:00
|
|
|
if (sc->bios_control & CF284XEXTEND)
|
2000-09-16 20:02:28 +00:00
|
|
|
ahc->flags |= AHC_EXTENDED_TRANS_A;
|
|
|
|
|
/* Set SCSICONF info */
|
|
|
|
|
ahc_outb(ahc, SCSICONF, scsi_conf);
|
|
|
|
|
|
2002-08-31 06:40:32 +00:00
|
|
|
if (sc->adapter_control & CF284XSTERM)
|
2000-09-16 20:02:28 +00:00
|
|
|
ahc->flags |= AHC_TERM_ENB_A;
|
|
|
|
|
}
|
2002-08-31 06:40:32 +00:00
|
|
|
return (have_seeprom);
|
2000-09-16 20:02:28 +00:00
|
|
|
}
|
|
|
|
|
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static int
|
2001-07-18 21:39:48 +00:00
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ahc_aic7770_VL_setup(struct ahc_softc *ahc)
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2000-09-16 20:02:28 +00:00
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{
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int error;
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2001-07-18 21:39:48 +00:00
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error = ahc_aic7770_setup(ahc);
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ahc->chip |= AHC_VL;
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2000-09-16 20:02:28 +00:00
|
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return (error);
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}
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static int
|
2001-07-18 21:39:48 +00:00
|
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ahc_aic7770_EISA_setup(struct ahc_softc *ahc)
|
2000-09-16 20:02:28 +00:00
|
|
|
{
|
|
|
|
|
int error;
|
|
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|
2001-07-18 21:39:48 +00:00
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error = ahc_aic7770_setup(ahc);
|
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|
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|
ahc->chip |= AHC_EISA;
|
2000-09-16 20:02:28 +00:00
|
|
|
return (error);
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}
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static int
|
2001-07-18 21:39:48 +00:00
|
|
|
ahc_aic7770_setup(struct ahc_softc *ahc)
|
2000-09-16 20:02:28 +00:00
|
|
|
{
|
2001-07-18 21:39:48 +00:00
|
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|
ahc->channel = 'A';
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|
ahc->channel_b = 'B';
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|
ahc->chip = AHC_AIC7770;
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|
|
|
ahc->features = AHC_AIC7770_FE;
|
|
|
|
|
ahc->bugs |= AHC_TMODE_WIDEODD_BUG;
|
|
|
|
|
ahc->flags |= AHC_PAGESCBS;
|
2003-05-03 23:55:38 +00:00
|
|
|
ahc->instruction_ram_size = 448;
|
2000-09-16 20:02:28 +00:00
|
|
|
return (0);
|
|
|
|
|
}
|
