45 lines
1.9 KiB
C
45 lines
1.9 KiB
C
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/*-
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* Copyright (C) 2005 TAKAHASHI Yoshihiro. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _PC98_CBUS_CBUS_DMAREG_H_
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#define _PC98_CBUS_CBUS_DMAREG_H_
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#include <dev/ic/i8237.h>
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#define IO_DMA 0x01 /* 8237A DMA Controller */
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/*
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* Register definitions for DMA controller 1 (channels 0..3):
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*/
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#define DMA1_CHN(c) (IO_DMA + (4*(c))) /* addr reg for channel c */
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#define DMA1_STATUS (IO_DMA + 0x10) /* status register */
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#define DMA1_SMSK (IO_DMA + 0x14) /* single mask register */
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#define DMA1_MODE (IO_DMA + 0x16) /* mode register */
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#define DMA1_FFC (IO_DMA + 0x18) /* clear first/last FF */
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#endif /* _PC98_CBUS_CBUS_DMAREG_H_ */
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