558 lines
14 KiB
C
558 lines
14 KiB
C
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/*-
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* Copyright (c) 2016 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* Allwinner DMA controller
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/condvar.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/endian.h>
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#include <machine/bus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm/allwinner/a10_dmac.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include "sunxi_dma_if.h"
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#define DMA_IRQ_EN_REG0 0x00
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#define DMA_IRQ_EN_REG1 0x04
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#define DMA_IRQ_EN_REG(ch) (DMA_IRQ_EN_REG0 + ((ch) / 8) * 4)
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#define DMA_PKG_IRQ_EN(ch) (1 << (((ch) % 8) * 4 + 1))
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#define DMA_PKG_IRQ_MASK 0x2222222222222222ULL
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#define DMA_IRQ_PEND_REG0 0x10
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#define DMA_IRQ_PEND_REG1 0x14
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#define DMA_IRQ_PEND_REG(ch) (DMA_IRQ_PEND_REG0 + ((ch) / 8) * 4)
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#define DMA_STA_REG 0x30
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#define DMA_EN_REG(n) (0x100 + (n) * 0x40 + 0x00)
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#define DMA_EN (1 << 0)
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#define DMA_PAU_REG(n) (0x100 + (n) * 0x40 + 0x04)
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#define DMA_STAR_ADDR_REG(n) (0x100 + (n) * 0x40 + 0x08)
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#define DMA_CFG_REG(n) (0x100 + (n) * 0x40 + 0x0c)
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#define DMA_DEST_DATA_WIDTH (0x3 << 25)
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#define DMA_DEST_DATA_WIDTH_SHIFT 25
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#define DMA_DEST_BST_LEN (0x3 << 22)
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#define DMA_DEST_BST_LEN_SHIFT 22
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#define DMA_DEST_ADDR_MODE (0x1 << 21)
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#define DMA_DEST_ADDR_MODE_SHIFT 21
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#define DMA_DEST_DRQ_TYPE (0x1f << 16)
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#define DMA_DEST_DRQ_TYPE_SHIFT 16
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#define DMA_SRC_DATA_WIDTH (0x3 << 9)
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#define DMA_SRC_DATA_WIDTH_SHIFT 9
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#define DMA_SRC_BST_LEN (0x3 << 6)
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#define DMA_SRC_BST_LEN_SHIFT 6
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#define DMA_SRC_ADDR_MODE (0x1 << 5)
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#define DMA_SRC_ADDR_MODE_SHIFT 5
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#define DMA_SRC_DRQ_TYPE (0x1f << 0)
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#define DMA_SRC_DRQ_TYPE_SHIFT 0
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#define DMA_DATA_WIDTH_8BIT 0
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#define DMA_DATA_WIDTH_16BIT 1
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#define DMA_DATA_WIDTH_32BIT 2
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#define DMA_DATA_WIDTH_64BIT 3
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#define DMA_ADDR_MODE_LINEAR 0
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#define DMA_ADDR_MODE_IO 1
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#define DMA_BST_LEN_1 0
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#define DMA_BST_LEN_4 1
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#define DMA_BST_LEN_8 2
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#define DMA_BST_LEN_16 3
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#define DMA_CUR_SRC_REG(n) (0x100 + (n) * 0x40 + 0x10)
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#define DMA_CUR_DEST_REG(n) (0x100 + (n) * 0x40 + 0x14)
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#define DMA_BCNT_LEFT_REG(n) (0x100 + (n) * 0x40 + 0x18)
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#define DMA_PARA_REG(n) (0x100 + (n) * 0x40 + 0x1c)
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#define WAIT_CYC (0xff << 0)
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#define WAIT_CYC_SHIFT 0
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struct a31dmac_desc {
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uint32_t config;
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uint32_t srcaddr;
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uint32_t dstaddr;
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uint32_t bcnt;
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uint32_t para;
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uint32_t next;
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#define DMA_NULL 0xfffff800
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};
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#define DESC_ALIGN 4
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#define DESC_SIZE sizeof(struct a31dmac_desc)
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struct a31dmac_config {
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u_int nchans;
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};
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static const struct a31dmac_config a31_config = { .nchans = 16 };
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static const struct a31dmac_config h3_config = { .nchans = 12 };
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static const struct a31dmac_config a83t_config = { .nchans = 8 };
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static const struct a31dmac_config a64_config = { .nchans = 8 };
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static struct ofw_compat_data compat_data[] = {
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{ "allwinner,sun6i-a31-dma", (uintptr_t)&a31_config },
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{ "allwinner,sun8i-a83t-dma", (uintptr_t)&a83t_config },
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{ "allwinner,sun8i-h3-dma", (uintptr_t)&h3_config },
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{ "allwinner,sun50i-a64-dma", (uintptr_t)&a64_config },
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{ NULL, (uintptr_t)NULL }
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};
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struct a31dmac_softc;
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struct a31dmac_channel {
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struct a31dmac_softc * sc;
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uint8_t index;
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void (*callback)(void *);
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void * callbackarg;
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bus_dmamap_t dmamap;
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struct a31dmac_desc *desc;
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bus_addr_t physaddr;
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};
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struct a31dmac_softc {
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struct resource * res[2];
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struct mtx mtx;
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void * ih;
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bus_dma_tag_t dmat;
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u_int nchans;
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struct a31dmac_channel * chans;
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};
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static struct resource_spec a31dmac_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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#define DMA_READ(sc, reg) bus_read_4((sc)->res[0], (reg))
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#define DMA_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))
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static void a31dmac_intr(void *);
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static void a31dmac_dmamap_cb(void *, bus_dma_segment_t *, int, int);
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static int
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a31dmac_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
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return (ENXIO);
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device_set_desc(dev, "Allwinner DMA controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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a31dmac_attach(device_t dev)
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{
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struct a31dmac_softc *sc;
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struct a31dmac_config *conf;
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u_int index;
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hwreset_t rst;
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clk_t clk;
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int error;
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sc = device_get_softc(dev);
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conf = (void *)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
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clk = NULL;
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rst = NULL;
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if (bus_alloc_resources(dev, a31dmac_spec, sc->res)) {
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device_printf(dev, "cannot allocate resources for device\n");
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return (ENXIO);
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}
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mtx_init(&sc->mtx, "a31 dmac", NULL, MTX_SPIN);
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/* Clock and reset setup */
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if (clk_get_by_ofw_index(dev, 0, 0, &clk) != 0) {
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device_printf(dev, "cannot get clock\n");
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goto fail;
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}
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if (clk_enable(clk) != 0) {
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device_printf(dev, "cannot enable clock\n");
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goto fail;
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}
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if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) != 0) {
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device_printf(dev, "cannot get hwreset\n");
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goto fail;
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}
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if (hwreset_deassert(rst) != 0) {
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device_printf(dev, "cannot de-assert reset\n");
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goto fail;
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}
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/* Descriptor DMA */
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error = bus_dma_tag_create(
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bus_get_dma_tag(dev), /* Parent tag */
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DESC_ALIGN, 0, /* alignment, boundary */
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BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
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BUS_SPACE_MAXADDR, /* highaddr */
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NULL, NULL, /* filter, filterarg */
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DESC_SIZE, 1, /* maxsize, nsegs */
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DESC_SIZE, /* maxsegsize */
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0, /* flags */
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NULL, NULL, /* lockfunc, lockarg */
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&sc->dmat);
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if (error != 0) {
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device_printf(dev, "cannot create dma tag\n");
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goto fail;
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}
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/* Disable all interrupts and clear pending status */
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DMA_WRITE(sc, DMA_IRQ_EN_REG0, 0);
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DMA_WRITE(sc, DMA_IRQ_EN_REG1, 0);
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DMA_WRITE(sc, DMA_IRQ_PEND_REG0, ~0);
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DMA_WRITE(sc, DMA_IRQ_PEND_REG1, ~0);
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/* Initialize channels */
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sc->nchans = conf->nchans;
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sc->chans = malloc(sizeof(*sc->chans) * sc->nchans, M_DEVBUF,
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M_WAITOK | M_ZERO);
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for (index = 0; index < sc->nchans; index++) {
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sc->chans[index].sc = sc;
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sc->chans[index].index = index;
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sc->chans[index].callback = NULL;
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sc->chans[index].callbackarg = NULL;
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error = bus_dmamem_alloc(sc->dmat,
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(void **)&sc->chans[index].desc,
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BUS_DMA_WAITOK | BUS_DMA_COHERENT,
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&sc->chans[index].dmamap);
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if (error != 0) {
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device_printf(dev, "cannot allocate dma mem\n");
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goto fail;
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}
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error = bus_dmamap_load(sc->dmat, sc->chans[index].dmamap,
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sc->chans[index].desc, sizeof(*sc->chans[index].desc),
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a31dmac_dmamap_cb, &sc->chans[index], BUS_DMA_WAITOK);
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if (error != 0) {
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device_printf(dev, "cannot load dma map\n");
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goto fail;
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}
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DMA_WRITE(sc, DMA_EN_REG(index), 0);
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}
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error = bus_setup_intr(dev, sc->res[1], INTR_MPSAFE | INTR_TYPE_MISC,
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NULL, a31dmac_intr, sc, &sc->ih);
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if (error != 0) {
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device_printf(dev, "could not setup interrupt handler\n");
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bus_release_resources(dev, a31dmac_spec, sc->res);
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mtx_destroy(&sc->mtx);
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return (ENXIO);
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}
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OF_device_register_xref(OF_xref_from_node(ofw_bus_get_node(dev)), dev);
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return (0);
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fail:
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for (index = 0; index < sc->nchans; index++)
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if (sc->chans[index].desc != NULL) {
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bus_dmamap_unload(sc->dmat, sc->chans[index].dmamap);
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bus_dmamem_free(sc->dmat, sc->chans[index].desc,
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sc->chans[index].dmamap);
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}
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if (sc->chans != NULL)
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free(sc->chans, M_DEVBUF);
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if (sc->ih != NULL)
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bus_teardown_intr(dev, sc->res[1], sc->ih);
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if (rst != NULL)
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hwreset_release(rst);
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if (clk != NULL)
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clk_release(clk);
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bus_release_resources(dev, a31dmac_spec, sc->res);
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return (ENXIO);
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}
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static void
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a31dmac_dmamap_cb(void *priv, bus_dma_segment_t *segs, int nsegs, int error)
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{
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struct a31dmac_channel *ch;
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if (error != 0)
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return;
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ch = priv;
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ch->physaddr = segs[0].ds_addr;
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}
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static void
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a31dmac_intr(void *priv)
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{
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struct a31dmac_softc *sc;
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uint32_t pend0, pend1, bit;
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uint64_t pend, mask;
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u_int index;
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sc = priv;
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pend0 = DMA_READ(sc, DMA_IRQ_PEND_REG0);
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pend1 = sc->nchans > 8 ? DMA_READ(sc, DMA_IRQ_PEND_REG1) : 0;
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if (pend0 == 0 && pend1 == 0)
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return;
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if (pend0 != 0)
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DMA_WRITE(sc, DMA_IRQ_PEND_REG0, pend0);
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if (pend1 != 0)
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DMA_WRITE(sc, DMA_IRQ_PEND_REG1, pend1);
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pend = pend0 | ((uint64_t)pend1 << 32);
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while ((bit = ffsll(pend & DMA_PKG_IRQ_MASK)) != 0) {
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mask = (1U << (bit - 1));
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pend &= ~mask;
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index = (bit - 1) / 4;
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if (index >= sc->nchans)
|
||
|
|
continue;
|
||
|
|
if (sc->chans[index].callback == NULL)
|
||
|
|
continue;
|
||
|
|
sc->chans[index].callback(sc->chans[index].callbackarg);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static int
|
||
|
|
a31dmac_set_config(device_t dev, void *priv, const struct sunxi_dma_config *cfg)
|
||
|
|
{
|
||
|
|
struct a31dmac_channel *ch;
|
||
|
|
uint32_t config, para;
|
||
|
|
unsigned int dst_dw, dst_bl, dst_wc, dst_am;
|
||
|
|
unsigned int src_dw, src_bl, src_wc, src_am;
|
||
|
|
|
||
|
|
ch = priv;
|
||
|
|
|
||
|
|
switch (cfg->dst_width) {
|
||
|
|
case 8:
|
||
|
|
dst_dw = DMA_DATA_WIDTH_8BIT;
|
||
|
|
break;
|
||
|
|
case 16:
|
||
|
|
dst_dw = DMA_DATA_WIDTH_16BIT;
|
||
|
|
break;
|
||
|
|
case 32:
|
||
|
|
dst_dw = DMA_DATA_WIDTH_32BIT;
|
||
|
|
break;
|
||
|
|
case 64:
|
||
|
|
dst_dw = DMA_DATA_WIDTH_64BIT;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
return (EINVAL);
|
||
|
|
}
|
||
|
|
switch (cfg->dst_burst_len) {
|
||
|
|
case 1:
|
||
|
|
dst_bl = DMA_BST_LEN_1;
|
||
|
|
break;
|
||
|
|
case 4:
|
||
|
|
dst_bl = DMA_BST_LEN_4;
|
||
|
|
break;
|
||
|
|
case 8:
|
||
|
|
dst_bl = DMA_BST_LEN_8;
|
||
|
|
break;
|
||
|
|
case 16:
|
||
|
|
dst_bl = DMA_BST_LEN_16;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
return (EINVAL);
|
||
|
|
}
|
||
|
|
switch (cfg->src_width) {
|
||
|
|
case 8:
|
||
|
|
src_dw = DMA_DATA_WIDTH_8BIT;
|
||
|
|
break;
|
||
|
|
case 16:
|
||
|
|
src_dw = DMA_DATA_WIDTH_16BIT;
|
||
|
|
break;
|
||
|
|
case 32:
|
||
|
|
src_dw = DMA_DATA_WIDTH_32BIT;
|
||
|
|
break;
|
||
|
|
case 64:
|
||
|
|
src_dw = DMA_DATA_WIDTH_64BIT;
|
||
|
|
default:
|
||
|
|
return (EINVAL);
|
||
|
|
}
|
||
|
|
switch (cfg->src_burst_len) {
|
||
|
|
case 1:
|
||
|
|
src_bl = DMA_BST_LEN_1;
|
||
|
|
break;
|
||
|
|
case 4:
|
||
|
|
src_bl = DMA_BST_LEN_4;
|
||
|
|
break;
|
||
|
|
case 8:
|
||
|
|
src_bl = DMA_BST_LEN_8;
|
||
|
|
break;
|
||
|
|
case 16:
|
||
|
|
src_bl = DMA_BST_LEN_16;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
return (EINVAL);
|
||
|
|
}
|
||
|
|
dst_am = cfg->dst_noincr ? DMA_ADDR_MODE_IO : DMA_ADDR_MODE_LINEAR;
|
||
|
|
src_am = cfg->src_noincr ? DMA_ADDR_MODE_IO : DMA_ADDR_MODE_LINEAR;
|
||
|
|
dst_wc = cfg->dst_wait_cyc;
|
||
|
|
src_wc = cfg->src_wait_cyc;
|
||
|
|
if (dst_wc != src_wc)
|
||
|
|
return (EINVAL);
|
||
|
|
|
||
|
|
config = (dst_dw << DMA_DEST_DATA_WIDTH_SHIFT) |
|
||
|
|
(dst_bl << DMA_DEST_BST_LEN_SHIFT) |
|
||
|
|
(dst_am << DMA_DEST_ADDR_MODE_SHIFT) |
|
||
|
|
(cfg->dst_drqtype << DMA_DEST_DRQ_TYPE_SHIFT) |
|
||
|
|
(src_dw << DMA_SRC_DATA_WIDTH_SHIFT) |
|
||
|
|
(src_bl << DMA_SRC_BST_LEN_SHIFT) |
|
||
|
|
(src_am << DMA_SRC_ADDR_MODE_SHIFT) |
|
||
|
|
(cfg->src_drqtype << DMA_SRC_DRQ_TYPE_SHIFT);
|
||
|
|
para = (dst_wc << WAIT_CYC_SHIFT);
|
||
|
|
|
||
|
|
ch->desc->config = htole32(config);
|
||
|
|
ch->desc->para = htole32(para);
|
||
|
|
|
||
|
|
return (0);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void *
|
||
|
|
a31dmac_alloc(device_t dev, bool dedicated, void (*cb)(void *), void *cbarg)
|
||
|
|
{
|
||
|
|
struct a31dmac_softc *sc;
|
||
|
|
struct a31dmac_channel *ch;
|
||
|
|
uint32_t irqen;
|
||
|
|
u_int index;
|
||
|
|
|
||
|
|
sc = device_get_softc(dev);
|
||
|
|
ch = NULL;
|
||
|
|
|
||
|
|
mtx_lock_spin(&sc->mtx);
|
||
|
|
for (index = 0; index < sc->nchans; index++) {
|
||
|
|
if (sc->chans[index].callback == NULL) {
|
||
|
|
ch = &sc->chans[index];
|
||
|
|
ch->callback = cb;
|
||
|
|
ch->callbackarg = cbarg;
|
||
|
|
|
||
|
|
irqen = DMA_READ(sc, DMA_IRQ_EN_REG(index));
|
||
|
|
irqen |= DMA_PKG_IRQ_EN(index);
|
||
|
|
DMA_WRITE(sc, DMA_IRQ_EN_REG(index), irqen);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
mtx_unlock_spin(&sc->mtx);
|
||
|
|
|
||
|
|
return (ch);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void
|
||
|
|
a31dmac_free(device_t dev, void *priv)
|
||
|
|
{
|
||
|
|
struct a31dmac_channel *ch;
|
||
|
|
struct a31dmac_softc *sc;
|
||
|
|
uint32_t irqen;
|
||
|
|
u_int index;
|
||
|
|
|
||
|
|
ch = priv;
|
||
|
|
sc = ch->sc;
|
||
|
|
index = ch->index;
|
||
|
|
|
||
|
|
mtx_lock_spin(&sc->mtx);
|
||
|
|
|
||
|
|
irqen = DMA_READ(sc, DMA_IRQ_EN_REG(index));
|
||
|
|
irqen &= ~DMA_PKG_IRQ_EN(index);
|
||
|
|
DMA_WRITE(sc, DMA_IRQ_EN_REG(index), irqen);
|
||
|
|
DMA_WRITE(sc, DMA_IRQ_PEND_REG(index), DMA_PKG_IRQ_EN(index));
|
||
|
|
|
||
|
|
ch->callback = NULL;
|
||
|
|
ch->callbackarg = NULL;
|
||
|
|
|
||
|
|
mtx_unlock_spin(&sc->mtx);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int
|
||
|
|
a31dmac_transfer(device_t dev, void *priv, bus_addr_t src, bus_addr_t dst,
|
||
|
|
size_t nbytes)
|
||
|
|
{
|
||
|
|
struct a31dmac_channel *ch;
|
||
|
|
struct a31dmac_softc *sc;
|
||
|
|
|
||
|
|
ch = priv;
|
||
|
|
sc = ch->sc;
|
||
|
|
|
||
|
|
ch->desc->srcaddr = htole32((uint32_t)src);
|
||
|
|
ch->desc->dstaddr = htole32((uint32_t)dst);
|
||
|
|
ch->desc->bcnt = htole32(nbytes);
|
||
|
|
ch->desc->next = htole32(DMA_NULL);
|
||
|
|
|
||
|
|
DMA_WRITE(sc, DMA_STAR_ADDR_REG(ch->index), (uint32_t)ch->physaddr);
|
||
|
|
DMA_WRITE(sc, DMA_EN_REG(ch->index), DMA_EN);
|
||
|
|
|
||
|
|
return (0);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void
|
||
|
|
a31dmac_halt(device_t dev, void *priv)
|
||
|
|
{
|
||
|
|
struct a31dmac_channel *ch;
|
||
|
|
struct a31dmac_softc *sc;
|
||
|
|
|
||
|
|
ch = priv;
|
||
|
|
sc = ch->sc;
|
||
|
|
|
||
|
|
DMA_WRITE(sc, DMA_EN_REG(ch->index), 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
static device_method_t a31dmac_methods[] = {
|
||
|
|
/* Device interface */
|
||
|
|
DEVMETHOD(device_probe, a31dmac_probe),
|
||
|
|
DEVMETHOD(device_attach, a31dmac_attach),
|
||
|
|
|
||
|
|
/* sunxi DMA interface */
|
||
|
|
DEVMETHOD(sunxi_dma_alloc, a31dmac_alloc),
|
||
|
|
DEVMETHOD(sunxi_dma_free, a31dmac_free),
|
||
|
|
DEVMETHOD(sunxi_dma_set_config, a31dmac_set_config),
|
||
|
|
DEVMETHOD(sunxi_dma_transfer, a31dmac_transfer),
|
||
|
|
DEVMETHOD(sunxi_dma_halt, a31dmac_halt),
|
||
|
|
|
||
|
|
DEVMETHOD_END
|
||
|
|
};
|
||
|
|
|
||
|
|
static driver_t a31dmac_driver = {
|
||
|
|
"a31dmac",
|
||
|
|
a31dmac_methods,
|
||
|
|
sizeof(struct a31dmac_softc)
|
||
|
|
};
|
||
|
|
|
||
|
|
static devclass_t a31dmac_devclass;
|
||
|
|
|
||
|
|
DRIVER_MODULE(a31dmac, simplebus, a31dmac_driver, a31dmac_devclass, 0, 0);
|