2011-10-04 21:40:25 +00:00
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/*
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* Copyright (c) 2010, LSI Corp.
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* All rights reserved.
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* Author : Manjunath Ranganathaiah
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* Support: freebsdraid@lsi.com
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name of the <ORGANIZATION> nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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2011-11-22 21:28:20 +00:00
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*/
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2011-10-04 21:40:25 +00:00
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2011-11-22 21:28:20 +00:00
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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2011-10-04 21:40:25 +00:00
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#include <dev/tws/tws.h>
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#include <dev/tws/tws_services.h>
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#include <dev/tws/tws_hdm.h>
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#include <cam/cam.h>
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#include <cam/cam_ccb.h>
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MALLOC_DEFINE(M_TWS, "twsbuf", "buffers used by tws driver");
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int tws_queue_depth = TWS_MAX_REQS;
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int tws_enable_msi = 0;
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int tws_enable_msix = 0;
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/* externs */
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extern int tws_cam_attach(struct tws_softc *sc);
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extern void tws_cam_detach(struct tws_softc *sc);
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extern int tws_init_ctlr(struct tws_softc *sc);
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extern boolean tws_ctlr_ready(struct tws_softc *sc);
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extern void tws_turn_off_interrupts(struct tws_softc *sc);
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extern void tws_q_insert_tail(struct tws_softc *sc, struct tws_request *req,
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u_int8_t q_type );
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extern struct tws_request *tws_q_remove_request(struct tws_softc *sc,
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struct tws_request *req, u_int8_t q_type );
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extern struct tws_request *tws_q_remove_head(struct tws_softc *sc,
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u_int8_t q_type );
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extern boolean tws_get_response(struct tws_softc *sc, u_int16_t *req_id);
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extern boolean tws_ctlr_reset(struct tws_softc *sc);
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extern void tws_intr(void *arg);
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extern int tws_use_32bit_sgls;
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struct tws_request *tws_get_request(struct tws_softc *sc, u_int16_t type);
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int tws_init_connect(struct tws_softc *sc, u_int16_t mc);
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void tws_send_event(struct tws_softc *sc, u_int8_t event);
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uint8_t tws_get_state(struct tws_softc *sc);
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void tws_release_request(struct tws_request *req);
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/* Function prototypes */
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static d_open_t tws_open;
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static d_close_t tws_close;
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static d_read_t tws_read;
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static d_write_t tws_write;
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extern d_ioctl_t tws_ioctl;
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static int tws_init(struct tws_softc *sc);
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static void tws_dmamap_cmds_load_cbfn(void *arg, bus_dma_segment_t *segs,
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int nseg, int error);
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static int tws_init_reqs(struct tws_softc *sc, u_int32_t dma_mem_size);
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static int tws_init_aen_q(struct tws_softc *sc);
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static int tws_init_trace_q(struct tws_softc *sc);
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static int tws_setup_irq(struct tws_softc *sc);
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int tws_setup_intr(struct tws_softc *sc, int irqs);
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int tws_teardown_intr(struct tws_softc *sc);
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/* Character device entry points */
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static struct cdevsw tws_cdevsw = {
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.d_version = D_VERSION,
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.d_open = tws_open,
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.d_close = tws_close,
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.d_read = tws_read,
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.d_write = tws_write,
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.d_ioctl = tws_ioctl,
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.d_name = "tws",
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};
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/*
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* In the cdevsw routines, we find our softc by using the si_drv1 member
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* of struct cdev. We set this variable to point to our softc in our
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* attach routine when we create the /dev entry.
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*/
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int
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tws_open(struct cdev *dev, int oflags, int devtype, d_thread_t *td)
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{
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struct tws_softc *sc = dev->si_drv1;
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if ( sc )
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TWS_TRACE_DEBUG(sc, "entry", dev, oflags);
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return (0);
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}
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int
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tws_close(struct cdev *dev, int fflag, int devtype, d_thread_t *td)
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{
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struct tws_softc *sc = dev->si_drv1;
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if ( sc )
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TWS_TRACE_DEBUG(sc, "entry", dev, fflag);
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return (0);
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}
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int
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tws_read(struct cdev *dev, struct uio *uio, int ioflag)
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{
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struct tws_softc *sc = dev->si_drv1;
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if ( sc )
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TWS_TRACE_DEBUG(sc, "entry", dev, ioflag);
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return (0);
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}
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int
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tws_write(struct cdev *dev, struct uio *uio, int ioflag)
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{
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struct tws_softc *sc = dev->si_drv1;
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if ( sc )
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TWS_TRACE_DEBUG(sc, "entry", dev, ioflag);
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return (0);
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}
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/* PCI Support Functions */
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/*
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* Compare the device ID of this device against the IDs that this driver
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* supports. If there is a match, set the description and return success.
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*/
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static int
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tws_probe(device_t dev)
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{
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static u_int8_t first_ctlr = 1;
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if ((pci_get_vendor(dev) == TWS_VENDOR_ID) &&
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(pci_get_device(dev) == TWS_DEVICE_ID)) {
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device_set_desc(dev, "LSI 3ware SAS/SATA Storage Controller");
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if (first_ctlr) {
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printf("LSI 3ware device driver for SAS/SATA storage "
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"controllers, version: %s\n", TWS_DRIVER_VERSION_STRING);
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first_ctlr = 0;
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}
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2011-10-17 19:21:42 +00:00
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return(BUS_PROBE_DEFAULT);
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2011-10-04 21:40:25 +00:00
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}
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return (ENXIO);
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}
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/* Attach function is only called if the probe is successful. */
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static int
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tws_attach(device_t dev)
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{
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struct tws_softc *sc = device_get_softc(dev);
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u_int32_t cmd, bar;
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int error=0,i;
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/* no tracing yet */
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/* Look up our softc and initialize its fields. */
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sc->tws_dev = dev;
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sc->device_id = pci_get_device(dev);
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sc->subvendor_id = pci_get_subvendor(dev);
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sc->subdevice_id = pci_get_subdevice(dev);
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/* Intialize mutexes */
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mtx_init( &sc->q_lock, "tws_q_lock", NULL, MTX_DEF);
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mtx_init( &sc->sim_lock, "tws_sim_lock", NULL, MTX_DEF);
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mtx_init( &sc->gen_lock, "tws_gen_lock", NULL, MTX_DEF);
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2012-09-24 21:40:22 +00:00
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mtx_init( &sc->io_lock, "tws_io_lock", NULL, MTX_DEF | MTX_RECURSE);
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2011-10-04 21:40:25 +00:00
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if ( tws_init_trace_q(sc) == FAILURE )
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printf("trace init failure\n");
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/* send init event */
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mtx_lock(&sc->gen_lock);
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tws_send_event(sc, TWS_INIT_START);
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mtx_unlock(&sc->gen_lock);
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#if _BYTE_ORDER == _BIG_ENDIAN
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TWS_TRACE(sc, "BIG endian", 0, 0);
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#endif
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/* sysctl context setup */
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sysctl_ctx_init(&sc->tws_clist);
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sc->tws_oidp = SYSCTL_ADD_NODE(&sc->tws_clist,
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SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
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device_get_nameunit(dev),
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CTLFLAG_RD, 0, "");
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if ( sc->tws_oidp == NULL ) {
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tws_log(sc, SYSCTL_TREE_NODE_ADD);
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goto attach_fail_1;
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}
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SYSCTL_ADD_STRING(&sc->tws_clist, SYSCTL_CHILDREN(sc->tws_oidp),
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OID_AUTO, "driver_version", CTLFLAG_RD,
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TWS_DRIVER_VERSION_STRING, 0, "TWS driver version");
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cmd = pci_read_config(dev, PCIR_COMMAND, 2);
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if ( (cmd & PCIM_CMD_PORTEN) == 0) {
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tws_log(sc, PCI_COMMAND_READ);
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goto attach_fail_1;
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}
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/* Force the busmaster enable bit on. */
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cmd |= PCIM_CMD_BUSMASTEREN;
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pci_write_config(dev, PCIR_COMMAND, cmd, 2);
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bar = pci_read_config(dev, TWS_PCI_BAR0, 4);
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TWS_TRACE_DEBUG(sc, "bar0 ", bar, 0);
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bar = pci_read_config(dev, TWS_PCI_BAR1, 4);
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bar = bar & ~TWS_BIT2;
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TWS_TRACE_DEBUG(sc, "bar1 ", bar, 0);
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/* MFA base address is BAR2 register used for
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* push mode. Firmware will evatualy move to
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* pull mode during witch this needs to change
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*/
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#ifndef TWS_PULL_MODE_ENABLE
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sc->mfa_base = (u_int64_t)pci_read_config(dev, TWS_PCI_BAR2, 4);
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sc->mfa_base = sc->mfa_base & ~TWS_BIT2;
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TWS_TRACE_DEBUG(sc, "bar2 ", sc->mfa_base, 0);
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#endif
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/* allocate MMIO register space */
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sc->reg_res_id = TWS_PCI_BAR1; /* BAR1 offset */
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if ((sc->reg_res = bus_alloc_resource(dev, SYS_RES_MEMORY,
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&(sc->reg_res_id), 0, ~0, 1, RF_ACTIVE))
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== NULL) {
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tws_log(sc, ALLOC_MEMORY_RES);
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goto attach_fail_1;
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}
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sc->bus_tag = rman_get_bustag(sc->reg_res);
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sc->bus_handle = rman_get_bushandle(sc->reg_res);
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#ifndef TWS_PULL_MODE_ENABLE
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/* Allocate bus space for inbound mfa */
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sc->mfa_res_id = TWS_PCI_BAR2; /* BAR2 offset */
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if ((sc->mfa_res = bus_alloc_resource(dev, SYS_RES_MEMORY,
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&(sc->mfa_res_id), 0, ~0, 0x100000, RF_ACTIVE))
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== NULL) {
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tws_log(sc, ALLOC_MEMORY_RES);
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goto attach_fail_2;
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}
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sc->bus_mfa_tag = rman_get_bustag(sc->mfa_res);
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sc->bus_mfa_handle = rman_get_bushandle(sc->mfa_res);
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#endif
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/* Allocate and register our interrupt. */
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sc->intr_type = TWS_INTx; /* default */
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if ( tws_enable_msi )
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sc->intr_type = TWS_MSI;
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if ( tws_setup_irq(sc) == FAILURE ) {
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tws_log(sc, ALLOC_MEMORY_RES);
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goto attach_fail_3;
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}
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/*
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* Create a /dev entry for this device. The kernel will assign us
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* a major number automatically. We use the unit number of this
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* device as the minor number and name the character device
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* "tws<unit>".
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*/
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sc->tws_cdev = make_dev(&tws_cdevsw, device_get_unit(dev),
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UID_ROOT, GID_OPERATOR, S_IRUSR | S_IWUSR, "tws%u",
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device_get_unit(dev));
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sc->tws_cdev->si_drv1 = sc;
|
|
|
|
|
|
|
|
|
|
if ( tws_init(sc) == FAILURE ) {
|
|
|
|
|
tws_log(sc, TWS_INIT_FAILURE);
|
|
|
|
|
goto attach_fail_4;
|
|
|
|
|
}
|
|
|
|
|
if ( tws_init_ctlr(sc) == FAILURE ) {
|
|
|
|
|
tws_log(sc, TWS_CTLR_INIT_FAILURE);
|
|
|
|
|
goto attach_fail_4;
|
|
|
|
|
}
|
|
|
|
|
if ((error = tws_cam_attach(sc))) {
|
|
|
|
|
tws_log(sc, TWS_CAM_ATTACH);
|
|
|
|
|
goto attach_fail_4;
|
|
|
|
|
}
|
|
|
|
|
/* send init complete event */
|
|
|
|
|
mtx_lock(&sc->gen_lock);
|
|
|
|
|
tws_send_event(sc, TWS_INIT_COMPLETE);
|
|
|
|
|
mtx_unlock(&sc->gen_lock);
|
|
|
|
|
|
|
|
|
|
TWS_TRACE_DEBUG(sc, "attached successfully", 0, sc->device_id);
|
|
|
|
|
return(0);
|
|
|
|
|
|
|
|
|
|
attach_fail_4:
|
|
|
|
|
tws_teardown_intr(sc);
|
|
|
|
|
destroy_dev(sc->tws_cdev);
|
|
|
|
|
attach_fail_3:
|
|
|
|
|
for(i=0;i<sc->irqs;i++) {
|
|
|
|
|
if ( sc->irq_res[i] ){
|
|
|
|
|
if (bus_release_resource(sc->tws_dev,
|
|
|
|
|
SYS_RES_IRQ, sc->irq_res_id[i], sc->irq_res[i]))
|
|
|
|
|
TWS_TRACE(sc, "bus irq res", 0, 0);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
#ifndef TWS_PULL_MODE_ENABLE
|
|
|
|
|
attach_fail_2:
|
|
|
|
|
#endif
|
|
|
|
|
if ( sc->mfa_res ){
|
|
|
|
|
if (bus_release_resource(sc->tws_dev,
|
|
|
|
|
SYS_RES_MEMORY, sc->mfa_res_id, sc->mfa_res))
|
|
|
|
|
TWS_TRACE(sc, "bus release ", 0, sc->mfa_res_id);
|
|
|
|
|
}
|
|
|
|
|
if ( sc->reg_res ){
|
|
|
|
|
if (bus_release_resource(sc->tws_dev,
|
|
|
|
|
SYS_RES_MEMORY, sc->reg_res_id, sc->reg_res))
|
|
|
|
|
TWS_TRACE(sc, "bus release2 ", 0, sc->reg_res_id);
|
|
|
|
|
}
|
|
|
|
|
attach_fail_1:
|
|
|
|
|
mtx_destroy(&sc->q_lock);
|
|
|
|
|
mtx_destroy(&sc->sim_lock);
|
|
|
|
|
mtx_destroy(&sc->gen_lock);
|
|
|
|
|
mtx_destroy(&sc->io_lock);
|
|
|
|
|
sysctl_ctx_free(&sc->tws_clist);
|
|
|
|
|
return (ENXIO);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Detach device. */
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
tws_detach(device_t dev)
|
|
|
|
|
{
|
|
|
|
|
struct tws_softc *sc = device_get_softc(dev);
|
|
|
|
|
int i;
|
|
|
|
|
u_int32_t reg;
|
|
|
|
|
|
|
|
|
|
TWS_TRACE_DEBUG(sc, "entry", 0, 0);
|
|
|
|
|
|
|
|
|
|
mtx_lock(&sc->gen_lock);
|
|
|
|
|
tws_send_event(sc, TWS_UNINIT_START);
|
|
|
|
|
mtx_unlock(&sc->gen_lock);
|
|
|
|
|
|
|
|
|
|
/* needs to disable interrupt before detaching from cam */
|
|
|
|
|
tws_turn_off_interrupts(sc);
|
|
|
|
|
/* clear door bell */
|
|
|
|
|
tws_write_reg(sc, TWS_I2O0_HOBDBC, ~0, 4);
|
|
|
|
|
reg = tws_read_reg(sc, TWS_I2O0_HIMASK, 4);
|
|
|
|
|
TWS_TRACE_DEBUG(sc, "turn-off-intr", reg, 0);
|
|
|
|
|
sc->obfl_q_overrun = false;
|
|
|
|
|
tws_init_connect(sc, 1);
|
|
|
|
|
|
|
|
|
|
/* Teardown the state in our softc created in our attach routine. */
|
|
|
|
|
/* Disconnect the interrupt handler. */
|
|
|
|
|
tws_teardown_intr(sc);
|
|
|
|
|
|
|
|
|
|
/* Release irq resource */
|
|
|
|
|
for(i=0;i<sc->irqs;i++) {
|
|
|
|
|
if ( sc->irq_res[i] ){
|
|
|
|
|
if (bus_release_resource(sc->tws_dev,
|
|
|
|
|
SYS_RES_IRQ, sc->irq_res_id[i], sc->irq_res[i]))
|
|
|
|
|
TWS_TRACE(sc, "bus release irq resource",
|
|
|
|
|
i, sc->irq_res_id[i]);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if ( sc->intr_type == TWS_MSI ) {
|
|
|
|
|
pci_release_msi(sc->tws_dev);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
tws_cam_detach(sc);
|
|
|
|
|
|
|
|
|
|
/* Release memory resource */
|
|
|
|
|
if ( sc->mfa_res ){
|
|
|
|
|
if (bus_release_resource(sc->tws_dev,
|
|
|
|
|
SYS_RES_MEMORY, sc->mfa_res_id, sc->mfa_res))
|
|
|
|
|
TWS_TRACE(sc, "bus release mem resource", 0, sc->mfa_res_id);
|
|
|
|
|
}
|
|
|
|
|
if ( sc->reg_res ){
|
|
|
|
|
if (bus_release_resource(sc->tws_dev,
|
|
|
|
|
SYS_RES_MEMORY, sc->reg_res_id, sc->reg_res))
|
|
|
|
|
TWS_TRACE(sc, "bus release mem resource", 0, sc->reg_res_id);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
free(sc->reqs, M_TWS);
|
|
|
|
|
free(sc->sense_bufs, M_TWS);
|
|
|
|
|
free(sc->scan_ccb, M_TWS);
|
2012-10-19 22:07:40 +00:00
|
|
|
if (sc->ioctl_data_mem)
|
|
|
|
|
bus_dmamem_free(sc->data_tag, sc->ioctl_data_mem, sc->ioctl_data_map);
|
2011-10-04 21:40:25 +00:00
|
|
|
free(sc->aen_q.q, M_TWS);
|
|
|
|
|
free(sc->trace_q.q, M_TWS);
|
|
|
|
|
mtx_destroy(&sc->q_lock);
|
|
|
|
|
mtx_destroy(&sc->sim_lock);
|
|
|
|
|
mtx_destroy(&sc->gen_lock);
|
|
|
|
|
mtx_destroy(&sc->io_lock);
|
|
|
|
|
destroy_dev(sc->tws_cdev);
|
|
|
|
|
sysctl_ctx_free(&sc->tws_clist);
|
|
|
|
|
return (0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int
|
|
|
|
|
tws_setup_intr(struct tws_softc *sc, int irqs)
|
|
|
|
|
{
|
|
|
|
|
int i, error;
|
|
|
|
|
|
|
|
|
|
for(i=0;i<irqs;i++) {
|
|
|
|
|
if (!(sc->intr_handle[i])) {
|
|
|
|
|
if ((error = bus_setup_intr(sc->tws_dev, sc->irq_res[i],
|
|
|
|
|
INTR_TYPE_CAM | INTR_MPSAFE,
|
|
|
|
|
#if (__FreeBSD_version >= 700000)
|
|
|
|
|
NULL,
|
|
|
|
|
#endif
|
|
|
|
|
tws_intr, sc, &sc->intr_handle[i]))) {
|
|
|
|
|
tws_log(sc, SETUP_INTR_RES);
|
|
|
|
|
return(FAILURE);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
return(SUCCESS);
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
int
|
|
|
|
|
tws_teardown_intr(struct tws_softc *sc)
|
|
|
|
|
{
|
|
|
|
|
int i, error;
|
|
|
|
|
|
|
|
|
|
for(i=0;i<sc->irqs;i++) {
|
|
|
|
|
if (sc->intr_handle[i]) {
|
|
|
|
|
error = bus_teardown_intr(sc->tws_dev,
|
|
|
|
|
sc->irq_res[i], sc->intr_handle[i]);
|
|
|
|
|
sc->intr_handle[i] = NULL;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
return(SUCCESS);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
tws_setup_irq(struct tws_softc *sc)
|
|
|
|
|
{
|
|
|
|
|
int messages;
|
|
|
|
|
u_int16_t cmd;
|
|
|
|
|
|
|
|
|
|
cmd = pci_read_config(sc->tws_dev, PCIR_COMMAND, 2);
|
|
|
|
|
switch(sc->intr_type) {
|
|
|
|
|
case TWS_INTx :
|
|
|
|
|
cmd = cmd & ~0x0400;
|
|
|
|
|
pci_write_config(sc->tws_dev, PCIR_COMMAND, cmd, 2);
|
|
|
|
|
sc->irqs = 1;
|
|
|
|
|
sc->irq_res_id[0] = 0;
|
|
|
|
|
sc->irq_res[0] = bus_alloc_resource_any(sc->tws_dev, SYS_RES_IRQ,
|
|
|
|
|
&sc->irq_res_id[0], RF_SHAREABLE | RF_ACTIVE);
|
|
|
|
|
if ( ! sc->irq_res[0] )
|
|
|
|
|
return(FAILURE);
|
|
|
|
|
if ( tws_setup_intr(sc, sc->irqs) == FAILURE )
|
|
|
|
|
return(FAILURE);
|
|
|
|
|
device_printf(sc->tws_dev, "Using legacy INTx\n");
|
|
|
|
|
break;
|
|
|
|
|
case TWS_MSI :
|
|
|
|
|
cmd = cmd | 0x0400;
|
|
|
|
|
pci_write_config(sc->tws_dev, PCIR_COMMAND, cmd, 2);
|
|
|
|
|
sc->irqs = 1;
|
|
|
|
|
sc->irq_res_id[0] = 1;
|
|
|
|
|
messages = 1;
|
|
|
|
|
if (pci_alloc_msi(sc->tws_dev, &messages) != 0 ) {
|
|
|
|
|
TWS_TRACE(sc, "pci alloc msi fail", 0, messages);
|
|
|
|
|
return(FAILURE);
|
|
|
|
|
}
|
|
|
|
|
sc->irq_res[0] = bus_alloc_resource_any(sc->tws_dev, SYS_RES_IRQ,
|
|
|
|
|
&sc->irq_res_id[0], RF_SHAREABLE | RF_ACTIVE);
|
|
|
|
|
|
|
|
|
|
if ( !sc->irq_res[0] )
|
|
|
|
|
return(FAILURE);
|
|
|
|
|
if ( tws_setup_intr(sc, sc->irqs) == FAILURE )
|
|
|
|
|
return(FAILURE);
|
|
|
|
|
device_printf(sc->tws_dev, "Using MSI\n");
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return(SUCCESS);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
tws_init(struct tws_softc *sc)
|
|
|
|
|
{
|
|
|
|
|
|
|
|
|
|
u_int32_t max_sg_elements;
|
|
|
|
|
u_int32_t dma_mem_size;
|
|
|
|
|
int error;
|
|
|
|
|
u_int32_t reg;
|
|
|
|
|
|
|
|
|
|
sc->seq_id = 0;
|
|
|
|
|
if ( tws_queue_depth > TWS_MAX_REQS )
|
|
|
|
|
tws_queue_depth = TWS_MAX_REQS;
|
|
|
|
|
if (tws_queue_depth < TWS_RESERVED_REQS+1)
|
|
|
|
|
tws_queue_depth = TWS_RESERVED_REQS+1;
|
|
|
|
|
sc->is64bit = (sizeof(bus_addr_t) == 8) ? true : false;
|
|
|
|
|
max_sg_elements = (sc->is64bit && !tws_use_32bit_sgls) ?
|
|
|
|
|
TWS_MAX_64BIT_SG_ELEMENTS :
|
|
|
|
|
TWS_MAX_32BIT_SG_ELEMENTS;
|
|
|
|
|
dma_mem_size = (sizeof(struct tws_command_packet) * tws_queue_depth) +
|
|
|
|
|
(TWS_SECTOR_SIZE) ;
|
2012-03-12 08:03:51 +00:00
|
|
|
if ( bus_dma_tag_create(bus_get_dma_tag(sc->tws_dev), /* PCI parent */
|
2011-10-04 21:40:25 +00:00
|
|
|
TWS_ALIGNMENT, /* alignment */
|
|
|
|
|
0, /* boundary */
|
|
|
|
|
BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
|
|
|
|
|
BUS_SPACE_MAXADDR, /* highaddr */
|
|
|
|
|
NULL, NULL, /* filter, filterarg */
|
|
|
|
|
BUS_SPACE_MAXSIZE, /* maxsize */
|
|
|
|
|
max_sg_elements, /* numsegs */
|
|
|
|
|
BUS_SPACE_MAXSIZE, /* maxsegsize */
|
|
|
|
|
0, /* flags */
|
|
|
|
|
NULL, NULL, /* lockfunc, lockfuncarg */
|
|
|
|
|
&sc->parent_tag /* tag */
|
|
|
|
|
)) {
|
|
|
|
|
TWS_TRACE_DEBUG(sc, "DMA parent tag Create fail", max_sg_elements,
|
|
|
|
|
sc->is64bit);
|
|
|
|
|
return(ENOMEM);
|
|
|
|
|
}
|
|
|
|
|
/* In bound message frame requires 16byte alignment.
|
|
|
|
|
* Outbound MF's can live with 4byte alignment - for now just
|
|
|
|
|
* use 16 for both.
|
|
|
|
|
*/
|
|
|
|
|
if ( bus_dma_tag_create(sc->parent_tag, /* parent */
|
|
|
|
|
TWS_IN_MF_ALIGNMENT, /* alignment */
|
|
|
|
|
0, /* boundary */
|
|
|
|
|
BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
|
|
|
|
|
BUS_SPACE_MAXADDR, /* highaddr */
|
|
|
|
|
NULL, NULL, /* filter, filterarg */
|
|
|
|
|
dma_mem_size, /* maxsize */
|
|
|
|
|
1, /* numsegs */
|
|
|
|
|
BUS_SPACE_MAXSIZE, /* maxsegsize */
|
|
|
|
|
0, /* flags */
|
|
|
|
|
NULL, NULL, /* lockfunc, lockfuncarg */
|
|
|
|
|
&sc->cmd_tag /* tag */
|
|
|
|
|
)) {
|
|
|
|
|
TWS_TRACE_DEBUG(sc, "DMA cmd tag Create fail", max_sg_elements, sc->is64bit);
|
|
|
|
|
return(ENOMEM);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (bus_dmamem_alloc(sc->cmd_tag, &sc->dma_mem,
|
|
|
|
|
BUS_DMA_NOWAIT, &sc->cmd_map)) {
|
|
|
|
|
TWS_TRACE_DEBUG(sc, "DMA mem alloc fail", max_sg_elements, sc->is64bit);
|
|
|
|
|
return(ENOMEM);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* if bus_dmamem_alloc succeeds then bus_dmamap_load will succeed */
|
|
|
|
|
sc->dma_mem_phys=0;
|
|
|
|
|
error = bus_dmamap_load(sc->cmd_tag, sc->cmd_map, sc->dma_mem,
|
|
|
|
|
dma_mem_size, tws_dmamap_cmds_load_cbfn,
|
|
|
|
|
&sc->dma_mem_phys, 0);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Create a dma tag for data buffers; size will be the maximum
|
|
|
|
|
* possible I/O size (128kB).
|
|
|
|
|
*/
|
|
|
|
|
if (bus_dma_tag_create(sc->parent_tag, /* parent */
|
|
|
|
|
TWS_ALIGNMENT, /* alignment */
|
|
|
|
|
0, /* boundary */
|
|
|
|
|
BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
|
|
|
|
|
BUS_SPACE_MAXADDR, /* highaddr */
|
|
|
|
|
NULL, NULL, /* filter, filterarg */
|
|
|
|
|
TWS_MAX_IO_SIZE, /* maxsize */
|
|
|
|
|
max_sg_elements, /* nsegments */
|
|
|
|
|
TWS_MAX_IO_SIZE, /* maxsegsize */
|
|
|
|
|
BUS_DMA_ALLOCNOW, /* flags */
|
|
|
|
|
busdma_lock_mutex, /* lockfunc */
|
|
|
|
|
&sc->io_lock, /* lockfuncarg */
|
|
|
|
|
&sc->data_tag /* tag */)) {
|
|
|
|
|
TWS_TRACE_DEBUG(sc, "DMA cmd tag Create fail", max_sg_elements, sc->is64bit);
|
|
|
|
|
return(ENOMEM);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
sc->reqs = malloc(sizeof(struct tws_request) * tws_queue_depth, M_TWS,
|
|
|
|
|
M_WAITOK | M_ZERO);
|
|
|
|
|
if ( sc->reqs == NULL ) {
|
|
|
|
|
TWS_TRACE_DEBUG(sc, "malloc failed", 0, sc->is64bit);
|
|
|
|
|
return(ENOMEM);
|
|
|
|
|
}
|
|
|
|
|
sc->sense_bufs = malloc(sizeof(struct tws_sense) * tws_queue_depth, M_TWS,
|
|
|
|
|
M_WAITOK | M_ZERO);
|
|
|
|
|
if ( sc->sense_bufs == NULL ) {
|
|
|
|
|
TWS_TRACE_DEBUG(sc, "sense malloc failed", 0, sc->is64bit);
|
|
|
|
|
return(ENOMEM);
|
|
|
|
|
}
|
|
|
|
|
sc->scan_ccb = malloc(sizeof(union ccb), M_TWS, M_WAITOK | M_ZERO);
|
|
|
|
|
if ( sc->scan_ccb == NULL ) {
|
|
|
|
|
TWS_TRACE_DEBUG(sc, "ccb malloc failed", 0, sc->is64bit);
|
|
|
|
|
return(ENOMEM);
|
|
|
|
|
}
|
2012-10-19 22:07:40 +00:00
|
|
|
if (bus_dmamem_alloc(sc->data_tag, (void **)&sc->ioctl_data_mem,
|
|
|
|
|
(BUS_DMA_NOWAIT | BUS_DMA_ZERO), &sc->ioctl_data_map)) {
|
|
|
|
|
device_printf(sc->tws_dev, "Cannot allocate ioctl data mem\n");
|
|
|
|
|
return(ENOMEM);
|
|
|
|
|
}
|
2011-10-04 21:40:25 +00:00
|
|
|
|
|
|
|
|
if ( !tws_ctlr_ready(sc) )
|
|
|
|
|
if( !tws_ctlr_reset(sc) )
|
|
|
|
|
return(FAILURE);
|
|
|
|
|
|
|
|
|
|
bzero(&sc->stats, sizeof(struct tws_stats));
|
|
|
|
|
tws_init_qs(sc);
|
|
|
|
|
tws_turn_off_interrupts(sc);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* enable pull mode by setting bit1 .
|
|
|
|
|
* setting bit0 to 1 will enable interrupt coalesing
|
|
|
|
|
* will revisit.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#ifdef TWS_PULL_MODE_ENABLE
|
|
|
|
|
|
|
|
|
|
reg = tws_read_reg(sc, TWS_I2O0_CTL, 4);
|
|
|
|
|
TWS_TRACE_DEBUG(sc, "i20 ctl", reg, TWS_I2O0_CTL);
|
|
|
|
|
tws_write_reg(sc, TWS_I2O0_CTL, reg | TWS_BIT1, 4);
|
|
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
TWS_TRACE_DEBUG(sc, "dma_mem_phys", sc->dma_mem_phys, TWS_I2O0_CTL);
|
|
|
|
|
if ( tws_init_reqs(sc, dma_mem_size) == FAILURE )
|
|
|
|
|
return(FAILURE);
|
|
|
|
|
if ( tws_init_aen_q(sc) == FAILURE )
|
|
|
|
|
return(FAILURE);
|
|
|
|
|
|
|
|
|
|
return(SUCCESS);
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
tws_init_aen_q(struct tws_softc *sc)
|
|
|
|
|
{
|
|
|
|
|
sc->aen_q.head=0;
|
|
|
|
|
sc->aen_q.tail=0;
|
|
|
|
|
sc->aen_q.depth=256;
|
|
|
|
|
sc->aen_q.overflow=0;
|
|
|
|
|
sc->aen_q.q = malloc(sizeof(struct tws_event_packet)*sc->aen_q.depth,
|
|
|
|
|
M_TWS, M_WAITOK | M_ZERO);
|
|
|
|
|
if ( ! sc->aen_q.q )
|
|
|
|
|
return(FAILURE);
|
|
|
|
|
return(SUCCESS);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
tws_init_trace_q(struct tws_softc *sc)
|
|
|
|
|
{
|
|
|
|
|
sc->trace_q.head=0;
|
|
|
|
|
sc->trace_q.tail=0;
|
|
|
|
|
sc->trace_q.depth=256;
|
|
|
|
|
sc->trace_q.overflow=0;
|
|
|
|
|
sc->trace_q.q = malloc(sizeof(struct tws_trace_rec)*sc->trace_q.depth,
|
|
|
|
|
M_TWS, M_WAITOK | M_ZERO);
|
|
|
|
|
if ( ! sc->trace_q.q )
|
|
|
|
|
return(FAILURE);
|
|
|
|
|
return(SUCCESS);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
tws_init_reqs(struct tws_softc *sc, u_int32_t dma_mem_size)
|
|
|
|
|
{
|
|
|
|
|
|
|
|
|
|
struct tws_command_packet *cmd_buf;
|
|
|
|
|
cmd_buf = (struct tws_command_packet *)sc->dma_mem;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
bzero(cmd_buf, dma_mem_size);
|
|
|
|
|
TWS_TRACE_DEBUG(sc, "phy cmd", sc->dma_mem_phys, 0);
|
|
|
|
|
mtx_lock(&sc->q_lock);
|
|
|
|
|
for ( i=0; i< tws_queue_depth; i++)
|
|
|
|
|
{
|
|
|
|
|
if (bus_dmamap_create(sc->data_tag, 0, &sc->reqs[i].dma_map)) {
|
|
|
|
|
/* log a ENOMEM failure msg here */
|
2012-01-16 06:00:44 +00:00
|
|
|
mtx_unlock(&sc->q_lock);
|
2011-10-04 21:40:25 +00:00
|
|
|
return(FAILURE);
|
|
|
|
|
}
|
|
|
|
|
sc->reqs[i].cmd_pkt = &cmd_buf[i];
|
|
|
|
|
|
|
|
|
|
sc->sense_bufs[i].hdr = &cmd_buf[i].hdr ;
|
|
|
|
|
sc->sense_bufs[i].hdr_pkt_phy = sc->dma_mem_phys +
|
|
|
|
|
(i * sizeof(struct tws_command_packet));
|
|
|
|
|
|
|
|
|
|
sc->reqs[i].cmd_pkt_phy = sc->dma_mem_phys +
|
|
|
|
|
sizeof(struct tws_command_header) +
|
|
|
|
|
(i * sizeof(struct tws_command_packet));
|
|
|
|
|
sc->reqs[i].request_id = i;
|
|
|
|
|
sc->reqs[i].sc = sc;
|
|
|
|
|
|
|
|
|
|
sc->reqs[i].cmd_pkt->hdr.header_desc.size_header = 128;
|
|
|
|
|
|
|
|
|
|
sc->reqs[i].state = TWS_REQ_STATE_FREE;
|
|
|
|
|
if ( i >= TWS_RESERVED_REQS )
|
|
|
|
|
tws_q_insert_tail(sc, &sc->reqs[i], TWS_FREE_Q);
|
|
|
|
|
}
|
|
|
|
|
mtx_unlock(&sc->q_lock);
|
|
|
|
|
return(SUCCESS);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
tws_dmamap_cmds_load_cbfn(void *arg, bus_dma_segment_t *segs,
|
|
|
|
|
int nseg, int error)
|
|
|
|
|
{
|
|
|
|
|
|
|
|
|
|
/* printf("command load done \n"); */
|
|
|
|
|
|
|
|
|
|
*((bus_addr_t *)arg) = segs[0].ds_addr;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
tws_send_event(struct tws_softc *sc, u_int8_t event)
|
|
|
|
|
{
|
|
|
|
|
mtx_assert(&sc->gen_lock, MA_OWNED);
|
|
|
|
|
TWS_TRACE_DEBUG(sc, "received event ", 0, event);
|
|
|
|
|
switch (event) {
|
|
|
|
|
|
|
|
|
|
case TWS_INIT_START:
|
|
|
|
|
sc->tws_state = TWS_INIT;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case TWS_INIT_COMPLETE:
|
|
|
|
|
if (sc->tws_state != TWS_INIT) {
|
|
|
|
|
device_printf(sc->tws_dev, "invalid state transition %d => TWS_ONLINE\n", sc->tws_state);
|
|
|
|
|
} else {
|
|
|
|
|
sc->tws_state = TWS_ONLINE;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case TWS_RESET_START:
|
|
|
|
|
/* We can transition to reset state from any state except reset*/
|
|
|
|
|
if (sc->tws_state != TWS_RESET) {
|
|
|
|
|
sc->tws_prev_state = sc->tws_state;
|
|
|
|
|
sc->tws_state = TWS_RESET;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case TWS_RESET_COMPLETE:
|
|
|
|
|
if (sc->tws_state != TWS_RESET) {
|
|
|
|
|
device_printf(sc->tws_dev, "invalid state transition %d => %d (previous state)\n", sc->tws_state, sc->tws_prev_state);
|
|
|
|
|
} else {
|
|
|
|
|
sc->tws_state = sc->tws_prev_state;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case TWS_SCAN_FAILURE:
|
|
|
|
|
if (sc->tws_state != TWS_ONLINE) {
|
|
|
|
|
device_printf(sc->tws_dev, "invalid state transition %d => TWS_OFFLINE\n", sc->tws_state);
|
|
|
|
|
} else {
|
|
|
|
|
sc->tws_state = TWS_OFFLINE;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case TWS_UNINIT_START:
|
|
|
|
|
if ((sc->tws_state != TWS_ONLINE) && (sc->tws_state != TWS_OFFLINE)) {
|
|
|
|
|
device_printf(sc->tws_dev, "invalid state transition %d => TWS_UNINIT\n", sc->tws_state);
|
|
|
|
|
} else {
|
|
|
|
|
sc->tws_state = TWS_UNINIT;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
uint8_t
|
|
|
|
|
tws_get_state(struct tws_softc *sc)
|
|
|
|
|
{
|
|
|
|
|
|
|
|
|
|
return((u_int8_t)sc->tws_state);
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Called during system shutdown after sync. */
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
tws_shutdown(device_t dev)
|
|
|
|
|
{
|
|
|
|
|
|
|
|
|
|
struct tws_softc *sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
|
|
TWS_TRACE_DEBUG(sc, "entry", 0, 0);
|
|
|
|
|
|
|
|
|
|
tws_turn_off_interrupts(sc);
|
|
|
|
|
tws_init_connect(sc, 1);
|
|
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Device suspend routine.
|
|
|
|
|
*/
|
|
|
|
|
static int
|
|
|
|
|
tws_suspend(device_t dev)
|
|
|
|
|
{
|
|
|
|
|
struct tws_softc *sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
|
|
if ( sc )
|
|
|
|
|
TWS_TRACE_DEBUG(sc, "entry", 0, 0);
|
|
|
|
|
return (0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Device resume routine.
|
|
|
|
|
*/
|
|
|
|
|
static int
|
|
|
|
|
tws_resume(device_t dev)
|
|
|
|
|
{
|
|
|
|
|
|
|
|
|
|
struct tws_softc *sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
|
|
if ( sc )
|
|
|
|
|
TWS_TRACE_DEBUG(sc, "entry", 0, 0);
|
|
|
|
|
return (0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
struct tws_request *
|
|
|
|
|
tws_get_request(struct tws_softc *sc, u_int16_t type)
|
|
|
|
|
{
|
|
|
|
|
struct mtx *my_mutex = ((type == TWS_REQ_TYPE_SCSI_IO) ? &sc->q_lock : &sc->gen_lock);
|
|
|
|
|
struct tws_request *r = NULL;
|
|
|
|
|
|
|
|
|
|
mtx_lock(my_mutex);
|
|
|
|
|
|
|
|
|
|
if (type == TWS_REQ_TYPE_SCSI_IO) {
|
|
|
|
|
r = tws_q_remove_head(sc, TWS_FREE_Q);
|
|
|
|
|
} else {
|
|
|
|
|
if ( sc->reqs[type].state == TWS_REQ_STATE_FREE ) {
|
|
|
|
|
r = &sc->reqs[type];
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if ( r ) {
|
|
|
|
|
bzero(&r->cmd_pkt->cmd, sizeof(struct tws_command_apache));
|
|
|
|
|
r->data = NULL;
|
|
|
|
|
r->length = 0;
|
|
|
|
|
r->type = type;
|
|
|
|
|
r->flags = TWS_DIR_UNKNOWN;
|
|
|
|
|
r->error_code = TWS_REQ_RET_INVALID;
|
|
|
|
|
r->cb = NULL;
|
|
|
|
|
r->ccb_ptr = NULL;
|
|
|
|
|
r->thandle.callout = NULL;
|
|
|
|
|
r->next = r->prev = NULL;
|
|
|
|
|
|
|
|
|
|
r->state = ((type == TWS_REQ_TYPE_SCSI_IO) ? TWS_REQ_STATE_TRAN : TWS_REQ_STATE_BUSY);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
mtx_unlock(my_mutex);
|
|
|
|
|
|
|
|
|
|
return(r);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
tws_release_request(struct tws_request *req)
|
|
|
|
|
{
|
|
|
|
|
|
|
|
|
|
struct tws_softc *sc = req->sc;
|
|
|
|
|
|
|
|
|
|
TWS_TRACE_DEBUG(sc, "entry", sc, 0);
|
|
|
|
|
mtx_lock(&sc->q_lock);
|
|
|
|
|
tws_q_insert_tail(sc, req, TWS_FREE_Q);
|
|
|
|
|
mtx_unlock(&sc->q_lock);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static device_method_t tws_methods[] = {
|
|
|
|
|
/* Device interface */
|
|
|
|
|
DEVMETHOD(device_probe, tws_probe),
|
|
|
|
|
DEVMETHOD(device_attach, tws_attach),
|
|
|
|
|
DEVMETHOD(device_detach, tws_detach),
|
|
|
|
|
DEVMETHOD(device_shutdown, tws_shutdown),
|
|
|
|
|
DEVMETHOD(device_suspend, tws_suspend),
|
|
|
|
|
DEVMETHOD(device_resume, tws_resume),
|
|
|
|
|
|
2011-11-22 21:28:20 +00:00
|
|
|
DEVMETHOD_END
|
2011-10-04 21:40:25 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static driver_t tws_driver = {
|
|
|
|
|
"tws",
|
|
|
|
|
tws_methods,
|
|
|
|
|
sizeof(struct tws_softc)
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static devclass_t tws_devclass;
|
|
|
|
|
|
|
|
|
|
/* DEFINE_CLASS_0(tws, tws_driver, tws_methods, sizeof(struct tws_softc)); */
|
|
|
|
|
DRIVER_MODULE(tws, pci, tws_driver, tws_devclass, 0, 0);
|
|
|
|
|
MODULE_DEPEND(tws, cam, 1, 1, 1);
|
|
|
|
|
MODULE_DEPEND(tws, pci, 1, 1, 1);
|
|
|
|
|
|
|
|
|
|
TUNABLE_INT("hw.tws.queue_depth", &tws_queue_depth);
|
|
|
|
|
TUNABLE_INT("hw.tws.enable_msi", &tws_enable_msi);
|
