178 lines
5.4 KiB
C
178 lines
5.4 KiB
C
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/*-
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* Copyright (c) 2006 Kip Macy
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_HV_API_H
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#define _MACHINE_HV_API_H
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typedef uint64_t devhandle_t;
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typedef uint64_t pci_device_t;
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typedef uint32_t pci_config_offset_t;
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typedef uint8_t pci_config_size_t;
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/*
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* Section 10 Domain Services
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*/
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extern uint64_t hv_mach_desc(uint64_t buffer_ra, uint64_t *buffer_sizep);
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extern uint64_t hv_mach_watchdog(uint64_t timeout, uint64_t *time_remaining);
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/*
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* Section 11 CPU Services
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*/
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/*
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* Section 12 MMU Services
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*/
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/*
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* TSB description structure for MMU_TSB_CTX0 and MMU_TSB_CTXNON0.
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*/
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typedef struct hv_tsb_info {
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uint16_t hti_idxpgsz; /* page size used for index shift in TSB */
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uint16_t hti_assoc; /* associativity of TSB */
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uint32_t hti_ntte; /* size of TSB in TTEs */
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uint32_t hti_ctx_index; /* context index */
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uint32_t hti_pgszs; /* page size bitmasx */
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uint64_t hti_ra; /* real address of TSB base */
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uint64_t hti_rsvd; /* reserved */
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} hv_tsb_info_t;
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extern uint64_t hv_tsb_ctx0(uint64_t, uint64_t);
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extern uint64_t hv_tsb_ctxnon0(uint64_t, uint64_t);
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/*
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* Section 13 Cache and Memory Services
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*/
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/*
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* Section 14 Device Interrupt Services
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*/
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/*
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* Section 15 Time of Day Services
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*/
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extern uint64_t hv_tod_get(uint64_t *seconds);
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extern uint64_t hv_tod_set(uint64_t);
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/*
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* Section 16 Console Services
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*/
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extern int64_t hv_cons_putchar(uint8_t);
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extern int64_t hv_cons_getchar(uint8_t *);
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extern int64_t hv_cons_write(uint64_t buf_raddr, uint64_t size, uint64_t *nwritten);
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extern int64_t hv_cons_read(uint64_t buf_raddr, uint64_t size, uint64_t *nread);
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extern void hv_cnputs(char *);
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/*
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* Section 17 Core Dump Services
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*/
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extern uint64_t hv_dump_buf_update(uint64_t, uint64_t, uint64_t *);
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/*
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* Section 18 Trap Trace Services
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*/
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typedef struct trap_trace_entry {
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uint8_t tte_type; /* Hypervisor or guest entry. */
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uint8_t tte_hpstat; /* Hyper-privileged state. */
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uint8_t tte_tl; /* Trap level. */
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uint8_t tte_gl; /* Global register level. */
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uint16_t tte_tt; /* Trap type.*/
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uint16_t tte_tag; /* Extended trap identifier. */
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uint64_t tte_tstate; /* Trap state. */
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uint64_t tte_tick; /* Tick. */
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uint64_t tte_tpc; /* Trap PC. */
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uint64_t tte_f1; /* Entry specific. */
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uint64_t tte_f2; /* Entry specific. */
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uint64_t tte_f3; /* Entry specific. */
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uint64_t tte_f4; /* Entry specific. */
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} trap_trace_entry_t;
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extern uint64_t hv_ttrace_buf_info(uint64_t *, uint64_t *);
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extern uint64_t hv_ttrace_buf_conf(uint64_t, uint64_t, uint64_t *);
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extern uint64_t hv_ttrace_enable(uint64_t, uint64_t *);
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extern uint64_t hv_ttrace_freeze(uint64_t, uint64_t *);
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extern uint64_t hv_ttrace_addentry(uint64_t, uint64_t, uint64_t, uint64_t, uint64_t);
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/*
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* Section 19 Logical Domain Channel Services
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*
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*/
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typedef struct ldc_state_info {
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uint64_t lsi_head_offset;
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uint64_t lsi_tail_offset;
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uint64_t lsi_channel_state;
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} ldc_state_info_t;
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#define LDC_CHANNEL_DOWN 0
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#define LDC_CHANNEL_UP 1
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extern uint64_t hvio_ldc_tx_qconf(uint64_t ldc_id, uint64_t base_raddr, uint64_t nentries);
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extern uint64_t hvio_ldc_tx_qinfo(uint64_t ldc_id, uint64_t *base_raddr, uint64_t *nentries);
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extern uint64_t hvio_ldc_tx_get_state(uint64_t ldc_id, ldc_state_info_t *info);
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extern uint64_t hvio_ldc_tx_set_qtail(uint64_t ldc_id, uint64_t tail_offset);
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extern uint64_t hvio_ldc_rx_get_state(uint64_t ldc_id, ldc_state_info_t *info);
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extern uint64_t hvio_ldc_rx_qconf(uint64_t ldc_id, uint64_t base_raddr, uint64_t nentries);
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extern uint64_t hvio_ldc_rx_qinfo(uint64_t ldc_id, uint64_t *base_raddr, uint64_t *nentries);
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extern uint64_t hvio_ldc_rx_set_qhead(uint64_t ldc_id, uint64_t head_offset);
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/*
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* Section 20 PCI I/O Services
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*
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*/
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/*
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* Section 21 MSI Services
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*
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*/
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/*
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* Section 22 UltraSPARC T1 Performance Counters
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*
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*/
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/*
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* Section 23 UltraSPARC T1 MMU Statistics Counters
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*
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*/
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/*
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* Simulator Services
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*/
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extern void hv_magic_trap_on(void);
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extern void hv_magic_trap_off(void);
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extern int hv_sim_read(uint64_t offset, vm_paddr_t buffer_ra, uint64_t size);
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extern int hv_sim_write(uint64_t offset, vm_paddr_t buffer_ra, uint64_t size);
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