2003-11-03 21:34:45 +00:00
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/*-
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* Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* PIC driver for the 8259A Master and Slave PICs in PC/AT machines.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_auto_eoi.h"
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#include "opt_isa.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/interrupt.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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2004-05-30 17:57:46 +00:00
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#include <sys/module.h>
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2003-11-03 21:34:45 +00:00
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#include <sys/mutex.h>
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#include <machine/cpufunc.h>
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#include <machine/frame.h>
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#include <machine/intr_machdep.h>
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#include <machine/md_var.h>
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#include <machine/resource.h>
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#include <machine/segments.h>
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2004-01-06 19:07:08 +00:00
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#include <dev/ic/i8259.h>
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2003-11-03 21:34:45 +00:00
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#include <i386/isa/icu.h>
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2003-11-04 13:13:04 +00:00
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#ifdef PC98
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2005-05-10 12:02:18 +00:00
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#include <pc98/cbus/cbus.h>
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2003-11-04 13:13:04 +00:00
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#else
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2003-11-03 21:34:45 +00:00
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#include <i386/isa/isa.h>
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2003-11-04 13:13:04 +00:00
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#endif
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2003-11-03 21:34:45 +00:00
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#include <isa/isavar.h>
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#define MASTER 0
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#define SLAVE 1
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2004-05-11 20:23:24 +00:00
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/*
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* PC-98 machines wire the slave 8259A to pin 7 on the master PIC, and
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* PC-AT machines wire the slave PIC to pin 2 on the master PIC.
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*/
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#ifdef PC98
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#define ICU_SLAVEID 7
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#else
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#define ICU_SLAVEID 2
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#endif
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2004-01-06 19:07:08 +00:00
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/*
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* Determine the base master and slave modes not including auto EOI support.
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* All machines that FreeBSD supports use 8086 mode.
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*/
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2003-11-03 21:34:45 +00:00
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#ifdef PC98
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2004-01-06 19:07:08 +00:00
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/*
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* PC-98 machines do not support auto EOI on the second PIC. Also, it
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* seems that PC-98 machine PICs use buffered mode, and the master PIC
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* uses special fully nested mode.
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*/
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#define BASE_MASTER_MODE (ICW4_SFNM | ICW4_BUF | ICW4_MS | ICW4_8086)
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#define BASE_SLAVE_MODE (ICW4_BUF | ICW4_8086)
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2003-11-03 21:34:45 +00:00
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#else
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2004-01-06 19:07:08 +00:00
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#define BASE_MASTER_MODE ICW4_8086
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#define BASE_SLAVE_MODE ICW4_8086
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2003-11-03 21:34:45 +00:00
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#endif
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2004-01-06 19:07:08 +00:00
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/* Enable automatic EOI if requested. */
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2003-11-03 21:34:45 +00:00
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#ifdef AUTO_EOI_1
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2004-01-06 19:07:08 +00:00
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#define MASTER_MODE (BASE_MASTER_MODE | ICW4_AEOI)
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2003-11-03 21:34:45 +00:00
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#else
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2004-01-06 19:07:08 +00:00
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#define MASTER_MODE BASE_MASTER_MODE
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2003-11-03 21:34:45 +00:00
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#endif
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#ifdef AUTO_EOI_2
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2004-01-06 19:07:08 +00:00
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#define SLAVE_MODE (BASE_SLAVE_MODE | ICW4_AEOI)
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2003-11-03 21:34:45 +00:00
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#else
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2004-01-06 19:07:08 +00:00
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#define SLAVE_MODE BASE_SLAVE_MODE
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2003-11-03 21:34:45 +00:00
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#endif
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2004-05-11 20:23:24 +00:00
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#define IRQ_MASK(irq) (1 << (irq))
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#define IMEN_MASK(ai) (IRQ_MASK((ai)->at_irq))
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2004-05-03 14:52:41 +00:00
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#define NUM_ISA_IRQS 16
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2003-11-03 21:34:45 +00:00
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static void atpic_init(void *dummy);
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unsigned int imen; /* XXX */
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inthand_t
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IDTVEC(atpic_intr0), IDTVEC(atpic_intr1), IDTVEC(atpic_intr2),
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IDTVEC(atpic_intr3), IDTVEC(atpic_intr4), IDTVEC(atpic_intr5),
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IDTVEC(atpic_intr6), IDTVEC(atpic_intr7), IDTVEC(atpic_intr8),
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IDTVEC(atpic_intr9), IDTVEC(atpic_intr10), IDTVEC(atpic_intr11),
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IDTVEC(atpic_intr12), IDTVEC(atpic_intr13), IDTVEC(atpic_intr14),
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IDTVEC(atpic_intr15);
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#define IRQ(ap, ai) ((ap)->at_irqbase + (ai)->at_irq)
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- Add a member to the atpic interrupt source structures to indicate if the
IRQ is edge triggered or level triggered. For ISA interrupts, we assume
that edge triggered interrupts are always active high and that level
triggered interrupts are always active low.
- Don't disable an edge triggered interrupt in the PIC. This avoids
outb instructions to the actual PIC for traditional ISA IRQs such as
IRQ 1, 6, 14, and 15. (Fast interrupts such as IRQs 0 and 8 don't mask
their source, so this doesn't change anything for them.)
- For MCA systems we assume that all interrupts are level triggered and
thus need masking. Otherwise, we probe the ELCR. If it exists we trust
what it tells us regarding which interrupts are level triggered. If it
does not exist, we assume that IRQs 0, 1, 2, and 8 are edge triggered
and that all other IRQs are level triggered and need masking.
- Instruct the ELCR mini-driver to restore its saved state during resume.
2004-05-04 20:12:52 +00:00
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#define ATPIC(io, base, eoi, imenptr) \
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2003-11-03 21:34:45 +00:00
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{ { atpic_enable_source, atpic_disable_source, (eoi), \
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atpic_enable_intr, atpic_vector, atpic_source_pending, NULL, \
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Rework how we wire up interrupt sources to CPUs:
- Throw out all of the logical APIC ID stuff. The Intel docs are somewhat
ambiguous, but it seems that the "flat" cluster model we are currently
using is only supported on Pentium and P6 family CPUs. The other
"hierarchy" cluster model that is supported on all Intel CPUs with
local APICs is severely underdocumented. For example, it's not clear
if the OS needs to glean the topology of the APIC hierarchy from
somewhere (neither ACPI nor MP Table include it) and setup the logical
clusters based on the physical hierarchy or not. Not only that, but on
certain Intel chipsets, even though there were 4 CPUs in a logical
cluster, all the interrupts were only sent to one CPU anyway.
- We now bind interrupts to individual CPUs using physical addressing via
the local APIC IDs. This code has also moved out of the ioapic PIC
driver and into the common interrupt source code so that it can be
shared with MSI interrupt sources since MSI is addressed to APICs the
same way that I/O APIC pins are.
- Interrupt source classes grow a new method pic_assign_cpu() to bind an
interrupt source to a specific local APIC ID.
- The SMP code now tells the interrupt code which CPUs are avaiable to
handle interrupts in a simpler and more intuitive manner. For one thing,
it means we could now choose to not route interrupts to HT cores if we
wanted to (this code is currently in place in fact, but under an #if 0
for now).
- For now we simply do static round-robin of IRQs to CPUs when the first
interrupt handler just as before, with the change that IRQs are now
bound to individual CPUs rather than groups of up to 4 CPUs.
- Because the IRQ to CPU mapping has now been moved up a layer, it would
be easier to manage this mapping from higher levels. For example, we
could allow drivers to specify a CPU affinity map for their interrupts,
or we could allow a userland tool to bind IRQs to specific CPUs.
The MFC is tentative, but I want to see if this fixes problems some folks
had with UP APIC kernels on 6.0 on SMP machines (an SMP kernel would work
fine, but a UP APIC kernel (such as GENERIC in RELENG_6) would lose
interrupts).
MFC after: 1 week
2006-02-28 22:24:55 +00:00
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atpic_resume, atpic_config_intr, atpic_assign_cpu }, (io), \
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(base), IDT_IO_INTS + (base), (imenptr) }
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2003-11-03 21:34:45 +00:00
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#define INTSRC(irq) \
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- Add a member to the atpic interrupt source structures to indicate if the
IRQ is edge triggered or level triggered. For ISA interrupts, we assume
that edge triggered interrupts are always active high and that level
triggered interrupts are always active low.
- Don't disable an edge triggered interrupt in the PIC. This avoids
outb instructions to the actual PIC for traditional ISA IRQs such as
IRQ 1, 6, 14, and 15. (Fast interrupts such as IRQs 0 and 8 don't mask
their source, so this doesn't change anything for them.)
- For MCA systems we assume that all interrupts are level triggered and
thus need masking. Otherwise, we probe the ELCR. If it exists we trust
what it tells us regarding which interrupts are level triggered. If it
does not exist, we assume that IRQs 0, 1, 2, and 8 are edge triggered
and that all other IRQs are level triggered and need masking.
- Instruct the ELCR mini-driver to restore its saved state during resume.
2004-05-04 20:12:52 +00:00
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{ { &atpics[(irq) / 8].at_pic }, IDTVEC(atpic_intr ## irq ), \
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(irq) % 8 }
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2003-11-03 21:34:45 +00:00
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struct atpic {
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struct pic at_pic;
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int at_ioaddr;
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int at_irqbase;
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uint8_t at_intbase;
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uint8_t *at_imen;
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};
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struct atpic_intsrc {
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struct intsrc at_intsrc;
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inthand_t *at_intr;
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- Add a member to the atpic interrupt source structures to indicate if the
IRQ is edge triggered or level triggered. For ISA interrupts, we assume
that edge triggered interrupts are always active high and that level
triggered interrupts are always active low.
- Don't disable an edge triggered interrupt in the PIC. This avoids
outb instructions to the actual PIC for traditional ISA IRQs such as
IRQ 1, 6, 14, and 15. (Fast interrupts such as IRQs 0 and 8 don't mask
their source, so this doesn't change anything for them.)
- For MCA systems we assume that all interrupts are level triggered and
thus need masking. Otherwise, we probe the ELCR. If it exists we trust
what it tells us regarding which interrupts are level triggered. If it
does not exist, we assume that IRQs 0, 1, 2, and 8 are edge triggered
and that all other IRQs are level triggered and need masking.
- Instruct the ELCR mini-driver to restore its saved state during resume.
2004-05-04 20:12:52 +00:00
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int at_irq; /* Relative to PIC base. */
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enum intr_trigger at_trigger;
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2003-11-19 15:38:56 +00:00
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u_long at_count;
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u_long at_straycount;
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2003-11-03 21:34:45 +00:00
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};
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static void atpic_enable_source(struct intsrc *isrc);
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2004-08-02 15:31:10 +00:00
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static void atpic_disable_source(struct intsrc *isrc, int eoi);
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2003-11-03 21:34:45 +00:00
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static void atpic_eoi_master(struct intsrc *isrc);
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static void atpic_eoi_slave(struct intsrc *isrc);
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static void atpic_enable_intr(struct intsrc *isrc);
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static int atpic_vector(struct intsrc *isrc);
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static void atpic_resume(struct intsrc *isrc);
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static int atpic_source_pending(struct intsrc *isrc);
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2004-05-04 21:02:56 +00:00
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static int atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
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enum intr_polarity pol);
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Rework how we wire up interrupt sources to CPUs:
- Throw out all of the logical APIC ID stuff. The Intel docs are somewhat
ambiguous, but it seems that the "flat" cluster model we are currently
using is only supported on Pentium and P6 family CPUs. The other
"hierarchy" cluster model that is supported on all Intel CPUs with
local APICs is severely underdocumented. For example, it's not clear
if the OS needs to glean the topology of the APIC hierarchy from
somewhere (neither ACPI nor MP Table include it) and setup the logical
clusters based on the physical hierarchy or not. Not only that, but on
certain Intel chipsets, even though there were 4 CPUs in a logical
cluster, all the interrupts were only sent to one CPU anyway.
- We now bind interrupts to individual CPUs using physical addressing via
the local APIC IDs. This code has also moved out of the ioapic PIC
driver and into the common interrupt source code so that it can be
shared with MSI interrupt sources since MSI is addressed to APICs the
same way that I/O APIC pins are.
- Interrupt source classes grow a new method pic_assign_cpu() to bind an
interrupt source to a specific local APIC ID.
- The SMP code now tells the interrupt code which CPUs are avaiable to
handle interrupts in a simpler and more intuitive manner. For one thing,
it means we could now choose to not route interrupts to HT cores if we
wanted to (this code is currently in place in fact, but under an #if 0
for now).
- For now we simply do static round-robin of IRQs to CPUs when the first
interrupt handler just as before, with the change that IRQs are now
bound to individual CPUs rather than groups of up to 4 CPUs.
- Because the IRQ to CPU mapping has now been moved up a layer, it would
be easier to manage this mapping from higher levels. For example, we
could allow drivers to specify a CPU affinity map for their interrupts,
or we could allow a userland tool to bind IRQs to specific CPUs.
The MFC is tentative, but I want to see if this fixes problems some folks
had with UP APIC kernels on 6.0 on SMP machines (an SMP kernel would work
fine, but a UP APIC kernel (such as GENERIC in RELENG_6) would lose
interrupts).
MFC after: 1 week
2006-02-28 22:24:55 +00:00
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static void atpic_assign_cpu(struct intsrc *isrc, u_int apic_id);
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2003-11-03 21:34:45 +00:00
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static void i8259_init(struct atpic *pic, int slave);
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static struct atpic atpics[] = {
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ATPIC(IO_ICU1, 0, atpic_eoi_master, (uint8_t *)&imen),
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ATPIC(IO_ICU2, 8, atpic_eoi_slave, ((uint8_t *)&imen) + 1)
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};
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static struct atpic_intsrc atintrs[] = {
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INTSRC(0),
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INTSRC(1),
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INTSRC(2),
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INTSRC(3),
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INTSRC(4),
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INTSRC(5),
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INTSRC(6),
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INTSRC(7),
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INTSRC(8),
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INTSRC(9),
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INTSRC(10),
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INTSRC(11),
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INTSRC(12),
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INTSRC(13),
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INTSRC(14),
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INTSRC(15),
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};
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2004-05-10 18:33:52 +00:00
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CTASSERT(sizeof(atintrs) / sizeof(atintrs[0]) == NUM_ISA_IRQS);
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2004-05-03 14:52:41 +00:00
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2004-08-02 15:31:10 +00:00
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static __inline void
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_atpic_eoi_master(struct intsrc *isrc)
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{
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KASSERT(isrc->is_pic == &atpics[MASTER].at_pic,
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("%s: mismatched pic", __func__));
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#ifndef AUTO_EOI_1
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outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
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#endif
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}
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/*
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* The data sheet says no auto-EOI on slave, but it sometimes works.
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* So, if AUTO_EOI_2 is enabled, we use it.
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*/
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static __inline void
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_atpic_eoi_slave(struct intsrc *isrc)
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{
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KASSERT(isrc->is_pic == &atpics[SLAVE].at_pic,
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("%s: mismatched pic", __func__));
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#ifndef AUTO_EOI_2
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|
|
outb(atpics[SLAVE].at_ioaddr, OCW2_EOI);
|
|
|
|
|
#ifndef AUTO_EOI_1
|
|
|
|
|
outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
|
|
|
|
|
#endif
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
2003-11-03 21:34:45 +00:00
|
|
|
static void
|
|
|
|
|
atpic_enable_source(struct intsrc *isrc)
|
|
|
|
|
{
|
|
|
|
|
struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
|
|
|
|
|
struct atpic *ap = (struct atpic *)isrc->is_pic;
|
|
|
|
|
|
|
|
|
|
mtx_lock_spin(&icu_lock);
|
2004-05-03 14:52:41 +00:00
|
|
|
if (*ap->at_imen & IMEN_MASK(ai)) {
|
|
|
|
|
*ap->at_imen &= ~IMEN_MASK(ai);
|
|
|
|
|
outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen);
|
|
|
|
|
}
|
2003-11-03 21:34:45 +00:00
|
|
|
mtx_unlock_spin(&icu_lock);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2004-08-02 15:31:10 +00:00
|
|
|
atpic_disable_source(struct intsrc *isrc, int eoi)
|
2003-11-03 21:34:45 +00:00
|
|
|
{
|
|
|
|
|
struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
|
|
|
|
|
struct atpic *ap = (struct atpic *)isrc->is_pic;
|
|
|
|
|
|
|
|
|
|
mtx_lock_spin(&icu_lock);
|
2004-08-02 15:31:10 +00:00
|
|
|
if (ai->at_trigger != INTR_TRIGGER_EDGE) {
|
|
|
|
|
*ap->at_imen |= IMEN_MASK(ai);
|
|
|
|
|
outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Take care to call these functions directly instead of through
|
|
|
|
|
* a function pointer. All of the referenced variables should
|
|
|
|
|
* still be hot in the cache.
|
|
|
|
|
*/
|
|
|
|
|
if (eoi == PIC_EOI) {
|
|
|
|
|
if (isrc->is_pic == &atpics[MASTER].at_pic)
|
|
|
|
|
_atpic_eoi_master(isrc);
|
|
|
|
|
else
|
|
|
|
|
_atpic_eoi_slave(isrc);
|
|
|
|
|
}
|
|
|
|
|
|
2003-11-03 21:34:45 +00:00
|
|
|
mtx_unlock_spin(&icu_lock);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
atpic_eoi_master(struct intsrc *isrc)
|
|
|
|
|
{
|
|
|
|
|
#ifndef AUTO_EOI_1
|
|
|
|
|
mtx_lock_spin(&icu_lock);
|
2004-08-02 15:31:10 +00:00
|
|
|
_atpic_eoi_master(isrc);
|
2003-11-03 21:34:45 +00:00
|
|
|
mtx_unlock_spin(&icu_lock);
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
atpic_eoi_slave(struct intsrc *isrc)
|
|
|
|
|
{
|
|
|
|
|
#ifndef AUTO_EOI_2
|
|
|
|
|
mtx_lock_spin(&icu_lock);
|
2004-08-02 15:31:10 +00:00
|
|
|
_atpic_eoi_slave(isrc);
|
2003-11-03 21:34:45 +00:00
|
|
|
mtx_unlock_spin(&icu_lock);
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
atpic_enable_intr(struct intsrc *isrc)
|
|
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
atpic_vector(struct intsrc *isrc)
|
|
|
|
|
{
|
|
|
|
|
struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
|
|
|
|
|
struct atpic *ap = (struct atpic *)isrc->is_pic;
|
|
|
|
|
|
|
|
|
|
return (IRQ(ap, ai));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
atpic_source_pending(struct intsrc *isrc)
|
|
|
|
|
{
|
|
|
|
|
struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
|
|
|
|
|
struct atpic *ap = (struct atpic *)isrc->is_pic;
|
|
|
|
|
|
2004-05-03 14:52:41 +00:00
|
|
|
return (inb(ap->at_ioaddr) & IMEN_MASK(ai));
|
2003-11-03 21:34:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
atpic_resume(struct intsrc *isrc)
|
|
|
|
|
{
|
|
|
|
|
struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
|
|
|
|
|
struct atpic *ap = (struct atpic *)isrc->is_pic;
|
|
|
|
|
|
- Add a member to the atpic interrupt source structures to indicate if the
IRQ is edge triggered or level triggered. For ISA interrupts, we assume
that edge triggered interrupts are always active high and that level
triggered interrupts are always active low.
- Don't disable an edge triggered interrupt in the PIC. This avoids
outb instructions to the actual PIC for traditional ISA IRQs such as
IRQ 1, 6, 14, and 15. (Fast interrupts such as IRQs 0 and 8 don't mask
their source, so this doesn't change anything for them.)
- For MCA systems we assume that all interrupts are level triggered and
thus need masking. Otherwise, we probe the ELCR. If it exists we trust
what it tells us regarding which interrupts are level triggered. If it
does not exist, we assume that IRQs 0, 1, 2, and 8 are edge triggered
and that all other IRQs are level triggered and need masking.
- Instruct the ELCR mini-driver to restore its saved state during resume.
2004-05-04 20:12:52 +00:00
|
|
|
if (ai->at_irq == 0) {
|
2003-11-03 21:34:45 +00:00
|
|
|
i8259_init(ap, ap == &atpics[SLAVE]);
|
2004-05-06 13:48:34 +00:00
|
|
|
#ifndef PC98
|
2005-01-18 20:24:47 +00:00
|
|
|
if (ap == &atpics[SLAVE] && elcr_found)
|
- Add a member to the atpic interrupt source structures to indicate if the
IRQ is edge triggered or level triggered. For ISA interrupts, we assume
that edge triggered interrupts are always active high and that level
triggered interrupts are always active low.
- Don't disable an edge triggered interrupt in the PIC. This avoids
outb instructions to the actual PIC for traditional ISA IRQs such as
IRQ 1, 6, 14, and 15. (Fast interrupts such as IRQs 0 and 8 don't mask
their source, so this doesn't change anything for them.)
- For MCA systems we assume that all interrupts are level triggered and
thus need masking. Otherwise, we probe the ELCR. If it exists we trust
what it tells us regarding which interrupts are level triggered. If it
does not exist, we assume that IRQs 0, 1, 2, and 8 are edge triggered
and that all other IRQs are level triggered and need masking.
- Instruct the ELCR mini-driver to restore its saved state during resume.
2004-05-04 20:12:52 +00:00
|
|
|
elcr_resume();
|
2004-05-06 13:48:34 +00:00
|
|
|
#endif
|
- Add a member to the atpic interrupt source structures to indicate if the
IRQ is edge triggered or level triggered. For ISA interrupts, we assume
that edge triggered interrupts are always active high and that level
triggered interrupts are always active low.
- Don't disable an edge triggered interrupt in the PIC. This avoids
outb instructions to the actual PIC for traditional ISA IRQs such as
IRQ 1, 6, 14, and 15. (Fast interrupts such as IRQs 0 and 8 don't mask
their source, so this doesn't change anything for them.)
- For MCA systems we assume that all interrupts are level triggered and
thus need masking. Otherwise, we probe the ELCR. If it exists we trust
what it tells us regarding which interrupts are level triggered. If it
does not exist, we assume that IRQs 0, 1, 2, and 8 are edge triggered
and that all other IRQs are level triggered and need masking.
- Instruct the ELCR mini-driver to restore its saved state during resume.
2004-05-04 20:12:52 +00:00
|
|
|
}
|
2003-11-03 21:34:45 +00:00
|
|
|
}
|
|
|
|
|
|
2004-05-04 21:02:56 +00:00
|
|
|
static int
|
|
|
|
|
atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
|
|
|
|
|
enum intr_polarity pol)
|
|
|
|
|
{
|
|
|
|
|
struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
|
|
|
|
|
u_int vector;
|
|
|
|
|
|
|
|
|
|
/* Map conforming values to edge/hi and sanity check the values. */
|
|
|
|
|
if (trig == INTR_TRIGGER_CONFORM)
|
|
|
|
|
trig = INTR_TRIGGER_EDGE;
|
|
|
|
|
if (pol == INTR_POLARITY_CONFORM)
|
|
|
|
|
pol = INTR_POLARITY_HIGH;
|
|
|
|
|
vector = atpic_vector(isrc);
|
|
|
|
|
if ((trig == INTR_TRIGGER_EDGE && pol == INTR_POLARITY_LOW) ||
|
|
|
|
|
(trig == INTR_TRIGGER_LEVEL && pol == INTR_POLARITY_HIGH)) {
|
|
|
|
|
printf(
|
|
|
|
|
"atpic: Mismatched config for IRQ%u: trigger %s, polarity %s\n",
|
|
|
|
|
vector, trig == INTR_TRIGGER_EDGE ? "edge" : "level",
|
|
|
|
|
pol == INTR_POLARITY_HIGH ? "high" : "low");
|
|
|
|
|
return (EINVAL);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* If there is no change, just return. */
|
|
|
|
|
if (ai->at_trigger == trig)
|
|
|
|
|
return (0);
|
|
|
|
|
|
2004-05-06 13:48:34 +00:00
|
|
|
#ifdef PC98
|
|
|
|
|
if ((vector == 0 || vector == 1 || vector == 7 || vector == 8) &&
|
|
|
|
|
trig == INTR_TRIGGER_LEVEL) {
|
|
|
|
|
if (bootverbose)
|
|
|
|
|
printf(
|
|
|
|
|
"atpic: Ignoring invalid level/low configuration for IRQ%u\n",
|
|
|
|
|
vector);
|
|
|
|
|
return (EINVAL);
|
|
|
|
|
}
|
|
|
|
|
return (ENXIO);
|
|
|
|
|
#else
|
2004-05-04 21:02:56 +00:00
|
|
|
/*
|
|
|
|
|
* Certain IRQs can never be level/lo, so don't try to set them
|
|
|
|
|
* that way if asked. At least some ELCR registers ignore setting
|
|
|
|
|
* these bits as well.
|
|
|
|
|
*/
|
|
|
|
|
if ((vector == 0 || vector == 1 || vector == 2 || vector == 13) &&
|
|
|
|
|
trig == INTR_TRIGGER_LEVEL) {
|
|
|
|
|
if (bootverbose)
|
|
|
|
|
printf(
|
|
|
|
|
"atpic: Ignoring invalid level/low configuration for IRQ%u\n",
|
|
|
|
|
vector);
|
|
|
|
|
return (EINVAL);
|
|
|
|
|
}
|
2005-01-18 20:24:47 +00:00
|
|
|
if (!elcr_found) {
|
2004-05-04 21:02:56 +00:00
|
|
|
if (bootverbose)
|
|
|
|
|
printf("atpic: No ELCR to configure IRQ%u as %s\n",
|
|
|
|
|
vector, trig == INTR_TRIGGER_EDGE ? "edge/high" :
|
|
|
|
|
"level/low");
|
|
|
|
|
return (ENXIO);
|
|
|
|
|
}
|
|
|
|
|
if (bootverbose)
|
|
|
|
|
printf("atpic: Programming IRQ%u as %s\n", vector,
|
|
|
|
|
trig == INTR_TRIGGER_EDGE ? "edge/high" : "level/low");
|
|
|
|
|
mtx_lock_spin(&icu_lock);
|
|
|
|
|
elcr_write_trigger(atpic_vector(isrc), trig);
|
|
|
|
|
ai->at_trigger = trig;
|
|
|
|
|
mtx_unlock_spin(&icu_lock);
|
|
|
|
|
return (0);
|
2004-05-06 13:48:34 +00:00
|
|
|
#endif /* PC98 */
|
2004-05-04 21:02:56 +00:00
|
|
|
}
|
|
|
|
|
|
Rework how we wire up interrupt sources to CPUs:
- Throw out all of the logical APIC ID stuff. The Intel docs are somewhat
ambiguous, but it seems that the "flat" cluster model we are currently
using is only supported on Pentium and P6 family CPUs. The other
"hierarchy" cluster model that is supported on all Intel CPUs with
local APICs is severely underdocumented. For example, it's not clear
if the OS needs to glean the topology of the APIC hierarchy from
somewhere (neither ACPI nor MP Table include it) and setup the logical
clusters based on the physical hierarchy or not. Not only that, but on
certain Intel chipsets, even though there were 4 CPUs in a logical
cluster, all the interrupts were only sent to one CPU anyway.
- We now bind interrupts to individual CPUs using physical addressing via
the local APIC IDs. This code has also moved out of the ioapic PIC
driver and into the common interrupt source code so that it can be
shared with MSI interrupt sources since MSI is addressed to APICs the
same way that I/O APIC pins are.
- Interrupt source classes grow a new method pic_assign_cpu() to bind an
interrupt source to a specific local APIC ID.
- The SMP code now tells the interrupt code which CPUs are avaiable to
handle interrupts in a simpler and more intuitive manner. For one thing,
it means we could now choose to not route interrupts to HT cores if we
wanted to (this code is currently in place in fact, but under an #if 0
for now).
- For now we simply do static round-robin of IRQs to CPUs when the first
interrupt handler just as before, with the change that IRQs are now
bound to individual CPUs rather than groups of up to 4 CPUs.
- Because the IRQ to CPU mapping has now been moved up a layer, it would
be easier to manage this mapping from higher levels. For example, we
could allow drivers to specify a CPU affinity map for their interrupts,
or we could allow a userland tool to bind IRQs to specific CPUs.
The MFC is tentative, but I want to see if this fixes problems some folks
had with UP APIC kernels on 6.0 on SMP machines (an SMP kernel would work
fine, but a UP APIC kernel (such as GENERIC in RELENG_6) would lose
interrupts).
MFC after: 1 week
2006-02-28 22:24:55 +00:00
|
|
|
static void
|
|
|
|
|
atpic_assign_cpu(struct intsrc *isrc, u_int apic_id)
|
|
|
|
|
{
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* 8259A's are only used in UP in which case all interrupts always
|
|
|
|
|
* go to the sole CPU and this function shouldn't even be called.
|
|
|
|
|
*/
|
|
|
|
|
panic("%s: bad cookie", __func__);
|
|
|
|
|
}
|
|
|
|
|
|
2003-11-03 21:34:45 +00:00
|
|
|
static void
|
|
|
|
|
i8259_init(struct atpic *pic, int slave)
|
|
|
|
|
{
|
|
|
|
|
int imr_addr;
|
|
|
|
|
|
|
|
|
|
/* Reset the PIC and program with next four bytes. */
|
|
|
|
|
mtx_lock_spin(&icu_lock);
|
|
|
|
|
#ifdef DEV_MCA
|
2003-11-14 19:13:06 +00:00
|
|
|
/* MCA uses level triggered interrupts. */
|
2003-11-03 21:34:45 +00:00
|
|
|
if (MCA_system)
|
2003-11-14 19:13:06 +00:00
|
|
|
outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4 | ICW1_LTIM);
|
2003-11-03 21:34:45 +00:00
|
|
|
else
|
|
|
|
|
#endif
|
2003-11-14 19:13:06 +00:00
|
|
|
outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4);
|
2003-11-03 21:34:45 +00:00
|
|
|
imr_addr = pic->at_ioaddr + ICU_IMR_OFFSET;
|
|
|
|
|
|
|
|
|
|
/* Start vector. */
|
|
|
|
|
outb(imr_addr, pic->at_intbase);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Setup slave links. For the master pic, indicate what line
|
|
|
|
|
* the slave is configured on. For the slave indicate
|
|
|
|
|
* which line on the master we are connected to.
|
|
|
|
|
*/
|
|
|
|
|
if (slave)
|
2004-05-11 20:23:24 +00:00
|
|
|
outb(imr_addr, ICU_SLAVEID);
|
2003-11-03 21:34:45 +00:00
|
|
|
else
|
2004-05-11 20:23:24 +00:00
|
|
|
outb(imr_addr, IRQ_MASK(ICU_SLAVEID));
|
2003-11-03 21:34:45 +00:00
|
|
|
|
|
|
|
|
/* Set mode. */
|
|
|
|
|
if (slave)
|
|
|
|
|
outb(imr_addr, SLAVE_MODE);
|
|
|
|
|
else
|
|
|
|
|
outb(imr_addr, MASTER_MODE);
|
|
|
|
|
|
|
|
|
|
/* Set interrupt enable mask. */
|
|
|
|
|
outb(imr_addr, *pic->at_imen);
|
|
|
|
|
|
|
|
|
|
/* Reset is finished, default to IRR on read. */
|
2003-11-14 19:13:06 +00:00
|
|
|
outb(pic->at_ioaddr, OCW3_SEL | OCW3_RR);
|
2003-11-03 21:34:45 +00:00
|
|
|
|
|
|
|
|
#ifndef PC98
|
2003-11-14 19:13:06 +00:00
|
|
|
/* OCW2_L1 sets priority order to 3-7, 0-2 (com2 first). */
|
2003-11-03 21:34:45 +00:00
|
|
|
if (!slave)
|
2003-11-14 19:13:06 +00:00
|
|
|
outb(pic->at_ioaddr, OCW2_R | OCW2_SL | OCW2_L1);
|
2003-11-03 21:34:45 +00:00
|
|
|
#endif
|
|
|
|
|
mtx_unlock_spin(&icu_lock);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
atpic_startup(void)
|
|
|
|
|
{
|
2003-11-19 15:38:56 +00:00
|
|
|
struct atpic_intsrc *ai;
|
|
|
|
|
int i;
|
2003-11-03 21:34:45 +00:00
|
|
|
|
|
|
|
|
/* Start off with all interrupts disabled. */
|
|
|
|
|
imen = 0xffff;
|
|
|
|
|
i8259_init(&atpics[MASTER], 0);
|
|
|
|
|
i8259_init(&atpics[SLAVE], 1);
|
|
|
|
|
atpic_enable_source((struct intsrc *)&atintrs[ICU_SLAVEID]);
|
2003-11-19 15:38:56 +00:00
|
|
|
|
|
|
|
|
/* Install low-level interrupt handlers for all of our IRQs. */
|
2004-05-03 14:52:41 +00:00
|
|
|
for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
|
2003-11-19 15:38:56 +00:00
|
|
|
if (i == ICU_SLAVEID)
|
|
|
|
|
continue;
|
|
|
|
|
ai->at_intsrc.is_count = &ai->at_count;
|
|
|
|
|
ai->at_intsrc.is_straycount = &ai->at_straycount;
|
|
|
|
|
setidt(((struct atpic *)ai->at_intsrc.is_pic)->at_intbase +
|
|
|
|
|
ai->at_irq, ai->at_intr, SDT_SYS386IGT, SEL_KPL,
|
|
|
|
|
GSEL(GCODE_SEL, SEL_KPL));
|
|
|
|
|
}
|
- Add a member to the atpic interrupt source structures to indicate if the
IRQ is edge triggered or level triggered. For ISA interrupts, we assume
that edge triggered interrupts are always active high and that level
triggered interrupts are always active low.
- Don't disable an edge triggered interrupt in the PIC. This avoids
outb instructions to the actual PIC for traditional ISA IRQs such as
IRQ 1, 6, 14, and 15. (Fast interrupts such as IRQs 0 and 8 don't mask
their source, so this doesn't change anything for them.)
- For MCA systems we assume that all interrupts are level triggered and
thus need masking. Otherwise, we probe the ELCR. If it exists we trust
what it tells us regarding which interrupts are level triggered. If it
does not exist, we assume that IRQs 0, 1, 2, and 8 are edge triggered
and that all other IRQs are level triggered and need masking.
- Instruct the ELCR mini-driver to restore its saved state during resume.
2004-05-04 20:12:52 +00:00
|
|
|
|
|
|
|
|
#ifdef DEV_MCA
|
|
|
|
|
/* For MCA systems, all interrupts are level triggered. */
|
|
|
|
|
if (MCA_system)
|
|
|
|
|
for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
|
|
|
|
|
ai->at_trigger = INTR_TRIGGER_LEVEL;
|
|
|
|
|
else
|
|
|
|
|
#endif
|
|
|
|
|
|
2004-05-06 13:48:34 +00:00
|
|
|
#ifdef PC98
|
|
|
|
|
for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
|
|
|
|
|
switch (i) {
|
|
|
|
|
case 0:
|
|
|
|
|
case 1:
|
|
|
|
|
case 7:
|
|
|
|
|
case 8:
|
|
|
|
|
ai->at_trigger = INTR_TRIGGER_EDGE;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
ai->at_trigger = INTR_TRIGGER_LEVEL;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
#else
|
- Add a member to the atpic interrupt source structures to indicate if the
IRQ is edge triggered or level triggered. For ISA interrupts, we assume
that edge triggered interrupts are always active high and that level
triggered interrupts are always active low.
- Don't disable an edge triggered interrupt in the PIC. This avoids
outb instructions to the actual PIC for traditional ISA IRQs such as
IRQ 1, 6, 14, and 15. (Fast interrupts such as IRQs 0 and 8 don't mask
their source, so this doesn't change anything for them.)
- For MCA systems we assume that all interrupts are level triggered and
thus need masking. Otherwise, we probe the ELCR. If it exists we trust
what it tells us regarding which interrupts are level triggered. If it
does not exist, we assume that IRQs 0, 1, 2, and 8 are edge triggered
and that all other IRQs are level triggered and need masking.
- Instruct the ELCR mini-driver to restore its saved state during resume.
2004-05-04 20:12:52 +00:00
|
|
|
/*
|
|
|
|
|
* Look for an ELCR. If we find one, update the trigger modes.
|
|
|
|
|
* If we don't find one, assume that IRQs 0, 1, 2, and 13 are
|
|
|
|
|
* edge triggered and that everything else is level triggered.
|
|
|
|
|
* We only use the trigger information to reprogram the ELCR if
|
|
|
|
|
* we have one and as an optimization to avoid masking edge
|
|
|
|
|
* triggered interrupts. For the case that we don't have an ELCR,
|
|
|
|
|
* it doesn't hurt to mask an edge triggered interrupt, so we
|
2004-05-10 18:33:52 +00:00
|
|
|
* assume level trigger for any interrupt that we aren't sure is
|
|
|
|
|
* edge triggered.
|
- Add a member to the atpic interrupt source structures to indicate if the
IRQ is edge triggered or level triggered. For ISA interrupts, we assume
that edge triggered interrupts are always active high and that level
triggered interrupts are always active low.
- Don't disable an edge triggered interrupt in the PIC. This avoids
outb instructions to the actual PIC for traditional ISA IRQs such as
IRQ 1, 6, 14, and 15. (Fast interrupts such as IRQs 0 and 8 don't mask
their source, so this doesn't change anything for them.)
- For MCA systems we assume that all interrupts are level triggered and
thus need masking. Otherwise, we probe the ELCR. If it exists we trust
what it tells us regarding which interrupts are level triggered. If it
does not exist, we assume that IRQs 0, 1, 2, and 8 are edge triggered
and that all other IRQs are level triggered and need masking.
- Instruct the ELCR mini-driver to restore its saved state during resume.
2004-05-04 20:12:52 +00:00
|
|
|
*/
|
2005-01-18 20:24:47 +00:00
|
|
|
if (elcr_found) {
|
- Add a member to the atpic interrupt source structures to indicate if the
IRQ is edge triggered or level triggered. For ISA interrupts, we assume
that edge triggered interrupts are always active high and that level
triggered interrupts are always active low.
- Don't disable an edge triggered interrupt in the PIC. This avoids
outb instructions to the actual PIC for traditional ISA IRQs such as
IRQ 1, 6, 14, and 15. (Fast interrupts such as IRQs 0 and 8 don't mask
their source, so this doesn't change anything for them.)
- For MCA systems we assume that all interrupts are level triggered and
thus need masking. Otherwise, we probe the ELCR. If it exists we trust
what it tells us regarding which interrupts are level triggered. If it
does not exist, we assume that IRQs 0, 1, 2, and 8 are edge triggered
and that all other IRQs are level triggered and need masking.
- Instruct the ELCR mini-driver to restore its saved state during resume.
2004-05-04 20:12:52 +00:00
|
|
|
for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
|
|
|
|
|
ai->at_trigger = elcr_read_trigger(i);
|
|
|
|
|
} else {
|
|
|
|
|
for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
|
|
|
|
|
switch (i) {
|
|
|
|
|
case 0:
|
|
|
|
|
case 1:
|
|
|
|
|
case 2:
|
|
|
|
|
case 8:
|
|
|
|
|
case 13:
|
|
|
|
|
ai->at_trigger = INTR_TRIGGER_EDGE;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
ai->at_trigger = INTR_TRIGGER_LEVEL;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
2004-05-06 13:48:34 +00:00
|
|
|
#endif /* PC98 */
|
2003-11-03 21:34:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
atpic_init(void *dummy __unused)
|
|
|
|
|
{
|
2004-05-03 14:52:41 +00:00
|
|
|
struct atpic_intsrc *ai;
|
2003-11-03 21:34:45 +00:00
|
|
|
int i;
|
|
|
|
|
|
2005-12-05 22:09:30 +00:00
|
|
|
/*
|
|
|
|
|
* If any of the ISA IRQs have an interrupt source already, then
|
|
|
|
|
* assume that the APICs are being used and don't register any
|
|
|
|
|
* of our interrupt sources. This makes sure we don't accidentally
|
|
|
|
|
* use mixed mode. The "accidental" use could otherwise occur on
|
|
|
|
|
* machines that route the ACPI SCI interrupt to a different ISA
|
|
|
|
|
* IRQ (at least one machines routes it to IRQ 13) thus disabling
|
|
|
|
|
* that APIC ISA routing and allowing the ATPIC source for that IRQ
|
|
|
|
|
* to leak through. We used to depend on this feature for routing
|
|
|
|
|
* IRQ0 via mixed mode, but now we don't use mixed mode at all.
|
|
|
|
|
*/
|
|
|
|
|
for (i = 0; i < NUM_ISA_IRQS; i++)
|
|
|
|
|
if (intr_lookup_source(i) != NULL)
|
|
|
|
|
return;
|
|
|
|
|
|
2003-11-03 21:34:45 +00:00
|
|
|
/* Loop through all interrupt sources and add them. */
|
2004-05-03 14:52:41 +00:00
|
|
|
for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
|
2003-11-03 21:34:45 +00:00
|
|
|
if (i == ICU_SLAVEID)
|
|
|
|
|
continue;
|
2004-05-03 14:52:41 +00:00
|
|
|
intr_register_source(&ai->at_intsrc);
|
2003-11-03 21:34:45 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
SYSINIT(atpic_init, SI_SUB_INTR, SI_ORDER_SECOND + 1, atpic_init, NULL)
|
|
|
|
|
|
|
|
|
|
void
|
2005-12-05 22:39:09 +00:00
|
|
|
atpic_handle_intr(u_int vector, struct trapframe frame)
|
2003-11-03 21:34:45 +00:00
|
|
|
{
|
|
|
|
|
struct intsrc *isrc;
|
|
|
|
|
|
2005-12-08 18:33:48 +00:00
|
|
|
KASSERT(vector < NUM_ISA_IRQS, ("unknown int %u\n", vector));
|
2005-12-05 22:39:09 +00:00
|
|
|
isrc = &atintrs[vector].at_intsrc;
|
2003-11-19 15:40:23 +00:00
|
|
|
|
|
|
|
|
/*
|
Reorganize the interrupt handling code a bit to make a few things cleaner
and increase flexibility to allow various different approaches to be tried
in the future.
- Split struct ithd up into two pieces. struct intr_event holds the list
of interrupt handlers associated with interrupt sources.
struct intr_thread contains the data relative to an interrupt thread.
Currently we still provide a 1:1 relationship of events to threads
with the exception that events only have an associated thread if there
is at least one threaded interrupt handler attached to the event. This
means that on x86 we no longer have 4 bazillion interrupt threads with
no handlers. It also means that interrupt events with only INTR_FAST
handlers no longer have an associated thread either.
- Renamed struct intrhand to struct intr_handler to follow the struct
intr_foo naming convention. This did require renaming the powerpc
MD struct intr_handler to struct ppc_intr_handler.
- INTR_FAST no longer implies INTR_EXCL on all architectures except for
powerpc. This means that multiple INTR_FAST handlers can attach to the
same interrupt and that INTR_FAST and non-INTR_FAST handlers can attach
to the same interrupt. Sharing INTR_FAST handlers may not always be
desirable, but having sio(4) and uhci(4) fight over an IRQ isn't fun
either. Drivers can always still use INTR_EXCL to ask for an interrupt
exclusively. The way this sharing works is that when an interrupt
comes in, all the INTR_FAST handlers are executed first, and if any
threaded handlers exist, the interrupt thread is scheduled afterwards.
This type of layout also makes it possible to investigate using interrupt
filters ala OS X where the filter determines whether or not its companion
threaded handler should run.
- Aside from the INTR_FAST changes above, the impact on MD interrupt code
is mostly just 's/ithread/intr_event/'.
- A new MI ddb command 'show intrs' walks the list of interrupt events
dumping their state. It also has a '/v' verbose switch which dumps
info about all of the handlers attached to each event.
- We currently don't destroy an interrupt thread when the last threaded
handler is removed because it would suck for things like ppbus(8)'s
braindead behavior. The code is present, though, it is just under
#if 0 for now.
- Move the code to actually execute the threaded handlers for an interrrupt
event into a separate function so that ithread_loop() becomes more
readable. Previously this code was all in the middle of ithread_loop()
and indented halfway across the screen.
- Made struct intr_thread private to kern_intr.c and replaced td_ithd
with a thread private flag TDP_ITHREAD.
- In statclock, check curthread against idlethread directly rather than
curthread's proc against idlethread's proc. (Not really related to intr
changes)
Tested on: alpha, amd64, i386, sparc64
Tested on: arm, ia64 (older version of patch by cognet and marcel)
2005-10-25 19:48:48 +00:00
|
|
|
* If we don't have an event, see if this is a spurious
|
2003-11-19 15:40:23 +00:00
|
|
|
* interrupt.
|
|
|
|
|
*/
|
2005-12-05 22:39:09 +00:00
|
|
|
if (isrc->is_event == NULL && (vector == 7 || vector == 15)) {
|
2003-11-19 15:40:23 +00:00
|
|
|
int port, isr;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Read the ISR register to see if IRQ 7/15 is really
|
|
|
|
|
* pending. Reset read register back to IRR when done.
|
|
|
|
|
*/
|
|
|
|
|
port = ((struct atpic *)isrc->is_pic)->at_ioaddr;
|
|
|
|
|
mtx_lock_spin(&icu_lock);
|
|
|
|
|
outb(port, OCW3_SEL | OCW3_RR | OCW3_RIS);
|
|
|
|
|
isr = inb(port);
|
|
|
|
|
outb(port, OCW3_SEL | OCW3_RR);
|
|
|
|
|
mtx_unlock_spin(&icu_lock);
|
2004-05-11 20:23:24 +00:00
|
|
|
if ((isr & IRQ_MASK(7)) == 0)
|
2003-11-19 15:40:23 +00:00
|
|
|
return;
|
|
|
|
|
}
|
2005-12-05 22:39:09 +00:00
|
|
|
intr_execute_handlers(isrc, &frame);
|
2003-11-03 21:34:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#ifdef DEV_ISA
|
|
|
|
|
/*
|
|
|
|
|
* Bus attachment for the ISA PIC.
|
|
|
|
|
*/
|
|
|
|
|
static struct isa_pnp_id atpic_ids[] = {
|
|
|
|
|
{ 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
|
|
|
|
|
{ 0 }
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
atpic_probe(device_t dev)
|
|
|
|
|
{
|
|
|
|
|
int result;
|
|
|
|
|
|
|
|
|
|
result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids);
|
|
|
|
|
if (result <= 0)
|
|
|
|
|
device_quiet(dev);
|
|
|
|
|
return (result);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* We might be granted IRQ 2, as this is typically consumed by chaining
|
|
|
|
|
* between the two PIC components. If we're using the APIC, however,
|
|
|
|
|
* this may not be the case, and as such we should free the resource.
|
|
|
|
|
* (XXX untested)
|
|
|
|
|
*
|
|
|
|
|
* The generic ISA attachment code will handle allocating any other resources
|
|
|
|
|
* that we don't explicitly claim here.
|
|
|
|
|
*/
|
|
|
|
|
static int
|
|
|
|
|
atpic_attach(device_t dev)
|
|
|
|
|
{
|
|
|
|
|
struct resource *res;
|
|
|
|
|
int rid;
|
|
|
|
|
|
|
|
|
|
/* Try to allocate our IRQ and then free it. */
|
|
|
|
|
rid = 0;
|
2004-03-17 17:50:55 +00:00
|
|
|
res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 0);
|
2003-11-03 21:34:45 +00:00
|
|
|
if (res != NULL)
|
|
|
|
|
bus_release_resource(dev, SYS_RES_IRQ, rid, res);
|
|
|
|
|
return (0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static device_method_t atpic_methods[] = {
|
|
|
|
|
/* Device interface */
|
|
|
|
|
DEVMETHOD(device_probe, atpic_probe),
|
|
|
|
|
DEVMETHOD(device_attach, atpic_attach),
|
|
|
|
|
DEVMETHOD(device_detach, bus_generic_detach),
|
|
|
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
|
|
|
DEVMETHOD(device_suspend, bus_generic_suspend),
|
|
|
|
|
DEVMETHOD(device_resume, bus_generic_resume),
|
|
|
|
|
{ 0, 0 }
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static driver_t atpic_driver = {
|
|
|
|
|
"atpic",
|
|
|
|
|
atpic_methods,
|
|
|
|
|
1, /* no softc */
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static devclass_t atpic_devclass;
|
|
|
|
|
|
|
|
|
|
DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0);
|
2003-11-04 13:13:04 +00:00
|
|
|
#ifndef PC98
|
2003-11-03 21:34:45 +00:00
|
|
|
DRIVER_MODULE(atpic, acpi, atpic_driver, atpic_devclass, 0, 0);
|
2003-11-04 13:13:04 +00:00
|
|
|
#endif
|
2003-11-03 21:34:45 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Return a bitmap of the current interrupt requests. This is 8259-specific
|
|
|
|
|
* and is only suitable for use at probe time.
|
|
|
|
|
*/
|
|
|
|
|
intrmask_t
|
|
|
|
|
isa_irq_pending(void)
|
|
|
|
|
{
|
|
|
|
|
u_char irr1;
|
|
|
|
|
u_char irr2;
|
|
|
|
|
|
|
|
|
|
irr1 = inb(IO_ICU1);
|
|
|
|
|
irr2 = inb(IO_ICU2);
|
|
|
|
|
return ((irr2 << 8) | irr1);
|
|
|
|
|
}
|
|
|
|
|
#endif /* DEV_ISA */
|
