128 lines
4.0 KiB
Markdown
128 lines
4.0 KiB
Markdown
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;; Scheduling description for PowerPC 603 processor.
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;; Copyright (C) 2003 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 2, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING. If not, write to the
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;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
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;; MA 02111-1307, USA.
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(define_automaton "ppc603,ppc603fp")
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(define_cpu_unit "iu_603" "ppc603")
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(define_cpu_unit "fpu_603" "ppc603fp")
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(define_cpu_unit "lsu_603,bpu_603,sru_603" "ppc603")
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;; PPC603/PPC603e 32-bit IU, LSU, FPU, BPU, SRU
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;; Max issue 3 insns/clock cycle (includes 1 branch)
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;; Branches go straight to the BPU. All other insns are handled
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;; by a dispatch unit which can issue a max of 2 insns per cycle.
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;; The PPC603e user's manual recommends that to reduce branch mispredictions,
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;; the insn that sets CR bits should be separated from the branch insn
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;; that evaluates them; separation by more than 9 insns ensures that the CR
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;; bits will be immediately available for execution.
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;; This could be artificially achieved by exaggerating the latency of
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;; compare insns but at the expense of a poorer schedule.
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;; CR insns get executed in the SRU. Not modelled.
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(define_insn_reservation "ppc603-load" 2
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(and (eq_attr "type" "load,load_ext,load_ux,load_u")
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(eq_attr "cpu" "ppc603"))
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"lsu_603")
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(define_insn_reservation "ppc603-store" 1
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(and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
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(eq_attr "cpu" "ppc603"))
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"lsu_603")
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(define_insn_reservation "ppc603-fpload" 2
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(and (eq_attr "type" "fpload,fpload_ux,fpload_u")
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(eq_attr "cpu" "ppc603"))
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"lsu_603")
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(define_insn_reservation "ppc603-integer" 1
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(and (eq_attr "type" "integer,insert_word")
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(eq_attr "cpu" "ppc603"))
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"iu_603")
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; This takes 2 or 3 cycles
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(define_insn_reservation "ppc603-imul" 3
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(and (eq_attr "type" "imul,imul_compare")
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(eq_attr "cpu" "ppc603"))
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"iu_603*2")
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(define_insn_reservation "ppc603-imul2" 2
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(and (eq_attr "type" "imul2,imul3")
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(eq_attr "cpu" "ppc603"))
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"iu_603*2")
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(define_insn_reservation "ppc603-idiv" 37
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(and (eq_attr "type" "idiv")
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(eq_attr "cpu" "ppc603"))
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"iu_603*37")
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(define_insn_reservation "ppc603-compare" 3
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(and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
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(eq_attr "cpu" "ppc603"))
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"iu_603,nothing,bpu_603")
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(define_insn_reservation "ppc603-fpcompare" 3
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(and (eq_attr "type" "fpcompare")
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(eq_attr "cpu" "ppc603"))
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"(fpu_603+iu_603*2),bpu_603")
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(define_insn_reservation "ppc603-fp" 3
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(and (eq_attr "type" "fp")
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(eq_attr "cpu" "ppc603"))
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"fpu_603")
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(define_insn_reservation "ppc603-dmul" 4
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(and (eq_attr "type" "dmul")
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(eq_attr "cpu" "ppc603"))
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"fpu_603*2")
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; Divides are not pipelined
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(define_insn_reservation "ppc603-sdiv" 18
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(and (eq_attr "type" "sdiv")
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(eq_attr "cpu" "ppc603"))
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"fpu_603*18")
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(define_insn_reservation "ppc603-ddiv" 33
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(and (eq_attr "type" "ddiv")
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(eq_attr "cpu" "ppc603"))
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"fpu_603*33")
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(define_insn_reservation "ppc603-crlogical" 2
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(and (eq_attr "type" "cr_logical,delayed_cr,mfcr,mtcr")
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(eq_attr "cpu" "ppc603"))
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"sru_603")
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(define_insn_reservation "ppc603-mtjmpr" 4
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(and (eq_attr "type" "mtjmpr")
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(eq_attr "cpu" "ppc603"))
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"sru_603")
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(define_insn_reservation "ppc603-mfjmpr" 2
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(and (eq_attr "type" "mfjmpr")
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(eq_attr "cpu" "ppc603"))
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"sru_603")
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(define_insn_reservation "ppc603-jmpreg" 1
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(and (eq_attr "type" "jmpreg,branch")
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(eq_attr "cpu" "ppc603"))
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"bpu_603")
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