389 lines
14 KiB
Markdown
389 lines
14 KiB
Markdown
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;; ARM 1020E & ARM 1022E Pipeline Description
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;; Copyright (C) 2005 Free Software Foundation, Inc.
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;; Contributed by Richard Earnshaw (richard.earnshaw@arm.com)
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 2, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but
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;; WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;; General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING. If not, write to the Free
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;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
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;; 02110-1301, USA. */
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;; These descriptions are based on the information contained in the
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;; ARM1020E Technical Reference Manual, Copyright (c) 2003 ARM
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;; Limited.
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;;
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;; This automaton provides a pipeline description for the ARM
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;; 1020E core.
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;;
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;; The model given here assumes that the condition for all conditional
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;; instructions is "true", i.e., that all of the instructions are
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;; actually executed.
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(define_automaton "arm1020e")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Pipelines
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; There are two pipelines:
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;;
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;; - An Arithmetic Logic Unit (ALU) pipeline.
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;;
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;; The ALU pipeline has fetch, issue, decode, execute, memory, and
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;; write stages. We only need to model the execute, memory and write
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;; stages.
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;;
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;; - A Load-Store Unit (LSU) pipeline.
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;;
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;; The LSU pipeline has decode, execute, memory, and write stages.
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;; We only model the execute, memory and write stages.
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(define_cpu_unit "1020a_e,1020a_m,1020a_w" "arm1020e")
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(define_cpu_unit "1020l_e,1020l_m,1020l_w" "arm1020e")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ALU Instructions
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ALU instructions require three cycles to execute, and use the ALU
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;; pipeline in each of the three stages. The results are available
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;; after the execute stage stage has finished.
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;;
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;; If the destination register is the PC, the pipelines are stalled
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;; for several cycles. That case is not modeled here.
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;; ALU operations with no shifted operand
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(define_insn_reservation "1020alu_op" 1
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(and (eq_attr "tune" "arm1020e,arm1022e")
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(eq_attr "type" "alu"))
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"1020a_e,1020a_m,1020a_w")
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;; ALU operations with a shift-by-constant operand
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(define_insn_reservation "1020alu_shift_op" 1
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(and (eq_attr "tune" "arm1020e,arm1022e")
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(eq_attr "type" "alu_shift"))
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"1020a_e,1020a_m,1020a_w")
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;; ALU operations with a shift-by-register operand
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;; These really stall in the decoder, in order to read
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;; the shift value in a second cycle. Pretend we take two cycles in
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;; the execute stage.
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(define_insn_reservation "1020alu_shift_reg_op" 2
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(and (eq_attr "tune" "arm1020e,arm1022e")
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(eq_attr "type" "alu_shift_reg"))
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"1020a_e*2,1020a_m,1020a_w")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Multiplication Instructions
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Multiplication instructions loop in the execute stage until the
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;; instruction has been passed through the multiplier array enough
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;; times.
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;; The result of the "smul" and "smulw" instructions is not available
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;; until after the memory stage.
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(define_insn_reservation "1020mult1" 2
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(and (eq_attr "tune" "arm1020e,arm1022e")
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(eq_attr "insn" "smulxy,smulwy"))
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"1020a_e,1020a_m,1020a_w")
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;; The "smlaxy" and "smlawx" instructions require two iterations through
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;; the execute stage; the result is available immediately following
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;; the execute stage.
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(define_insn_reservation "1020mult2" 2
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(and (eq_attr "tune" "arm1020e,arm1022e")
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(eq_attr "insn" "smlaxy,smlalxy,smlawx"))
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"1020a_e*2,1020a_m,1020a_w")
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;; The "smlalxy", "mul", and "mla" instructions require two iterations
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;; through the execute stage; the result is not available until after
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;; the memory stage.
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(define_insn_reservation "1020mult3" 3
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(and (eq_attr "tune" "arm1020e,arm1022e")
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(eq_attr "insn" "smlalxy,mul,mla"))
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"1020a_e*2,1020a_m,1020a_w")
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;; The "muls" and "mlas" instructions loop in the execute stage for
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;; four iterations in order to set the flags. The value result is
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;; available after three iterations.
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(define_insn_reservation "1020mult4" 3
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(and (eq_attr "tune" "arm1020e,arm1022e")
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(eq_attr "insn" "muls,mlas"))
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"1020a_e*4,1020a_m,1020a_w")
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;; Long multiply instructions that produce two registers of
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;; output (such as umull) make their results available in two cycles;
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;; the least significant word is available before the most significant
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;; word. That fact is not modeled; instead, the instructions are
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;; described.as if the entire result was available at the end of the
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;; cycle in which both words are available.
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;; The "umull", "umlal", "smull", and "smlal" instructions all take
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;; three iterations through the execute cycle, and make their results
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;; available after the memory cycle.
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(define_insn_reservation "1020mult5" 4
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(and (eq_attr "tune" "arm1020e,arm1022e")
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(eq_attr "insn" "umull,umlal,smull,smlal"))
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"1020a_e*3,1020a_m,1020a_w")
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;; The "umulls", "umlals", "smulls", and "smlals" instructions loop in
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;; the execute stage for five iterations in order to set the flags.
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;; The value result is available after four iterations.
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(define_insn_reservation "1020mult6" 4
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(and (eq_attr "tune" "arm1020e,arm1022e")
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(eq_attr "insn" "umulls,umlals,smulls,smlals"))
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"1020a_e*5,1020a_m,1020a_w")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Load/Store Instructions
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; The models for load/store instructions do not accurately describe
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;; the difference between operations with a base register writeback
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;; (such as "ldm!"). These models assume that all memory references
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;; hit in dcache.
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;; LSU instructions require six cycles to execute. They use the ALU
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;; pipeline in all but the 5th cycle, and the LSU pipeline in cycles
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;; three through six.
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;; Loads and stores which use a scaled register offset or scaled
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;; register pre-indexed addressing mode take three cycles EXCEPT for
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;; those that are base + offset with LSL of 0 or 2, or base - offset
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;; with LSL of zero. The remainder take 1 cycle to execute.
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;; For 4byte loads there is a bypass from the load stage
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(define_insn_reservation "1020load1_op" 2
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(and (eq_attr "tune" "arm1020e,arm1022e")
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(eq_attr "type" "load_byte,load1"))
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"1020a_e+1020l_e,1020l_m,1020l_w")
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(define_insn_reservation "1020store1_op" 0
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(and (eq_attr "tune" "arm1020e,arm1022e")
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(eq_attr "type" "store1"))
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"1020a_e+1020l_e,1020l_m,1020l_w")
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;; A load's result can be stored by an immediately following store
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(define_bypass 1 "1020load1_op" "1020store1_op" "arm_no_early_store_addr_dep")
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;; On a LDM/STM operation, the LSU pipeline iterates until all of the
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;; registers have been processed.
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;;
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;; The time it takes to load the data depends on whether or not the
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;; base address is 64-bit aligned; if it is not, an additional cycle
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;; is required. This model assumes that the address is always 64-bit
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;; aligned. Because the processor can load two registers per cycle,
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;; that assumption means that we use the same instruction reservations
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;; for loading 2k and 2k - 1 registers.
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;;
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;; The ALU pipeline is decoupled after the first cycle unless there is
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;; a register dependency; the dependency is cleared as soon as the LDM/STM
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;; has dealt with the corresponding register. So for example,
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;; stmia sp, {r0-r3}
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;; add r0, r0, #4
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;; will have one fewer stalls than
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;; stmia sp, {r0-r3}
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;; add r3, r3, #4
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;;
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;; As with ALU operations, if one of the destination registers is the
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;; PC, there are additional stalls; that is not modeled.
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(define_insn_reservation "1020load2_op" 2
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(and (eq_attr "tune" "arm1020e,arm1022e")
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(eq_attr "type" "load2"))
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"1020a_e+1020l_e,1020l_m,1020l_w")
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(define_insn_reservation "1020store2_op" 0
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(and (eq_attr "tune" "arm1020e,arm1022e")
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(eq_attr "type" "store2"))
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"1020a_e+1020l_e,1020l_m,1020l_w")
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(define_insn_reservation "1020load34_op" 3
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(and (eq_attr "tune" "arm1020e,arm1022e")
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(eq_attr "type" "load3,load4"))
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"1020a_e+1020l_e,1020l_e+1020l_m,1020l_m,1020l_w")
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(define_insn_reservation "1020store34_op" 0
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(and (eq_attr "tune" "arm1020e,arm1022e")
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(eq_attr "type" "store3,store4"))
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"1020a_e+1020l_e,1020l_e+1020l_m,1020l_m,1020l_w")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Branch and Call Instructions
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Branch instructions are difficult to model accurately. The ARM
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;; core can predict most branches. If the branch is predicted
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;; correctly, and predicted early enough, the branch can be completely
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;; eliminated from the instruction stream. Some branches can
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;; therefore appear to require zero cycles to execute. We assume that
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;; all branches are predicted correctly, and that the latency is
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;; therefore the minimum value.
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(define_insn_reservation "1020branch_op" 0
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(and (eq_attr "tune" "arm1020e,arm1022e")
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(eq_attr "type" "branch"))
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"1020a_e")
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;; The latency for a call is not predictable. Therefore, we use 32 as
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;; roughly equivalent to positive infinity.
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(define_insn_reservation "1020call_op" 32
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(and (eq_attr "tune" "arm1020e,arm1022e")
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(eq_attr "type" "call"))
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"1020a_e*32")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; VFP
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(define_cpu_unit "v10_fmac" "arm1020e")
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(define_cpu_unit "v10_ds" "arm1020e")
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(define_cpu_unit "v10_fmstat" "arm1020e")
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(define_cpu_unit "v10_ls1,v10_ls2,v10_ls3" "arm1020e")
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;; fmstat is a serializing instruction. It will stall the core until
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;; the mac and ds units have completed.
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(exclusion_set "v10_fmac,v10_ds" "v10_fmstat")
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(define_attr "vfp10" "yes,no"
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(const (if_then_else (and (eq_attr "tune" "arm1020e,arm1022e")
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(eq_attr "fpu" "vfp"))
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(const_string "yes") (const_string "no"))))
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;; The VFP "type" attributes differ from those used in the FPA model.
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;; ffarith Fast floating point insns, e.g. abs, neg, cpy, cmp.
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;; farith Most arithmetic insns.
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;; fmul Double precision multiply.
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;; fdivs Single precision sqrt or division.
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;; fdivd Double precision sqrt or division.
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;; f_flag fmstat operation
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;; f_load Floating point load from memory.
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;; f_store Floating point store to memory.
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;; f_2_r Transfer vfp to arm reg.
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;; r_2_f Transfer arm to vfp reg.
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;; Note, no instruction can issue to the VFP if the core is stalled in the
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;; first execute state. We model this by using 1020a_e in the first cycle.
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(define_insn_reservation "v10_ffarith" 5
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(and (eq_attr "vfp10" "yes")
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(eq_attr "type" "ffarith"))
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"1020a_e+v10_fmac")
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(define_insn_reservation "v10_farith" 5
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(and (eq_attr "vfp10" "yes")
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(eq_attr "type" "farith"))
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"1020a_e+v10_fmac")
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(define_insn_reservation "v10_cvt" 5
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(and (eq_attr "vfp10" "yes")
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(eq_attr "type" "f_cvt"))
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"1020a_e+v10_fmac")
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(define_insn_reservation "v10_fmul" 6
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(and (eq_attr "vfp10" "yes")
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(eq_attr "type" "fmul"))
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"1020a_e+v10_fmac*2")
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(define_insn_reservation "v10_fdivs" 18
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(and (eq_attr "vfp10" "yes")
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(eq_attr "type" "fdivs"))
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"1020a_e+v10_ds*14")
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(define_insn_reservation "v10_fdivd" 32
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(and (eq_attr "vfp10" "yes")
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(eq_attr "type" "fdivd"))
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"1020a_e+v10_fmac+v10_ds*28")
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(define_insn_reservation "v10_floads" 4
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(and (eq_attr "vfp10" "yes")
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(eq_attr "type" "f_loads"))
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"1020a_e+1020l_e+v10_ls1,v10_ls2")
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;; We model a load of a double as needing all the vfp ls* stage in cycle 1.
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;; This gives the correct mix between single-and double loads where a flds
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;; followed by and fldd will stall for one cycle, but two back-to-back fldd
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||
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|
;; insns stall for two cycles.
|
||
|
|
(define_insn_reservation "v10_floadd" 5
|
||
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|
(and (eq_attr "vfp10" "yes")
|
||
|
|
(eq_attr "type" "f_loadd"))
|
||
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|
"1020a_e+1020l_e+v10_ls1+v10_ls2+v10_ls3,v10_ls2+v10_ls3,v10_ls3")
|
||
|
|
|
||
|
|
;; Moves to/from arm regs also use the load/store pipeline.
|
||
|
|
|
||
|
|
(define_insn_reservation "v10_c2v" 4
|
||
|
|
(and (eq_attr "vfp10" "yes")
|
||
|
|
(eq_attr "type" "r_2_f"))
|
||
|
|
"1020a_e+1020l_e+v10_ls1,v10_ls2")
|
||
|
|
|
||
|
|
(define_insn_reservation "v10_fstores" 1
|
||
|
|
(and (eq_attr "vfp10" "yes")
|
||
|
|
(eq_attr "type" "f_stores"))
|
||
|
|
"1020a_e+1020l_e+v10_ls1,v10_ls2")
|
||
|
|
|
||
|
|
(define_insn_reservation "v10_fstored" 1
|
||
|
|
(and (eq_attr "vfp10" "yes")
|
||
|
|
(eq_attr "type" "f_stored"))
|
||
|
|
"1020a_e+1020l_e+v10_ls1+v10_ls2+v10_ls3,v10_ls2+v10_ls3,v10_ls3")
|
||
|
|
|
||
|
|
(define_insn_reservation "v10_v2c" 1
|
||
|
|
(and (eq_attr "vfp10" "yes")
|
||
|
|
(eq_attr "type" "f_2_r"))
|
||
|
|
"1020a_e+1020l_e,1020l_m,1020l_w")
|
||
|
|
|
||
|
|
(define_insn_reservation "v10_to_cpsr" 2
|
||
|
|
(and (eq_attr "vfp10" "yes")
|
||
|
|
(eq_attr "type" "f_flag"))
|
||
|
|
"1020a_e+v10_fmstat,1020a_e+1020l_e,1020l_m,1020l_w")
|
||
|
|
|
||
|
|
;; VFP bypasses
|
||
|
|
|
||
|
|
;; There are bypasses for most operations other than store
|
||
|
|
|
||
|
|
(define_bypass 3
|
||
|
|
"v10_c2v,v10_floads"
|
||
|
|
"v10_ffarith,v10_farith,v10_fmul,v10_fdivs,v10_fdivd,v10_cvt")
|
||
|
|
|
||
|
|
(define_bypass 4
|
||
|
|
"v10_floadd"
|
||
|
|
"v10_ffarith,v10_farith,v10_fmul,v10_fdivs,v10_fdivd")
|
||
|
|
|
||
|
|
;; Arithmetic to other arithmetic saves a cycle due to forwarding
|
||
|
|
(define_bypass 4
|
||
|
|
"v10_ffarith,v10_farith"
|
||
|
|
"v10_ffarith,v10_farith,v10_fmul,v10_fdivs,v10_fdivd")
|
||
|
|
|
||
|
|
(define_bypass 5
|
||
|
|
"v10_fmul"
|
||
|
|
"v10_ffarith,v10_farith,v10_fmul,v10_fdivs,v10_fdivd")
|
||
|
|
|
||
|
|
(define_bypass 17
|
||
|
|
"v10_fdivs"
|
||
|
|
"v10_ffarith,v10_farith,v10_fmul,v10_fdivs,v10_fdivd")
|
||
|
|
|
||
|
|
(define_bypass 31
|
||
|
|
"v10_fdivd"
|
||
|
|
"v10_ffarith,v10_farith,v10_fmul,v10_fdivs,v10_fdivd")
|
||
|
|
|
||
|
|
;; VFP anti-dependencies.
|
||
|
|
|
||
|
|
;; There is one anti-dependence in the following case (not yet modelled):
|
||
|
|
;; - After a store: one extra cycle for both fsts and fstd
|
||
|
|
;; Note, back-to-back fstd instructions will overload the load/store datapath
|
||
|
|
;; causing a two-cycle stall.
|