68 lines
2.9 KiB
C
68 lines
2.9 KiB
C
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/*-
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* Copyright (c) 1999 Kazutaka YOKOTA <yokota@zodiac.mech.utsunomiya-u.ac.jp>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer as
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* the first lines of this file unmodified.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id:$
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*/
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#ifndef _DEV_FB_VGAREG_H_
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#define _DEV_FB_VGAREG_H_
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/* physical addresses */
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#define MDA_BUF_BASE 0xb0000
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#define MDA_BUF_SIZE 0x08000
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#define MDA_BUF BIOS_PADDRTOVADDR(MDA_BUF_BASE)
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#define CGA_BUF_BASE 0xb8000
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#define CGA_BUF_SIZE 0x08000
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#define CGA_BUF BIOS_PADDRTOVADDR(CGA_BUF_BASE)
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#define EGA_BUF_BASE 0xa0000
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#define EGA_BUF_SIZE 0x20000
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#define EGA_BUF BIOS_PADDRTOVADDR(EGA_BUF_BASE)
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#define GRAPHICS_BUF_BASE 0xa0000
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#define GRAPHICS_BUF_SIZE 0x10000
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#define GRAPHICS_BUF BIOS_PADDRTOVADDR(GRAPHICS_BUF_BASE)
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#define FONT_BUF BIOS_PADDRTOVADDR(GRAPHICS_BUF_BASE)
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#define VIDEO_BUF_BASE 0xa0000
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#define VIDEO_BUF_SIZE 0x20000
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/* I/O port addresses */
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#define MONO_CRTC (IO_MDA + 0x04) /* crt controller base mono */
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#define COLOR_CRTC (IO_CGA + 0x04) /* crt controller base color */
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#define MISC (IO_VGA + 0x02) /* misc output register */
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#define ATC (IO_VGA + 0x00) /* attribute controller */
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#define TSIDX (IO_VGA + 0x04) /* timing sequencer idx */
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#define TSREG (IO_VGA + 0x05) /* timing sequencer data */
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#define PIXMASK (IO_VGA + 0x06) /* pixel write mask */
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#define PALRADR (IO_VGA + 0x07) /* palette read address */
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#define PALWADR (IO_VGA + 0x08) /* palette write address */
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#define PALDATA (IO_VGA + 0x09) /* palette data register */
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#define GDCIDX (IO_VGA + 0x0E) /* graph data controller idx */
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#define GDCREG (IO_VGA + 0x0F) /* graph data controller data */
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#ifdef KERNEL
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extern int (*vga_sub_configure)(int flags);
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#endif
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#endif /* _DEV_FB_VGAREG_H_ */
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