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freebsd-nq/sys/mips/nlm/xlp_pci.c

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MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
/*-
sys/mips: further adoption of SPDX licensing ID tags. Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
2017-11-27 15:07:26 +00:00
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
Update memory and resource allocation code for SoC devices The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
* Copyright (c) 2003-2012 Broadcom Corporation
* All Rights Reserved
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
Update memory and resource allocation code for SoC devices The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
*
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
Update memory and resource allocation code for SoC devices The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
Whitespace fixes for files in sys/mips/nlm Clean up whitespace issues under sys/mips/nlm (except dev). No functional change in this commit.
2015-02-28 00:17:29 +00:00
*
Update memory and resource allocation code for SoC devices The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/types.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/malloc.h>
#include <sys/bus.h>
#include <sys/endian.h>
#include <sys/rman.h>
Update memory and resource allocation code for SoC devices The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
#include <sys/pciio.h>
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
Fix build: include machine/bus.h before uart.h Reported by: emaste Sponsored by: DARPA, AFRL
2017-03-02 17:09:14 +00:00
#include <machine/bus.h>
#include <machine/md_var.h>
#include <machine/intr_machdep.h>
#include <machine/cpuregs.h>
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
#include <vm/vm.h>
#include <vm/vm_param.h>
#include <vm/pmap.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
Update memory and resource allocation code for SoC devices The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
#include <dev/pci/pci_private.h>
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
#include <dev/uart/uart.h>
#include <dev/uart/uart_bus.h>
#include <dev/uart/uart_cpu.h>
Add subclass of simplebus for Broadcom XLP This will override the resource allocation of simplebus, and also merge the resource allocation code which was in xlp_pci.c. With this change the SoC devices that does not have proper PCI resources will be on the FDT simplebus. We can remove sys/mips/nlm/dev/cfi_pci_xlp.c and sys/mips/nlm/dev/uart_pci_xlp.c
2015-02-27 23:33:53 +00:00
#include <dev/ofw/openfirm.h>
Move PCI bus below simplebus for Broadcom XLP This will enable us to do common allocation code for memory and interrupts for SoC devices as well as PCI devices.
2015-02-27 02:21:52 +00:00
#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
#include <mips/nlm/hal/haldefs.h>
#include <mips/nlm/interrupt.h>
#include <mips/nlm/hal/iomap.h>
#include <mips/nlm/hal/mips-extns.h>
#include <mips/nlm/hal/pic.h>
XLP PCIe code update. - XLP supports hardware swap for PCIe IO/MEM accesses. Since we are in big-endian mode, enable hardware swap and use the normal bus space. - move some printfs to bootverbose, and remove others. - fix SoC device resource allocation code - Do not use '|' while updating PCIE_BRIDGE_MSI_ADDRL - some style fixes In collaboration with: Venkatesh J. V. (venkatesh at netlogicmicro com)
2012-03-27 07:57:41 +00:00
#include <mips/nlm/hal/bridge.h>
NOR flash driver for XLP. The NOR interface on the SoC appears on the top level PCI bus. Add a simple driver for this.
2012-03-27 15:16:38 +00:00
#include <mips/nlm/hal/gbu.h>
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
#include <mips/nlm/hal/pcibus.h>
#include <mips/nlm/hal/uart.h>
#include <mips/nlm/xlp.h>
#include "pcib_if.h"
Include pcib_private.h for prototypes. Noticed by: rpokala@ Sponsored by: Netflix
2017-02-26 21:33:18 +00:00
#include <dev/pci/pcib_private.h>
Update memory and resource allocation code for SoC devices The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
#include "pci_if.h"
static int
Add subclass of simplebus for Broadcom XLP This will override the resource allocation of simplebus, and also merge the resource allocation code which was in xlp_pci.c. With this change the SoC devices that does not have proper PCI resources will be on the FDT simplebus. We can remove sys/mips/nlm/dev/cfi_pci_xlp.c and sys/mips/nlm/dev/uart_pci_xlp.c
2015-02-27 23:33:53 +00:00
xlp_pci_attach(device_t dev)
Update memory and resource allocation code for SoC devices The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
{
struct pci_devinfo *dinfo;
Add subclass of simplebus for Broadcom XLP This will override the resource allocation of simplebus, and also merge the resource allocation code which was in xlp_pci.c. With this change the SoC devices that does not have proper PCI resources will be on the FDT simplebus. We can remove sys/mips/nlm/dev/cfi_pci_xlp.c and sys/mips/nlm/dev/uart_pci_xlp.c
2015-02-27 23:33:53 +00:00
device_t pcib;
int maxslots, s, f, pcifunchigh, irq;
int busno, node, devoffset;
Update memory and resource allocation code for SoC devices The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
uint16_t devid;
uint8_t hdrtype;
/*
* The on-chip devices are on a bus that is almost, but not
* quite, completely like PCI. Add those things by hand.
*/
Add subclass of simplebus for Broadcom XLP This will override the resource allocation of simplebus, and also merge the resource allocation code which was in xlp_pci.c. With this change the SoC devices that does not have proper PCI resources will be on the FDT simplebus. We can remove sys/mips/nlm/dev/cfi_pci_xlp.c and sys/mips/nlm/dev/uart_pci_xlp.c
2015-02-27 23:33:53 +00:00
pcib = device_get_parent(dev);
Update memory and resource allocation code for SoC devices The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
busno = pcib_get_bus(dev);
maxslots = PCIB_MAXSLOTS(pcib);
for (s = 0; s <= maxslots; s++) {
pcifunchigh = 0;
f = 0;
hdrtype = PCIB_READ_CONFIG(pcib, busno, s, f, PCIR_HDRTYPE, 1);
if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
continue;
if (hdrtype & PCIM_MFDEV)
pcifunchigh = PCI_FUNCMAX;
Add subclass of simplebus for Broadcom XLP This will override the resource allocation of simplebus, and also merge the resource allocation code which was in xlp_pci.c. With this change the SoC devices that does not have proper PCI resources will be on the FDT simplebus. We can remove sys/mips/nlm/dev/cfi_pci_xlp.c and sys/mips/nlm/dev/uart_pci_xlp.c
2015-02-27 23:33:53 +00:00
node = s / 8;
for (f = 0; f <= pcifunchigh; f++) {
devoffset = XLP_HDR_OFFSET(node, 0, s % 8, f);
if (!nlm_dev_exists(devoffset))
continue;
/* Find if there is a desc for the SoC device */
devid = PCIB_READ_CONFIG(pcib, busno, s, f, PCIR_DEVICE, 2);
/* Skip devices that don't have a proper PCI header */
switch (devid) {
case PCI_DEVICE_ID_NLM_ICI:
case PCI_DEVICE_ID_NLM_PIC:
case PCI_DEVICE_ID_NLM_FMN:
case PCI_DEVICE_ID_NLM_UART:
case PCI_DEVICE_ID_NLM_I2C:
case PCI_DEVICE_ID_NLM_NOR:
case PCI_DEVICE_ID_NLM_MMC:
continue;
case PCI_DEVICE_ID_NLM_EHCI:
irq = PIC_USB_IRQ(f);
PCIB_WRITE_CONFIG(pcib, busno, s, f,
XLP_PCI_DEVSCRATCH_REG0 << 2,
(1 << 8) | irq, 4);
}
Add a new PCI bus interface method to alloc the ivars (dinfo) for a device. The ACPI and OFW PCI bus drivers as well as CardBus override this to allocate the larger ivars to hold additional info beyond the stock PCI ivars. This removes the need to pass the size to functions like pci_add_iov_child() and pci_read_device() simplifying IOV and bus rescanning implementations. As a result of this and earlier changes, the ACPI PCI bus driver no longer needs its own device_attach and pci_create_iov_child methods but can use the methods in the stock PCI bus driver instead. Differential Revision: https://reviews.freebsd.org/D5891
2016-04-15 03:42:12 +00:00
dinfo = pci_read_device(pcib, dev, pcib_get_domain(dev),
busno, s, f);
Add subclass of simplebus for Broadcom XLP This will override the resource allocation of simplebus, and also merge the resource allocation code which was in xlp_pci.c. With this change the SoC devices that does not have proper PCI resources will be on the FDT simplebus. We can remove sys/mips/nlm/dev/cfi_pci_xlp.c and sys/mips/nlm/dev/uart_pci_xlp.c
2015-02-27 23:33:53 +00:00
pci_add_child(dev, dinfo);
}
Update memory and resource allocation code for SoC devices The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
}
return (bus_generic_attach(dev));
}
static int
xlp_pci_probe(device_t dev)
{
device_t pcib;
pcib = device_get_parent(dev);
/*
* Only the top level bus has SoC devices, leave the rest to
* Generic PCI code
*/
if (strcmp(device_get_nameunit(pcib), "pcib0") != 0)
return (ENXIO);
device_set_desc(dev, "XLP SoCbus");
return (BUS_PROBE_DEFAULT);
}
static devclass_t pci_devclass;
static device_method_t xlp_pci_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, xlp_pci_probe),
DEVMETHOD(device_attach, xlp_pci_attach),
Add a bus_null_rescan() method that always fails with an error. Use this in place of kobj_error_method to disable BUS_RESCAN() on PCI drivers that do not use the "standard" scanning algorithm.
2016-04-27 17:49:42 +00:00
DEVMETHOD(bus_rescan, bus_null_rescan),
Update memory and resource allocation code for SoC devices The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
DEVMETHOD_END
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
};
Fix size of PCI softc.
2012-03-27 18:26:35 +00:00
DEFINE_CLASS_1(pci, xlp_pci_driver, xlp_pci_methods, sizeof(struct pci_softc),
pci_driver);
Update memory and resource allocation code for SoC devices The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
DRIVER_MODULE(xlp_pci, pcib, xlp_pci_driver, pci_devclass, 0, 0);
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
static int
xlp_pcib_probe(device_t dev)
{
Move PCI bus below simplebus for Broadcom XLP This will enable us to do common allocation code for memory and interrupts for SoC devices as well as PCI devices.
2015-02-27 02:21:52 +00:00
if (ofw_bus_is_compatible(dev, "netlogic,xlp-pci")) {
device_set_desc(dev, "XLP PCI bus");
return (BUS_PROBE_DEFAULT);
}
return (ENXIO);
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
}
static int
xlp_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
{
switch (which) {
case PCIB_IVAR_DOMAIN:
*result = 0;
return (0);
case PCIB_IVAR_BUS:
*result = 0;
return (0);
}
return (ENOENT);
}
static int
xlp_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
{
switch (which) {
case PCIB_IVAR_DOMAIN:
return (EINVAL);
case PCIB_IVAR_BUS:
return (EINVAL);
}
return (ENOENT);
}
static int
xlp_pcib_maxslots(device_t dev)
{
return (PCI_SLOTMAX);
}
static u_int32_t
xlp_pcib_read_config(device_t dev, u_int b, u_int s, u_int f,
u_int reg, int width)
{
uint32_t data = 0;
uint64_t cfgaddr;
int regindex = reg/sizeof(uint32_t);
cfgaddr = nlm_pcicfg_base(XLP_HDR_OFFSET(0, b, s, f));
if ((width == 2) && (reg & 1))
return 0xFFFFFFFF;
else if ((width == 4) && (reg & 3))
return 0xFFFFFFFF;
Whitespace fixes for files in sys/mips/nlm Clean up whitespace issues under sys/mips/nlm (except dev). No functional change in this commit.
2015-02-28 00:17:29 +00:00
/*
Update memory and resource allocation code for SoC devices The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
* The intline and int pin of SoC devices are DOA, except
* for bridges (slot %8 == 1).
* use the values we stashed in a writable PCI scratch reg.
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
*/
Update memory and resource allocation code for SoC devices The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
if (b == 0 && regindex == 0xf && s % 8 > 1)
regindex = XLP_PCI_DEVSCRATCH_REG0;
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
Update memory and resource allocation code for SoC devices The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
data = nlm_read_pci_reg(cfgaddr, regindex);
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
if (width == 1)
return ((data >> ((reg & 3) << 3)) & 0xff);
else if (width == 2)
return ((data >> ((reg & 3) << 3)) & 0xffff);
else
return (data);
}
static void
xlp_pcib_write_config(device_t dev, u_int b, u_int s, u_int f,
u_int reg, u_int32_t val, int width)
{
uint64_t cfgaddr;
uint32_t data = 0;
int regindex = reg / sizeof(uint32_t);
cfgaddr = nlm_pcicfg_base(XLP_HDR_OFFSET(0, b, s, f));
if ((width == 2) && (reg & 1))
return;
else if ((width == 4) && (reg & 3))
return;
if (width == 1) {
data = nlm_read_pci_reg(cfgaddr, regindex);
data = (data & ~(0xff << ((reg & 3) << 3))) |
(val << ((reg & 3) << 3));
} else if (width == 2) {
data = nlm_read_pci_reg(cfgaddr, regindex);
data = (data & ~(0xffff << ((reg & 3) << 3))) |
(val << ((reg & 3) << 3));
} else {
data = val;
}
Update memory and resource allocation code for SoC devices The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
/*
* use shadow reg for intpin/intline which are dead
*/
if (b == 0 && regindex == 0xf && s % 8 > 1)
regindex = XLP_PCI_DEVSCRATCH_REG0;
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
nlm_write_pci_reg(cfgaddr, regindex, data);
}
XLP PCIe code update. - XLP supports hardware swap for PCIe IO/MEM accesses. Since we are in big-endian mode, enable hardware swap and use the normal bus space. - move some printfs to bootverbose, and remove others. - fix SoC device resource allocation code - Do not use '|' while updating PCIE_BRIDGE_MSI_ADDRL - some style fixes In collaboration with: Venkatesh J. V. (venkatesh at netlogicmicro com)
2012-03-27 07:57:41 +00:00
/*
Little-endian fix for PCI on Broadcom XLP. Update the function xlp_pcib_hardware_swap_enable() to do nothing when BYTE_ORDER is not BIG_ENDIAN. PCIe hardware swap is not requred in little-endian mode as the endianness matches that of CPU.
2013-01-24 11:42:16 +00:00
* Enable byte swap in hardware when compiled big-endian.
* Programs a link's PCIe SWAP regions from the link's IO and MEM address
* ranges.
XLP PCIe code update. - XLP supports hardware swap for PCIe IO/MEM accesses. Since we are in big-endian mode, enable hardware swap and use the normal bus space. - move some printfs to bootverbose, and remove others. - fix SoC device resource allocation code - Do not use '|' while updating PCIE_BRIDGE_MSI_ADDRL - some style fixes In collaboration with: Venkatesh J. V. (venkatesh at netlogicmicro com)
2012-03-27 07:57:41 +00:00
*/
static void
Update memory and resource allocation code for SoC devices The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
xlp_pcib_hardware_swap_enable(int node, int link)
XLP PCIe code update. - XLP supports hardware swap for PCIe IO/MEM accesses. Since we are in big-endian mode, enable hardware swap and use the normal bus space. - move some printfs to bootverbose, and remove others. - fix SoC device resource allocation code - Do not use '|' while updating PCIE_BRIDGE_MSI_ADDRL - some style fixes In collaboration with: Venkatesh J. V. (venkatesh at netlogicmicro com)
2012-03-27 07:57:41 +00:00
{
Little-endian fix for PCI on Broadcom XLP. Update the function xlp_pcib_hardware_swap_enable() to do nothing when BYTE_ORDER is not BIG_ENDIAN. PCIe hardware swap is not requred in little-endian mode as the endianness matches that of CPU.
2013-01-24 11:42:16 +00:00
#if BYTE_ORDER == BIG_ENDIAN
XLP PCIe code update. - XLP supports hardware swap for PCIe IO/MEM accesses. Since we are in big-endian mode, enable hardware swap and use the normal bus space. - move some printfs to bootverbose, and remove others. - fix SoC device resource allocation code - Do not use '|' while updating PCIE_BRIDGE_MSI_ADDRL - some style fixes In collaboration with: Venkatesh J. V. (venkatesh at netlogicmicro com)
2012-03-27 07:57:41 +00:00
uint64_t bbase, linkpcibase;
uint32_t bar;
int pcieoffset;
pcieoffset = XLP_IO_PCIE_OFFSET(node, link);
if (!nlm_dev_exists(pcieoffset))
return;
bbase = nlm_get_bridge_regbase(node);
linkpcibase = nlm_pcicfg_base(pcieoffset);
bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_BASE0 + link);
nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_BASE, bar);
bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_LIMIT0 + link);
Fix PCIe hardware swap configuration for Netlogic XLP The last 12 bits of the limit registers have to be set to 1. These bits are not significant in bridge BARs and are 0 on read, but the bits are valid in the swap limit register and needs to be set.
2012-07-09 10:17:06 +00:00
nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_LIM, bar | 0xFFF);
XLP PCIe code update. - XLP supports hardware swap for PCIe IO/MEM accesses. Since we are in big-endian mode, enable hardware swap and use the normal bus space. - move some printfs to bootverbose, and remove others. - fix SoC device resource allocation code - Do not use '|' while updating PCIE_BRIDGE_MSI_ADDRL - some style fixes In collaboration with: Venkatesh J. V. (venkatesh at netlogicmicro com)
2012-03-27 07:57:41 +00:00
bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_BASE0 + link);
nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_BASE, bar);
bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_LIMIT0 + link);
Fix PCIe hardware swap configuration for Netlogic XLP The last 12 bits of the limit registers have to be set to 1. These bits are not significant in bridge BARs and are 0 on read, but the bits are valid in the swap limit register and needs to be set.
2012-07-09 10:17:06 +00:00
nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_LIM, bar | 0xFFF);
Little-endian fix for PCI on Broadcom XLP. Update the function xlp_pcib_hardware_swap_enable() to do nothing when BYTE_ORDER is not BIG_ENDIAN. PCIe hardware swap is not requred in little-endian mode as the endianness matches that of CPU.
2013-01-24 11:42:16 +00:00
#endif
XLP PCIe code update. - XLP supports hardware swap for PCIe IO/MEM accesses. Since we are in big-endian mode, enable hardware swap and use the normal bus space. - move some printfs to bootverbose, and remove others. - fix SoC device resource allocation code - Do not use '|' while updating PCIE_BRIDGE_MSI_ADDRL - some style fixes In collaboration with: Venkatesh J. V. (venkatesh at netlogicmicro com)
2012-03-27 07:57:41 +00:00
}
Whitespace fixes for files in sys/mips/nlm Clean up whitespace issues under sys/mips/nlm (except dev). No functional change in this commit.
2015-02-28 00:17:29 +00:00
static int
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
xlp_pcib_attach(device_t dev)
{
XLP PCIe code update. - XLP supports hardware swap for PCIe IO/MEM accesses. Since we are in big-endian mode, enable hardware swap and use the normal bus space. - move some printfs to bootverbose, and remove others. - fix SoC device resource allocation code - Do not use '|' while updating PCIE_BRIDGE_MSI_ADDRL - some style fixes In collaboration with: Venkatesh J. V. (venkatesh at netlogicmicro com)
2012-03-27 07:57:41 +00:00
int node, link;
/* enable hardware swap on all nodes/links */
for (node = 0; node < XLP_MAX_NODES; node++)
for (link = 0; link < 4; link++)
Update memory and resource allocation code for SoC devices The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
xlp_pcib_hardware_swap_enable(node, link);
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
Add domain support to PCI bus allocation When the system has more than a single PCI domain, the bus numbers are not unique, thus they cannot be used for "pci" device numbering. Change bus numbers to -1 (i.e. to-be-determined automatically) wherever the code did not care about domains. Reviewed by: jhb Obtained from: Semihalf Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D3406
2015-09-16 23:34:51 +00:00
device_add_child(dev, "pci", -1);
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
bus_generic_attach(dev);
return (0);
}
/*
* XLS PCIe can have upto 4 links, and each link has its on IRQ
Whitespace fixes for files in sys/mips/nlm Clean up whitespace issues under sys/mips/nlm (except dev). No functional change in this commit.
2015-02-28 00:17:29 +00:00
* Find the link on which the device is on
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
*/
static int
xlp_pcie_link(device_t pcib, device_t dev)
{
device_t parent, tmp;
/* find the lane on which the slot is connected to */
tmp = dev;
while (1) {
parent = device_get_parent(tmp);
if (parent == NULL || parent == pcib) {
device_printf(dev, "Cannot find parent bus\n");
return (-1);
}
if (strcmp(device_get_nameunit(parent), "pci0") == 0)
break;
tmp = parent;
}
return (pci_get_function(tmp));
}
static int
xlp_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
{
int i, link;
/*
* Each link has 32 MSIs that can be allocated, but for now
* we only support one device per link.
Whitespace fixes for files in sys/mips/nlm Clean up whitespace issues under sys/mips/nlm (except dev). No functional change in this commit.
2015-02-28 00:17:29 +00:00
* msi_alloc() equivalent is needed when we start supporting
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
* bridges on the PCIe link.
*/
link = xlp_pcie_link(pcib, dev);
if (link == -1)
return (ENXIO);
/*
* encode the irq so that we know it is a MSI interrupt when we
* setup interrupts
*/
for (i = 0; i < count; i++)
irqs[i] = 64 + link * 32 + i;
return (0);
}
static int
xlp_release_msi(device_t pcib, device_t dev, int count, int *irqs)
{
return (0);
}
static int
xlp_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
uint32_t *data)
{
Remove run-time allocation of XLP IRQs Follow the same static IRQ to Interrupt Table Entry mapping as the other OS supported on XLP.
2015-02-26 02:22:47 +00:00
int link;
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
Remove run-time allocation of XLP IRQs Follow the same static IRQ to Interrupt Table Entry mapping as the other OS supported on XLP.
2015-02-26 02:22:47 +00:00
if (irq < 64) {
Whitespace fixes for files in sys/mips/nlm Clean up whitespace issues under sys/mips/nlm (except dev). No functional change in this commit.
2015-02-28 00:17:29 +00:00
device_printf(dev, "%s: map_msi for irq %d - ignored",
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
device_get_nameunit(pcib), irq);
return (ENXIO);
}
Remove run-time allocation of XLP IRQs Follow the same static IRQ to Interrupt Table Entry mapping as the other OS supported on XLP.
2015-02-26 02:22:47 +00:00
link = (irq - 64) / 32;
*addr = MIPS_MSI_ADDR(0);
*data = MIPS_MSI_DATA(PIC_PCIE_IRQ(link));
return (0);
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
}
static void
Improve additional interrupt ACK for Broadcom XLP Handling some interrupts in XLP (like PCIe and SATA) involves writing to vendor specific registers as part of interrupt acknowledgement. This was earlier done with xlp_establish_intr(), but a better solution is to provide a function xlp_set_bus_ack() that can be used with cpu_establish_hardintr(). This will allow platform initialization code to setup these ACKs without changing the standrard drivers.
2015-02-27 00:57:09 +00:00
bridge_pcie_ack(int irq, void *arg)
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
{
uint32_t node,reg;
uint64_t base;
node = nlm_nodeid();
reg = PCIE_MSI_STATUS;
Merge XLP 3XX updates and related rework. * Update message station (CMS) code, read queue ids from PCI header. * Use interrupts to wakeup message handling threads on 3XX * Update PIC code, read interrupt information from PCI header instead of using fixed values. * Update PCI interrupt handling for the PIC change. * Update code for getting chip frequency, new code support XLP 3XX * Misc style(9) fixes In collaboration with: prabhath at netlogicmicro com (CMS/PIC) venkatesh at netlogicmicro.com (PCI)
2011-11-21 08:12:36 +00:00
switch (irq) {
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
case PIC_PCIE_0_IRQ:
base = nlm_pcicfg_base(XLP_IO_PCIE0_OFFSET(node));
break;
case PIC_PCIE_1_IRQ:
base = nlm_pcicfg_base(XLP_IO_PCIE1_OFFSET(node));
break;
case PIC_PCIE_2_IRQ:
base = nlm_pcicfg_base(XLP_IO_PCIE2_OFFSET(node));
break;
case PIC_PCIE_3_IRQ:
base = nlm_pcicfg_base(XLP_IO_PCIE3_OFFSET(node));
break;
default:
return;
}
nlm_write_pci_reg(base, reg, 0xFFFFFFFF);
return;
}
static int
Update memory and resource allocation code for SoC devices The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
mips_platform_pcib_setup_intr(device_t dev, device_t child,
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
struct resource *irq, int flags, driver_filter_t *filt,
driver_intr_t *intr, void *arg, void **cookiep)
{
int error = 0;
int xlpirq;
error = rman_activate_resource(irq);
if (error)
return error;
if (rman_get_start(irq) != rman_get_end(irq)) {
Use uintmax_t (typedef'd to rman_res_t type) for rman ranges. On some architectures, u_long isn't large enough for resource definitions. Particularly, powerpc and arm allow 36-bit (or larger) physical addresses, but type `long' is only 32-bit. This extends rman's resources to uintmax_t. With this change, any resource can feasibly be placed anywhere in physical memory (within the constraints of the driver). Why uintmax_t and not something machine dependent, or uint64_t? Though it's possible for uintmax_t to grow, it's highly unlikely it will become 128-bit on 32-bit architectures. 64-bit architectures should have plenty of RAM to absorb the increase on resource sizes if and when this occurs, and the number of resources on memory-constrained systems should be sufficiently small as to not pose a drastic overhead. That being said, uintmax_t was chosen for source clarity. If it's specified as uint64_t, all printf()-like calls would either need casts to uintmax_t, or be littered with PRI*64 macros. Casts to uintmax_t aren't horrible, but it would also bake into the API for resource_list_print_type() either a hidden assumption that entries get cast to uintmax_t for printing, or these calls would need the PRI*64 macros. Since source code is meant to be read more often than written, I chose the clearest path of simply using uintmax_t. Tested on a PowerPC p5020-based board, which places all device resources in 0xfxxxxxxxx, and has 8GB RAM. Regression tested on qemu-system-i386 Regression tested on qemu-system-mips (malta profile) Tested PAE and devinfo on virtualbox (live CD) Special thanks to bz for his testing on ARM. Reviewed By: bz, jhb (previous) Relnotes: Yes Sponsored by: Alex Perez/Inertial Computing Differential Revision: https://reviews.freebsd.org/D4544
2016-03-18 01:28:41 +00:00
device_printf(dev, "Interrupt allocation %ju != %ju\n",
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
rman_get_start(irq), rman_get_end(irq));
return (EINVAL);
}
xlpirq = rman_get_start(irq);
Update memory and resource allocation code for SoC devices The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
if (xlpirq == 0)
return (0);
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
Update memory and resource allocation code for SoC devices The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
if (strcmp(device_get_name(dev), "pcib") != 0)
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
return (0);
Whitespace fixes for files in sys/mips/nlm Clean up whitespace issues under sys/mips/nlm (except dev). No functional change in this commit.
2015-02-28 00:17:29 +00:00
/*
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
* temporary hack for MSI, we support just one device per
* link, and assign the link interrupt to the device interrupt
*/
if (xlpirq >= 64) {
Merge XLP 3XX updates and related rework. * Update message station (CMS) code, read queue ids from PCI header. * Use interrupts to wakeup message handling threads on 3XX * Update PIC code, read interrupt information from PCI header instead of using fixed values. * Update PCI interrupt handling for the PIC change. * Update code for getting chip frequency, new code support XLP 3XX * Misc style(9) fixes In collaboration with: prabhath at netlogicmicro com (CMS/PIC) venkatesh at netlogicmicro.com (PCI)
2011-11-21 08:12:36 +00:00
int node, val, link;
uint64_t base;
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
xlpirq -= 64;
if (xlpirq % 32 != 0)
return (0);
node = nlm_nodeid();
XLP PCIe code update. - XLP supports hardware swap for PCIe IO/MEM accesses. Since we are in big-endian mode, enable hardware swap and use the normal bus space. - move some printfs to bootverbose, and remove others. - fix SoC device resource allocation code - Do not use '|' while updating PCIE_BRIDGE_MSI_ADDRL - some style fixes In collaboration with: Venkatesh J. V. (venkatesh at netlogicmicro com)
2012-03-27 07:57:41 +00:00
link = xlpirq / 32;
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
base = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node,link));
/* MSI Interrupt Vector enable at bridge's configuration */
nlm_write_pci_reg(base, PCIE_MSI_EN, PCIE_MSI_VECTOR_INT_EN);
val = nlm_read_pci_reg(base, PCIE_INT_EN0);
/* MSI Interrupt enable at bridge's configuration */
nlm_write_pci_reg(base, PCIE_INT_EN0,
XLP PCIe code update. - XLP supports hardware swap for PCIe IO/MEM accesses. Since we are in big-endian mode, enable hardware swap and use the normal bus space. - move some printfs to bootverbose, and remove others. - fix SoC device resource allocation code - Do not use '|' while updating PCIE_BRIDGE_MSI_ADDRL - some style fixes In collaboration with: Venkatesh J. V. (venkatesh at netlogicmicro com)
2012-03-27 07:57:41 +00:00
(val | PCIE_MSI_INT_EN));
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
/* legacy interrupt disable at bridge */
val = nlm_read_pci_reg(base, PCIE_BRIDGE_CMD);
nlm_write_pci_reg(base, PCIE_BRIDGE_CMD,
XLP PCIe code update. - XLP supports hardware swap for PCIe IO/MEM accesses. Since we are in big-endian mode, enable hardware swap and use the normal bus space. - move some printfs to bootverbose, and remove others. - fix SoC device resource allocation code - Do not use '|' while updating PCIE_BRIDGE_MSI_ADDRL - some style fixes In collaboration with: Venkatesh J. V. (venkatesh at netlogicmicro com)
2012-03-27 07:57:41 +00:00
(val | PCIM_CMD_INTxDIS));
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
/* MSI address update at bridge */
nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_ADDRL,
XLP PCIe code update. - XLP supports hardware swap for PCIe IO/MEM accesses. Since we are in big-endian mode, enable hardware swap and use the normal bus space. - move some printfs to bootverbose, and remove others. - fix SoC device resource allocation code - Do not use '|' while updating PCIE_BRIDGE_MSI_ADDRL - some style fixes In collaboration with: Venkatesh J. V. (venkatesh at netlogicmicro com)
2012-03-27 07:57:41 +00:00
MSI_MIPS_ADDR_BASE);
nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_ADDRH, 0);
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
val = nlm_read_pci_reg(base, PCIE_BRIDGE_MSI_CAP);
/* MSI capability enable at bridge */
Whitespace fixes for files in sys/mips/nlm Clean up whitespace issues under sys/mips/nlm (except dev). No functional change in this commit.
2015-02-28 00:17:29 +00:00
nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_CAP,
XLP PCIe code update. - XLP supports hardware swap for PCIe IO/MEM accesses. Since we are in big-endian mode, enable hardware swap and use the normal bus space. - move some printfs to bootverbose, and remove others. - fix SoC device resource allocation code - Do not use '|' while updating PCIE_BRIDGE_MSI_ADDRL - some style fixes In collaboration with: Venkatesh J. V. (venkatesh at netlogicmicro com)
2012-03-27 07:57:41 +00:00
(val | (PCIM_MSICTRL_MSI_ENABLE << 16) |
(PCIM_MSICTRL_MMC_32 << 16)));
Remove run-time allocation of XLP IRQs Follow the same static IRQ to Interrupt Table Entry mapping as the other OS supported on XLP.
2015-02-26 02:22:47 +00:00
xlpirq = PIC_PCIE_IRQ(link);
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
}
Remove run-time allocation of XLP IRQs Follow the same static IRQ to Interrupt Table Entry mapping as the other OS supported on XLP.
2015-02-26 02:22:47 +00:00
Improve additional interrupt ACK for Broadcom XLP Handling some interrupts in XLP (like PCIe and SATA) involves writing to vendor specific registers as part of interrupt acknowledgement. This was earlier done with xlp_establish_intr(), but a better solution is to provide a function xlp_set_bus_ack() that can be used with cpu_establish_hardintr(). This will allow platform initialization code to setup these ACKs without changing the standrard drivers.
2015-02-27 00:57:09 +00:00
/* if it is for real PCIe, we need to ack at bridge too */
if (xlpirq >= PIC_PCIE_IRQ(0) && xlpirq <= PIC_PCIE_IRQ(3))
xlp_set_bus_ack(xlpirq, bridge_pcie_ack, NULL);
cpu_establish_hardintr(device_get_name(child), filt, intr, arg,
xlpirq, flags, cookiep);
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
return (0);
}
static int
Update memory and resource allocation code for SoC devices The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
mips_platform_pcib_teardown_intr(device_t dev, device_t child,
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
struct resource *irq, void *cookie)
{
if (strcmp(device_get_name(child), "pci") == 0) {
/* if needed reprogram the pic to clear pcix related entry */
device_printf(dev, "teardown intr\n");
}
return (bus_generic_teardown_intr(dev, child, irq, cookie));
}
static int
Update memory and resource allocation code for SoC devices The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
mips_pcib_route_interrupt(device_t bus, device_t dev, int pin)
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
{
Remove run-time allocation of XLP IRQs Follow the same static IRQ to Interrupt Table Entry mapping as the other OS supported on XLP.
2015-02-26 02:22:47 +00:00
int f, d;
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
/*
* Validate requested pin number.
*/
if ((pin < 1) || (pin > 4))
return (255);
Merge XLP 3XX updates and related rework. * Update message station (CMS) code, read queue ids from PCI header. * Use interrupts to wakeup message handling threads on 3XX * Update PIC code, read interrupt information from PCI header instead of using fixed values. * Update PCI interrupt handling for the PIC change. * Update code for getting chip frequency, new code support XLP 3XX * Misc style(9) fixes In collaboration with: prabhath at netlogicmicro com (CMS/PIC) venkatesh at netlogicmicro.com (PCI)
2011-11-21 08:12:36 +00:00
if (pci_get_bus(dev) == 0 &&
pci_get_vendor(dev) == PCI_VENDOR_NETLOGIC) {
f = pci_get_function(dev);
d = pci_get_slot(dev) % 8;
/*
* For PCIe links, return link IRT, for other SoC devices
* get the IRT from its PCIe header
*/
Remove run-time allocation of XLP IRQs Follow the same static IRQ to Interrupt Table Entry mapping as the other OS supported on XLP.
2015-02-26 02:22:47 +00:00
if (d == 1)
return (PIC_PCIE_IRQ(f));
else
return (255); /* use intline, don't reroute */
Merge XLP 3XX updates and related rework. * Update message station (CMS) code, read queue ids from PCI header. * Use interrupts to wakeup message handling threads on 3XX * Update PIC code, read interrupt information from PCI header instead of using fixed values. * Update PCI interrupt handling for the PIC change. * Update code for getting chip frequency, new code support XLP 3XX * Misc style(9) fixes In collaboration with: prabhath at netlogicmicro com (CMS/PIC) venkatesh at netlogicmicro.com (PCI)
2011-11-21 08:12:36 +00:00
} else {
/* Regular PCI devices */
Remove run-time allocation of XLP IRQs Follow the same static IRQ to Interrupt Table Entry mapping as the other OS supported on XLP.
2015-02-26 02:22:47 +00:00
return (PIC_PCIE_IRQ(xlp_pcie_link(bus, dev)));
Merge XLP 3XX updates and related rework. * Update message station (CMS) code, read queue ids from PCI header. * Use interrupts to wakeup message handling threads on 3XX * Update PIC code, read interrupt information from PCI header instead of using fixed values. * Update PCI interrupt handling for the PIC change. * Update code for getting chip frequency, new code support XLP 3XX * Misc style(9) fixes In collaboration with: prabhath at netlogicmicro com (CMS/PIC) venkatesh at netlogicmicro.com (PCI)
2011-11-21 08:12:36 +00:00
}
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
}
static device_method_t xlp_pcib_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, xlp_pcib_probe),
DEVMETHOD(device_attach, xlp_pcib_attach),
/* Bus interface */
DEVMETHOD(bus_read_ivar, xlp_pcib_read_ivar),
DEVMETHOD(bus_write_ivar, xlp_pcib_write_ivar),
Add subclass of simplebus for Broadcom XLP This will override the resource allocation of simplebus, and also merge the resource allocation code which was in xlp_pci.c. With this change the SoC devices that does not have proper PCI resources will be on the FDT simplebus. We can remove sys/mips/nlm/dev/cfi_pci_xlp.c and sys/mips/nlm/dev/uart_pci_xlp.c
2015-02-27 23:33:53 +00:00
DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
DEVMETHOD(bus_release_resource, bus_generic_release_resource),
DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
Update memory and resource allocation code for SoC devices The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
DEVMETHOD(bus_setup_intr, mips_platform_pcib_setup_intr),
DEVMETHOD(bus_teardown_intr, mips_platform_pcib_teardown_intr),
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
/* pcib interface */
DEVMETHOD(pcib_maxslots, xlp_pcib_maxslots),
DEVMETHOD(pcib_read_config, xlp_pcib_read_config),
DEVMETHOD(pcib_write_config, xlp_pcib_write_config),
Update memory and resource allocation code for SoC devices The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
DEVMETHOD(pcib_route_interrupt, mips_pcib_route_interrupt),
Convert PCIe Hot Plug to using pci_request_feature Convert PCIe hot plug support over to asking the firmware, if any, for permission to use the HotPlug hardware. Implement pci_request_feature for ACPI. All other host pci connections to allowing all valid feature requests. Sponsored by: Netflix
2017-02-25 06:11:59 +00:00
DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
DEVMETHOD(pcib_alloc_msi, xlp_alloc_msi),
DEVMETHOD(pcib_release_msi, xlp_release_msi),
DEVMETHOD(pcib_map_msi, xlp_map_msi),
- There's no need to overwrite the default device method with the default one. Interestingly, these are actually the default for quite some time (bus_generic_driver_added(9) since r52045 and bus_generic_print_child(9) since r52045) but even recently added device drivers do this unnecessarily. Discussed with: jhb, marcel - While at it, use DEVMETHOD_END. Discussed with: jhb - Also while at it, use __FBSDID.
2011-11-22 21:28:20 +00:00
DEVMETHOD_END
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
};
static driver_t xlp_pcib_driver = {
"pcib",
xlp_pcib_methods,
Update memory and resource allocation code for SoC devices The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
1, /* no softc */
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
};
Move PCI bus below simplebus for Broadcom XLP This will enable us to do common allocation code for memory and interrupts for SoC devices as well as PCI devices.
2015-02-27 02:21:52 +00:00
static devclass_t pcib_devclass;
DRIVER_MODULE(xlp_pcib, simplebus, xlp_pcib_driver, pcib_devclass, 0, 0);
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