freebsd-nq/sys/mips/include/elf.h

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/*
* Copyright (c) 2013 M. Warner Losh. All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* See below starting with the line with $NetBSD...$ for code this applies to.
*/
#ifndef __MIPS_ELF_H
#define __MIPS_ELF_H
/* FreeBSD specific bits - derived from FreeBSD specific files and changes to old elf.h */
/*
* Define __ELF_WORD_SIZE based on the ABI, if not defined yet. This sets
* the proper defaults when we're not trying to do 32-bit on 64-bit systems.
* We include both 32 and 64 bit versions so we can support multiple ABIs.
*/
#ifndef __ELF_WORD_SIZE
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines Get the sense of this right. We use uintpr_t for bus_addr_t when we're building everything except octeon && 32-bit. As note before, we need a clearner way, but at least now the hack is right. r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines Add in Cavium's CID. Report what the unknown CID is. r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON. Spell ld script name right. r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines Another kludge for 64-bit bus_addr_t with 32-bit pointers... r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines - Add cpu_init_interrupts function that is supposed to prepeare stuff required for spinning out interrupts later - Add API for managing intrcnt/intrnames arrays - Some minor style(9) fixes r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines For XLR adds extern for its bus space routines r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines Add some newer MIPS CO cores. r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines db_expr_t is really closer to a register_t. Submitted by: bde@ r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines - Remove bunch of declared but not defined cach-related variables - Add mips_picache_linesize and mips_pdcache_linesize variables r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines Get rid of the hardcoded constants to define cacheable memory: SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE Instead we now keep a copy of the memory regions enumerated by platform-specific code and use that to determine whether an address is cacheable or not. r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines - Commit missing part of "bt" fix: store PC register in pcb_context struct in cpu_switch and use it in stack_trace function later. pcb_regs contains state of the process stored by exception handler and therefor is not valid for sleeping processes. r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines Undo spamage of last MFC. r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines _ALIGN has to return u_long, since pointers don't fit into u_int in 64-bit mips. r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines - Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe. Context info could be obtained from other sources (see below) no only from td_pcb field - Do not show a0..a3 values unless they're obtained from the stack. These are only confirmed values. - Fix bt command in DDB. Previous implementation used thread's trapframe structure as a source info for trace unwinding, but this structure is filled only when exception occurs. Valid register values for sleeping processes are in pcb_context array. For curthread use pc/sp/ra for current frame r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines - Get rid of label_t. It came from NetBSD and was used only in one place r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines - Move stack tracing function to db_trace.c - Axe unused extern MipsXXX declarations - Move all declarations for functions in exceptions.S/swtch.S from trap.c to respective headers r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines - Sync caches properly when dealing with sf_buf r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines (u_int) is the wrong type here. Use unsigned long instead, even though that's only less wrong... r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines Use unsigned long instead of unsigned for the integer casts here. The former works for both ILP32 and LP64 programming models, while the latter fails LP64. r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines - Make i/d cache size field 32-bit to prevent overflow Submited by: Neelkanth Natu r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines fix prototype for MipsEmulateBranch. r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines Better definitions for a few types for n32/n64. r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines Fixed aligned macros... r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines - Port busdma code from FreeBSD/arm. This is more mature version that takes into account all limitation to DMA memory (boundaries, alignment) and implements bounce pages. - Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines Fix atomic_store_64 prototype for 64-bit systems. r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines The MCOUNT macro isn't going to work in 64-bit mode. Add a note to this effect. r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines Provide a macro for PTR_ADDU as well. We may need to implement this differently for N32... Use PTR_ADDU in DO_AST macro. r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines Change the addu here to daddu. addu paranoina prodded by: jmallet@ r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines addu and subu are special. We need to use daddu and dsubu here to get proper behavior. Submitted by: jmallet@ r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines The SB1 has cohernet memory, so add it. Also, Maxmem is better as a long. Submitted by: Neelkanth Natu r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines The SB1 needs a special value for the cache field of the pte. Submitted by: Neelkanth Natu r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines compute the areas to save registers in for 64-bit access correctly. r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines First cut at 64-bit types. not 100% sure these are all correct for N32 ABI. r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines Trim unreferenced goo. SDRAM likely should be next, but it is still referenced. r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines First cut at atomics for 64-bit machines and SMP machines. # Note: Cavium provided a port that has atomics similar to these, but # that does a syncw; sync; atomic; sync; syncw where we just do the classic # mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why # the extra is needed. Since my initial target is one core, I'll defer # investigation until I bring up multiple cores. syncw is an octeon specific # instruction. r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines Bring in cdefs.h from NetBSD to define ABI goo. Obtained from: NetBSD r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA, ala sgi, and use it in preference to a bare 'la' so that it gets translated to a 'dla' for the 64-bit pointer ABIs. r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines Use uintptr_t rather than unsigned here for 64-bit correctness. r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe this is correct. While registers are 64-bit, n32 is a 32-bit ABI and lives in a 32-bit world (with explicit 64-bit registers, however). Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4 + SZREG' to reflect the actual offset of the structure in question. r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines (1) Use uintptr_t in preference to unsigned. The latter isn't right for 64-bit case, while the former is. (2) include a SB1 specific coherency mapping Submitted by: Neelkanth Nath (2) r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines db_expr_t should be a intptr_t, not an int. These expressions can be addresses or numbers, and that's a intptr_t if I ever saw one. r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines Define COP0_SYNC for SB1 CPU. Submitted by: Neelkanth Natu r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines Switch to ABI agnostic ta0-ta3. Provide defs for this in the right places. Provide n32/n64 register name defintions. This should have no effect for the O32 builds that everybody else uses, but should help make N64 builds possible (lots of other changes are needed for that). Obtained from: NetBSD (for the regdef.h changes) r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines - Add support for handling TLS area address in kernel space. From the userland point of view get/set operations are performed using sysarch(2) call. r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines - Add guards to ensure that these files are included only once r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines - Mark temp variable as "earlyclobber" in assembler inline in atomic_fetchadd_32. Without it gcc would use it as input register for v and sometimes generate following code for function call like atomic_fetchadd_32(&(fp)->f_count, -1): 801238b4: 2402ffff li v0,-1 801238b8: c2230018 ll v1,24(s1) 801238bc: 00431021 addu v0,v0,v1 801238c0: e2220018 sc v0,24(s1) 801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8> 801238c8: 00000000 nop Which is definitly wrong because if sc fails v0 is set to 0 and previous value of -1 is overriden hence whole operation turns to bogus r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines bye bye. This is no longer referenced, but much code from it will resurface for a bus-space implementation. r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines Cavium-specific goo is no longer necessary here. Of course, I now have to write a bus space for cavium, but that shouldn't be too hard. r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines Move this to a more approrpiate plae. r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines Bring this in from the cavium port. r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines - Use restoreintr instead of enableint while accessing pcpu in DO_AST r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines - Add type cast for atomic_cmpset_acq_ptr arguments r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines - Remove now unused NetBSDism intr.h r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines - Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR macroses thet check if address belongs to KSEG0, KSEG1 or both of them respectively. r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines - Cast argument to proper type in order to avoid warnings like "shift value is too large for given type" r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines - Use naming convention the same as MIPS spec does: eliminate _sel1 sufix and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1 - Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes) r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines - Define accessor functions for CP0 Config(16) register selects 1, 2, 3. Content of these registers is defined in MIPS spec and can be used for obtaining info about CPU capabilities. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 19:50:24 +00:00
#if defined(__mips_n64)
#define __ELF_WORD_SIZE 64
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines Get the sense of this right. We use uintpr_t for bus_addr_t when we're building everything except octeon && 32-bit. As note before, we need a clearner way, but at least now the hack is right. r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines Add in Cavium's CID. Report what the unknown CID is. r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON. Spell ld script name right. r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines Another kludge for 64-bit bus_addr_t with 32-bit pointers... r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines - Add cpu_init_interrupts function that is supposed to prepeare stuff required for spinning out interrupts later - Add API for managing intrcnt/intrnames arrays - Some minor style(9) fixes r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines For XLR adds extern for its bus space routines r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines Add some newer MIPS CO cores. r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines db_expr_t is really closer to a register_t. Submitted by: bde@ r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines - Remove bunch of declared but not defined cach-related variables - Add mips_picache_linesize and mips_pdcache_linesize variables r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines Get rid of the hardcoded constants to define cacheable memory: SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE Instead we now keep a copy of the memory regions enumerated by platform-specific code and use that to determine whether an address is cacheable or not. r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines - Commit missing part of "bt" fix: store PC register in pcb_context struct in cpu_switch and use it in stack_trace function later. pcb_regs contains state of the process stored by exception handler and therefor is not valid for sleeping processes. r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines Undo spamage of last MFC. r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines _ALIGN has to return u_long, since pointers don't fit into u_int in 64-bit mips. r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines - Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe. Context info could be obtained from other sources (see below) no only from td_pcb field - Do not show a0..a3 values unless they're obtained from the stack. These are only confirmed values. - Fix bt command in DDB. Previous implementation used thread's trapframe structure as a source info for trace unwinding, but this structure is filled only when exception occurs. Valid register values for sleeping processes are in pcb_context array. For curthread use pc/sp/ra for current frame r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines - Get rid of label_t. It came from NetBSD and was used only in one place r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines - Move stack tracing function to db_trace.c - Axe unused extern MipsXXX declarations - Move all declarations for functions in exceptions.S/swtch.S from trap.c to respective headers r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines - Sync caches properly when dealing with sf_buf r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines (u_int) is the wrong type here. Use unsigned long instead, even though that's only less wrong... r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines Use unsigned long instead of unsigned for the integer casts here. The former works for both ILP32 and LP64 programming models, while the latter fails LP64. r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines - Make i/d cache size field 32-bit to prevent overflow Submited by: Neelkanth Natu r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines fix prototype for MipsEmulateBranch. r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines Better definitions for a few types for n32/n64. r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines Fixed aligned macros... r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines - Port busdma code from FreeBSD/arm. This is more mature version that takes into account all limitation to DMA memory (boundaries, alignment) and implements bounce pages. - Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines Fix atomic_store_64 prototype for 64-bit systems. r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines The MCOUNT macro isn't going to work in 64-bit mode. Add a note to this effect. r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines Provide a macro for PTR_ADDU as well. We may need to implement this differently for N32... Use PTR_ADDU in DO_AST macro. r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines Change the addu here to daddu. addu paranoina prodded by: jmallet@ r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines addu and subu are special. We need to use daddu and dsubu here to get proper behavior. Submitted by: jmallet@ r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines The SB1 has cohernet memory, so add it. Also, Maxmem is better as a long. Submitted by: Neelkanth Natu r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines The SB1 needs a special value for the cache field of the pte. Submitted by: Neelkanth Natu r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines compute the areas to save registers in for 64-bit access correctly. r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines First cut at 64-bit types. not 100% sure these are all correct for N32 ABI. r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines Trim unreferenced goo. SDRAM likely should be next, but it is still referenced. r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines First cut at atomics for 64-bit machines and SMP machines. # Note: Cavium provided a port that has atomics similar to these, but # that does a syncw; sync; atomic; sync; syncw where we just do the classic # mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why # the extra is needed. Since my initial target is one core, I'll defer # investigation until I bring up multiple cores. syncw is an octeon specific # instruction. r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines Bring in cdefs.h from NetBSD to define ABI goo. Obtained from: NetBSD r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA, ala sgi, and use it in preference to a bare 'la' so that it gets translated to a 'dla' for the 64-bit pointer ABIs. r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines Use uintptr_t rather than unsigned here for 64-bit correctness. r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe this is correct. While registers are 64-bit, n32 is a 32-bit ABI and lives in a 32-bit world (with explicit 64-bit registers, however). Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4 + SZREG' to reflect the actual offset of the structure in question. r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines (1) Use uintptr_t in preference to unsigned. The latter isn't right for 64-bit case, while the former is. (2) include a SB1 specific coherency mapping Submitted by: Neelkanth Nath (2) r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines db_expr_t should be a intptr_t, not an int. These expressions can be addresses or numbers, and that's a intptr_t if I ever saw one. r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines Define COP0_SYNC for SB1 CPU. Submitted by: Neelkanth Natu r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines Switch to ABI agnostic ta0-ta3. Provide defs for this in the right places. Provide n32/n64 register name defintions. This should have no effect for the O32 builds that everybody else uses, but should help make N64 builds possible (lots of other changes are needed for that). Obtained from: NetBSD (for the regdef.h changes) r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines - Add support for handling TLS area address in kernel space. From the userland point of view get/set operations are performed using sysarch(2) call. r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines - Add guards to ensure that these files are included only once r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines - Mark temp variable as "earlyclobber" in assembler inline in atomic_fetchadd_32. Without it gcc would use it as input register for v and sometimes generate following code for function call like atomic_fetchadd_32(&(fp)->f_count, -1): 801238b4: 2402ffff li v0,-1 801238b8: c2230018 ll v1,24(s1) 801238bc: 00431021 addu v0,v0,v1 801238c0: e2220018 sc v0,24(s1) 801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8> 801238c8: 00000000 nop Which is definitly wrong because if sc fails v0 is set to 0 and previous value of -1 is overriden hence whole operation turns to bogus r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines bye bye. This is no longer referenced, but much code from it will resurface for a bus-space implementation. r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines Cavium-specific goo is no longer necessary here. Of course, I now have to write a bus space for cavium, but that shouldn't be too hard. r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines Move this to a more approrpiate plae. r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines Bring this in from the cavium port. r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines - Use restoreintr instead of enableint while accessing pcpu in DO_AST r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines - Add type cast for atomic_cmpset_acq_ptr arguments r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines - Remove now unused NetBSDism intr.h r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines - Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR macroses thet check if address belongs to KSEG0, KSEG1 or both of them respectively. r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines - Cast argument to proper type in order to avoid warnings like "shift value is too large for given type" r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines - Use naming convention the same as MIPS spec does: eliminate _sel1 sufix and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1 - Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes) r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines - Define accessor functions for CP0 Config(16) register selects 1, 2, 3. Content of these registers is defined in MIPS spec and can be used for obtaining info about CPU capabilities. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 19:50:24 +00:00
#else
#define __ELF_WORD_SIZE 32
#endif
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines Get the sense of this right. We use uintpr_t for bus_addr_t when we're building everything except octeon && 32-bit. As note before, we need a clearner way, but at least now the hack is right. r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines Add in Cavium's CID. Report what the unknown CID is. r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON. Spell ld script name right. r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines Another kludge for 64-bit bus_addr_t with 32-bit pointers... r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines - Add cpu_init_interrupts function that is supposed to prepeare stuff required for spinning out interrupts later - Add API for managing intrcnt/intrnames arrays - Some minor style(9) fixes r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines For XLR adds extern for its bus space routines r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines Add some newer MIPS CO cores. r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines db_expr_t is really closer to a register_t. Submitted by: bde@ r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines - Remove bunch of declared but not defined cach-related variables - Add mips_picache_linesize and mips_pdcache_linesize variables r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines Get rid of the hardcoded constants to define cacheable memory: SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE Instead we now keep a copy of the memory regions enumerated by platform-specific code and use that to determine whether an address is cacheable or not. r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines - Commit missing part of "bt" fix: store PC register in pcb_context struct in cpu_switch and use it in stack_trace function later. pcb_regs contains state of the process stored by exception handler and therefor is not valid for sleeping processes. r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines Undo spamage of last MFC. r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines _ALIGN has to return u_long, since pointers don't fit into u_int in 64-bit mips. r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines - Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe. Context info could be obtained from other sources (see below) no only from td_pcb field - Do not show a0..a3 values unless they're obtained from the stack. These are only confirmed values. - Fix bt command in DDB. Previous implementation used thread's trapframe structure as a source info for trace unwinding, but this structure is filled only when exception occurs. Valid register values for sleeping processes are in pcb_context array. For curthread use pc/sp/ra for current frame r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines - Get rid of label_t. It came from NetBSD and was used only in one place r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines - Move stack tracing function to db_trace.c - Axe unused extern MipsXXX declarations - Move all declarations for functions in exceptions.S/swtch.S from trap.c to respective headers r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines - Sync caches properly when dealing with sf_buf r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines (u_int) is the wrong type here. Use unsigned long instead, even though that's only less wrong... r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines Use unsigned long instead of unsigned for the integer casts here. The former works for both ILP32 and LP64 programming models, while the latter fails LP64. r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines - Make i/d cache size field 32-bit to prevent overflow Submited by: Neelkanth Natu r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines fix prototype for MipsEmulateBranch. r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines Better definitions for a few types for n32/n64. r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines Fixed aligned macros... r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines - Port busdma code from FreeBSD/arm. This is more mature version that takes into account all limitation to DMA memory (boundaries, alignment) and implements bounce pages. - Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines Fix atomic_store_64 prototype for 64-bit systems. r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines The MCOUNT macro isn't going to work in 64-bit mode. Add a note to this effect. r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines Provide a macro for PTR_ADDU as well. We may need to implement this differently for N32... Use PTR_ADDU in DO_AST macro. r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines Change the addu here to daddu. addu paranoina prodded by: jmallet@ r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines addu and subu are special. We need to use daddu and dsubu here to get proper behavior. Submitted by: jmallet@ r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines The SB1 has cohernet memory, so add it. Also, Maxmem is better as a long. Submitted by: Neelkanth Natu r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines The SB1 needs a special value for the cache field of the pte. Submitted by: Neelkanth Natu r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines compute the areas to save registers in for 64-bit access correctly. r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines First cut at 64-bit types. not 100% sure these are all correct for N32 ABI. r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines Trim unreferenced goo. SDRAM likely should be next, but it is still referenced. r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines First cut at atomics for 64-bit machines and SMP machines. # Note: Cavium provided a port that has atomics similar to these, but # that does a syncw; sync; atomic; sync; syncw where we just do the classic # mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why # the extra is needed. Since my initial target is one core, I'll defer # investigation until I bring up multiple cores. syncw is an octeon specific # instruction. r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines Bring in cdefs.h from NetBSD to define ABI goo. Obtained from: NetBSD r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA, ala sgi, and use it in preference to a bare 'la' so that it gets translated to a 'dla' for the 64-bit pointer ABIs. r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines Use uintptr_t rather than unsigned here for 64-bit correctness. r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe this is correct. While registers are 64-bit, n32 is a 32-bit ABI and lives in a 32-bit world (with explicit 64-bit registers, however). Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4 + SZREG' to reflect the actual offset of the structure in question. r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines (1) Use uintptr_t in preference to unsigned. The latter isn't right for 64-bit case, while the former is. (2) include a SB1 specific coherency mapping Submitted by: Neelkanth Nath (2) r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines db_expr_t should be a intptr_t, not an int. These expressions can be addresses or numbers, and that's a intptr_t if I ever saw one. r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines Define COP0_SYNC for SB1 CPU. Submitted by: Neelkanth Natu r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines Switch to ABI agnostic ta0-ta3. Provide defs for this in the right places. Provide n32/n64 register name defintions. This should have no effect for the O32 builds that everybody else uses, but should help make N64 builds possible (lots of other changes are needed for that). Obtained from: NetBSD (for the regdef.h changes) r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines - Add support for handling TLS area address in kernel space. From the userland point of view get/set operations are performed using sysarch(2) call. r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines - Add guards to ensure that these files are included only once r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines - Mark temp variable as "earlyclobber" in assembler inline in atomic_fetchadd_32. Without it gcc would use it as input register for v and sometimes generate following code for function call like atomic_fetchadd_32(&(fp)->f_count, -1): 801238b4: 2402ffff li v0,-1 801238b8: c2230018 ll v1,24(s1) 801238bc: 00431021 addu v0,v0,v1 801238c0: e2220018 sc v0,24(s1) 801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8> 801238c8: 00000000 nop Which is definitly wrong because if sc fails v0 is set to 0 and previous value of -1 is overriden hence whole operation turns to bogus r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines bye bye. This is no longer referenced, but much code from it will resurface for a bus-space implementation. r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines Cavium-specific goo is no longer necessary here. Of course, I now have to write a bus space for cavium, but that shouldn't be too hard. r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines Move this to a more approrpiate plae. r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines Bring this in from the cavium port. r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines - Use restoreintr instead of enableint while accessing pcpu in DO_AST r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines - Add type cast for atomic_cmpset_acq_ptr arguments r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines - Remove now unused NetBSDism intr.h r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines - Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR macroses thet check if address belongs to KSEG0, KSEG1 or both of them respectively. r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines - Cast argument to proper type in order to avoid warnings like "shift value is too large for given type" r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines - Use naming convention the same as MIPS spec does: eliminate _sel1 sufix and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1 - Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes) r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines - Define accessor functions for CP0 Config(16) register selects 1, 2, 3. Content of these registers is defined in MIPS spec and can be used for obtaining info about CPU capabilities. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 19:50:24 +00:00
#endif
#include <sys/elf32.h>
#include <sys/elf64.h>
#include <sys/elf_generic.h>
#define ELF_ARCH EM_MIPS
#define ELF_ARCH32 EM_MIPS
/* Define "machine" characteristics */
#if __ELF_WORD_SIZE == 32
#define ELF_TARG_CLASS ELFCLASS32
#else
#define ELF_TARG_CLASS ELFCLASS64
#endif
#ifdef __MIPSEB__
#define ELF_TARG_DATA ELFDATA2MSB
#else
#define ELF_TARG_DATA ELFDATA2LSB
#endif
#define ELF_TARG_MACH EM_MIPS
#define ELF_TARG_VER 1
/*
* Auxiliary vector entries for passing information to the interpreter.
*
* The i386 supplement to the SVR4 ABI specification names this "auxv_t",
* but POSIX lays claim to all symbols ending with "_t".
*/
typedef struct { /* Auxiliary vector entry on initial stack */
int a_type; /* Entry type. */
union {
int a_val; /* Integer value. */
void *a_ptr; /* Address. */
void (*a_fcn)(void); /* Function pointer (not used). */
} a_un;
} Elf32_Auxinfo;
typedef struct { /* Auxiliary vector entry on initial stack */
long a_type; /* Entry type. */
union {
long a_val; /* Integer value. */
void *a_ptr; /* Address. */
void (*a_fcn)(void); /* Function pointer (not used). */
} a_un;
} Elf64_Auxinfo;
__ElfType(Auxinfo);
/* Values for a_type. */
#define AT_NULL 0 /* Terminates the vector. */
#define AT_IGNORE 1 /* Ignored entry. */
#define AT_EXECFD 2 /* File descriptor of program to load. */
#define AT_PHDR 3 /* Program header of program already loaded. */
#define AT_PHENT 4 /* Size of each program header entry. */
#define AT_PHNUM 5 /* Number of program header entries. */
#define AT_PAGESZ 6 /* Page size in bytes. */
#define AT_BASE 7 /* Interpreter's base address. */
#define AT_FLAGS 8 /* Flags (unused for i386). */
#define AT_ENTRY 9 /* Where interpreter should transfer control. */
#define AT_NOTELF 10 /* Program is not ELF ?? */
#define AT_UID 11 /* Real uid. */
#define AT_EUID 12 /* Effective uid. */
#define AT_GID 13 /* Real gid. */
#define AT_EGID 14 /* Effective gid. */
#define AT_EXECPATH 15 /* Path to the executable. */
#define AT_CANARY 16 /* Canary for SSP */
#define AT_CANARYLEN 17 /* Length of the canary. */
#define AT_OSRELDATE 18 /* OSRELDATE. */
#define AT_NCPUS 19 /* Number of CPUs. */
#define AT_PAGESIZES 20 /* Pagesizes. */
#define AT_PAGESIZESLEN 21 /* Number of pagesizes. */
#define AT_TIMEKEEP 22 /* Pointer to timehands. */
#define AT_STACKPROT 23 /* Initial stack protection. */
#define AT_COUNT 24 /* Count of defined aux entry types. */
#define ET_DYN_LOAD_ADDR 0x0120000
/*
* Constant to mark start of symtab/strtab saved by trampoline
*/
#define SYMTAB_MAGIC 0x64656267
/* from NetBSD's sys/mips/include/elf_machdep.h $NetBSD: elf_machdep.h,v 1.18 2013/05/23 21:39:49 christos Exp $ */
/* mips relocs. */
#define R_MIPS_NONE 0
#define R_MIPS_16 1
#define R_MIPS_32 2
#define R_MIPS_REL32 3
#define R_MIPS_REL R_MIPS_REL32
#define R_MIPS_26 4
#define R_MIPS_HI16 5 /* high 16 bits of symbol value */
#define R_MIPS_LO16 6 /* low 16 bits of symbol value */
#define R_MIPS_GPREL16 7 /* GP-relative reference */
#define R_MIPS_LITERAL 8 /* Reference to literal section */
#define R_MIPS_GOT16 9 /* Reference to global offset table */
#define R_MIPS_GOT R_MIPS_GOT16
#define R_MIPS_PC16 10 /* 16 bit PC relative reference */
#define R_MIPS_CALL16 11 /* 16 bit call thru glbl offset tbl */
#define R_MIPS_CALL R_MIPS_CALL16
#define R_MIPS_GPREL32 12
/* 13, 14, 15 are not defined at this point. */
#define R_MIPS_UNUSED1 13
#define R_MIPS_UNUSED2 14
#define R_MIPS_UNUSED3 15
/*
* The remaining relocs are apparently part of the 64-bit Irix ELF ABI.
*/
#define R_MIPS_SHIFT5 16
#define R_MIPS_SHIFT6 17
#define R_MIPS_64 18
#define R_MIPS_GOT_DISP 19
#define R_MIPS_GOT_PAGE 20
#define R_MIPS_GOT_OFST 21
#define R_MIPS_GOT_HI16 22
#define R_MIPS_GOT_LO16 23
#define R_MIPS_SUB 24
#define R_MIPS_INSERT_A 25
#define R_MIPS_INSERT_B 26
#define R_MIPS_DELETE 27
#define R_MIPS_HIGHER 28
#define R_MIPS_HIGHEST 29
#define R_MIPS_CALL_HI16 30
#define R_MIPS_CALL_LO16 31
#define R_MIPS_SCN_DISP 32
#define R_MIPS_REL16 33
#define R_MIPS_ADD_IMMEDIATE 34
#define R_MIPS_PJUMP 35
#define R_MIPS_RELGOT 36
#define R_MIPS_JALR 37
/* TLS relocations */
#define R_MIPS_TLS_DTPMOD32 38 /* Module number 32 bit */
#define R_MIPS_TLS_DTPREL32 39 /* Module-relative offset 32 bit */
#define R_MIPS_TLS_DTPMOD64 40 /* Module number 64 bit */
#define R_MIPS_TLS_DTPREL64 41 /* Module-relative offset 64 bit */
#define R_MIPS_TLS_GD 42 /* 16 bit GOT offset for GD */
#define R_MIPS_TLS_LDM 43 /* 16 bit GOT offset for LDM */
#define R_MIPS_TLS_DTPREL_HI16 44 /* Module-relative offset, high 16 bits */
#define R_MIPS_TLS_DTPREL_LO16 45 /* Module-relative offset, low 16 bits */
#define R_MIPS_TLS_GOTTPREL 46 /* 16 bit GOT offset for IE */
#define R_MIPS_TLS_TPREL32 47 /* TP-relative offset, 32 bit */
#define R_MIPS_TLS_TPREL64 48 /* TP-relative offset, 64 bit */
#define R_MIPS_TLS_TPREL_HI16 49 /* TP-relative offset, high 16 bits */
#define R_MIPS_TLS_TPREL_LO16 50 /* TP-relative offset, low 16 bits */
#define R_MIPS_max 51
#define R_TYPE(name) __CONCAT(R_MIPS_,name)
#define R_MIPS16_min 100
#define R_MIPS16_26 100
#define R_MIPS16_GPREL 101
#define R_MIPS16_GOT16 102
#define R_MIPS16_CALL16 103
#define R_MIPS16_HI16 104
#define R_MIPS16_LO16 105
#define R_MIPS16_max 106
#define R_MIPS_COPY 126
#define R_MIPS_JUMP_SLOT 127
/* mips dynamic tags */
#define DT_MIPS_RLD_VERSION 0x70000001
#define DT_MIPS_TIME_STAMP 0x70000002
#define DT_MIPS_ICHECKSUM 0x70000003
#define DT_MIPS_IVERSION 0x70000004
#define DT_MIPS_FLAGS 0x70000005
#define DT_MIPS_BASE_ADDRESS 0x70000006
#define DT_MIPS_CONFLICT 0x70000008
#define DT_MIPS_LIBLIST 0x70000009
#define DT_MIPS_CONFLICTNO 0x7000000b
#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* number of local got ents */
#define DT_MIPS_LIBLISTNO 0x70000010
#define DT_MIPS_SYMTABNO 0x70000011 /* number of .dynsym entries */
#define DT_MIPS_UNREFEXTNO 0x70000012
#define DT_MIPS_GOTSYM 0x70000013 /* first dynamic sym in got */
#define DT_MIPS_HIPAGENO 0x70000014
#define DT_MIPS_RLD_MAP 0x70000016 /* address of loader map */
#define DT_MIPS_PLTGOT 0x70000032
#define DT_MIPS_RWPLT 0x70000034
/*
* ELF Flags
*/
#define EF_MIPS_PIC 0x00000002 /* Contains PIC code */
#define EF_MIPS_CPIC 0x00000004 /* STD PIC calling sequence */
#define EF_MIPS_ABI2 0x00000020 /* N32 */
#define EF_MIPS_ARCH_ASE 0x0f000000 /* Architectural extensions */
#define EF_MIPS_ARCH_MDMX 0x08000000 /* MDMX multimedia extension */
#define EF_MIPS_ARCH_M16 0x04000000 /* MIPS-16 ISA extensions */
#define EF_MIPS_ARCH 0xf0000000 /* Architecture field */
#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code */
#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code */
#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code */
#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code */
#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code */
#define EF_MIPS_ARCH_32 0x50000000 /* -mips32 code */
#define EF_MIPS_ARCH_64 0x60000000 /* -mips64 code */
#define EF_MIPS_ARCH_32R2 0x70000000 /* -mips32r2 code */
#define EF_MIPS_ARCH_64R2 0x80000000 /* -mips64r2 code */
#define EF_MIPS_ABI 0x0000f000
#define EF_MIPS_ABI_O32 0x00001000
#define EF_MIPS_ABI_O64 0x00002000
#define EF_MIPS_ABI_EABI32 0x00003000
#define EF_MIPS_ABI_EABI64 0x00004000
#endif /* __MIPS_ELF_H */