2009-01-26 14:00:50 +00:00
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.\"
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.\" Copyright (C) 2008-2009 Semihalf, Michal Hajduk and Bartlomiej Sieka
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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2012-03-29 05:02:12 +00:00
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.\" $FreeBSD$
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2009-01-26 14:00:50 +00:00
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.\"
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2009-11-02 12:35:38 +00:00
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.Dd January 23, 2009
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2009-01-26 14:00:50 +00:00
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.Dt I2C 8
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.Os
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.Sh NAME
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.Nm i2c
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2012-03-29 05:02:12 +00:00
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.Nd test I2C bus and slave devices
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2009-01-26 14:00:50 +00:00
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.Sh SYNOPSIS
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.Nm
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.Cm -a Ar address
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.Op Fl f Ar device
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.Op Fl d Ar r|w
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.Op Fl w Ar 0|8|16
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.Op Fl o Ar offset
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.Op Fl c Ar count
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.Op Fl m Ar ss|rs|no
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.Op Fl b
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.Op Fl v
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.Nm
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.Cm -s
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.Op Fl f Ar device
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.Op Fl n Ar skip_addr
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.Op Fl v
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.Nm
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.Cm -r
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.Op Fl f Ar device
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.Op Fl v
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.Sh DESCRIPTION
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The
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.Nm
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utility can be used to perform raw data transfers (read or write) with devices
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on the I2C bus. It can also scan the bus for available devices and reset the
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I2C controller.
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.Pp
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The options are as follows:
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.Bl -tag -width ".Fl d Ar direction"
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.It Fl a Ar address
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7-bit address on the I2C device to operate on (hex).
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.It Fl b
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binary mode - when performing a read operation, the data read from the device
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is output in binary format on stdout; when doing a write, the binary data to
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be written to the device is read from stdin.
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.It Fl c Ar count
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number of bytes to transfer (dec).
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.It Fl d Ar r|w
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transfer direction: r - read, w - write.
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.It Fl f Ar device
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I2C bus to use (default is /dev/iic0).
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.It Fl m Ar ss|rs|no
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addressing mode, i.e., I2C bus operations performed after the offset for the
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transfer has been written to the device and before the actual read/write
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operation. rs - repeated start; ss - stop start; no - none.
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.It Fl n Ar skip_addr
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skip address - address(es) to be skipped during bus scan.
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2010-08-16 15:18:30 +00:00
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There are two ways to specify addresses to ignore: by range 'a..b' or
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2009-01-26 14:00:50 +00:00
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using selected addresses 'a:b:c'. This option is available only when "-s" is
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used.
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.It Fl o Ar offset
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offset within the device for data transfer (hex).
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.It Fl r
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reset the controller.
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.It Fl s
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scan the bus for devices.
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.It Fl v
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2012-05-24 02:24:03 +00:00
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be verbose.
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2009-01-26 14:00:50 +00:00
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.It Fl w Ar 0|8|16
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device addressing width (in bits).
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.El
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.Sh WARNINGS
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Great care must be taken when manipulating slave I2C devices with the
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.Nm
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utility. Often times important configuration data for the system is kept in
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non-volatile but write enabled memories located on the I2C bus, for example
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Ethernet hardware addresses, RAM module parameters (SPD), processor reset
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configuration word etc.
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.Pp
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It is very easy to render the whole system unusable when such configuration
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data is deleted or altered, so use the
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.Dq -d w
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(write) command only if you know exactly what you are doing.
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.Pp
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Also avoid ungraceful interrupting of an ongoing transaction on the I2C bus,
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as it can lead to potentially dangerous effects. Consider the following
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scenario: when the host CPU is reset (for whatever reason) in the middle of a
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started I2C transaction, the I2C slave device could be left in write mode
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waiting for data or offset to arrive. When the CPU reinitializes itself and
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talks to this I2C slave device again, the commands and other control info it
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sends are treated by the slave device as data or offset it was waiting for,
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and there's great potential for corruption if such a write is performed.
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.Sh EXAMPLES
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.Bl -bullet
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.It
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Scan the default bus (/dev/iic0) for devices:
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.Pp
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i2c -s
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.It
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2012-03-29 05:02:12 +00:00
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Scan the default bus (/dev/iic0) for devices and skip addresses 0x56 and
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2009-01-26 14:00:50 +00:00
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0x45.
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.Pp
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i2c -s -n 0x56:0x45
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.It
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2012-03-29 05:02:12 +00:00
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Scan the default bus (/dev/iic0) for devices and skip address range
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2009-01-26 14:00:50 +00:00
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0x34 to 0x56.
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.Pp
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i2c -s -n 0x34..0x56
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.It
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Read 8 bytes of data from device at address 0x56 (e.g., an EEPROM):
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.Pp
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i2c -a 0x56 -d r -c 8
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.It
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Write 16 bytes of data from file data.bin to device 0x56 at offset 0x10:
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.Pp
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i2c -a 0x56 -d w -c 16 -o 0x10 -b < data.bin
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.It
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Copy 4 bytes between two EEPROMs (0x56 on /dev/iic1 to 0x57 on /dev/iic0):
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.Pp
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i2c -a 0x56 -f /dev/iic1 -d r -c 0x4 -b | i2c -a 0x57 -f /dev/iic0 -d w -c 4 -b
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.It
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Reset the controller:
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.Pp
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i2c -f /dev/iic1 -r
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.El
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.Sh SEE ALSO
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.Xr iic 4 ,
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.Xr iicbus 4
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.Sh HISTORY
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The
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.Nm
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utility appeared in
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.Fx 8.0 .
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.Sh AUTHORS
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.An -nosplit
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The
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.Nm
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utility and this manual page were written by
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.An Bartlomiej Sieka
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.Aq tur@semihalf.com
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2012-03-29 05:02:12 +00:00
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and
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2009-01-26 14:00:50 +00:00
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.An Michal Hajduk
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.Aq mih@semihalf.com .
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