rtwn(4), urtwn(4): merge common code, add support for 11ac devices.
All devices:
- add support for rate adaptation via ieee80211_amrr(9);
- use short preamble for transmitted frames when needed;
- multi-bss support:
* for RTL8821AU: 2 VAPs at the same time;
* other: 1 any VAP + 1 sta VAP.
RTL8188CE:
- fix IQ calibration bug (reason of significant speed degradation);
- add h/w crypto acceleration support.
USB:
- A-MPDU Tx support;
- short GI support;
Other:
- add support for RTL8812AU / RTL8821AU chipsets
(a/b/g/n only; no ac yet);
- split merged code into subparts:
* bus glue (usb/*, pci/*, rtl*/usb/*, rtl*/pci/*)
* common (if_rtwn*)
* chip-specific (rtl*/*)
- various other bugfixes.
Due to code reorganization, module names / requirements were changed too:
urtwn urtwnfw -> rtwn rtwn_usb rtwnfw
rtwn rtwnfw -> rtwn rtwn_pci rtwnfw
Tested with RTL8188CE, RTL8188CUS, RTL8188EU and RTL8821AU.
Tested by: kevlo, garga,
Peter Garshtja <peter.garshtja@ambient-md.com>,
Kevin McAleavey <kevin.mcaleavey@knosproject.com>,
Ilias-Dimitrios Vrachnis <id@vrachnis.com>,
<otacilio.neto@bsd.com.br>
Relnotes: yes
2016-10-17 20:38:24 +00:00
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/*-
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* Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef R12A_REG_H
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#define R12A_REG_H
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#include <dev/rtwn/rtl8188e/r88e_reg.h>
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/*
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* MAC registers.
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*/
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/* System Configuration. */
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#define R12A_SDIO_CTRL 0x070
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#define R12A_RF_B_CTRL 0x076
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/* Rx DMA Configuration. */
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#define R12A_RXDMA_PRO 0x290
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#define R12A_EARLY_MODE_CONTROL 0x2bc
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/* Protocol Configuration. */
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#define R12A_TXPKT_EMPTY 0x41a
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#define R12A_ARFR_5G(i) (0x444 + (i) * 8)
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#define R12A_CCK_CHECK 0x454
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#define R12A_AMPDU_MAX_TIME 0x456
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#define R12A_AMPDU_MAX_LENGTH R92C_AGGLEN_LMT
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#define R12A_DATA_SEC 0x483
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#define R12A_ARFR_2G(i) (0x48c + (i) * 8)
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#define R12A_HT_SINGLE_AMPDU 0x4c7
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/* Bits for R92C_MAC_PHY_CTRL. */
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#define R12A_MAC_PHY_CRYSTALCAP_M 0x7ff80000
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#define R12A_MAC_PHY_CRYSTALCAP_S 19
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/* Bits for R92C_LEDCFG2. */
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#define R12A_LEDCFG2_ENA 0x20
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2018-06-19 00:38:28 +00:00
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/* Bits for R12A_RXDMA_PRO. */
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#define R12A_DMA_MODE 0x02
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#define R12A_BURST_CNT_M 0x0c
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#define R12A_BURST_CNT_S 2
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#define R12A_BURST_SZ_M 0x30
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#define R12A_BURST_SZ_S 4
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#define R12A_BURST_SZ_USB3 0
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#define R12A_BURST_SZ_USB2 1
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#define R12A_BURST_SZ_USB1 2
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rtwn(4), urtwn(4): merge common code, add support for 11ac devices.
All devices:
- add support for rate adaptation via ieee80211_amrr(9);
- use short preamble for transmitted frames when needed;
- multi-bss support:
* for RTL8821AU: 2 VAPs at the same time;
* other: 1 any VAP + 1 sta VAP.
RTL8188CE:
- fix IQ calibration bug (reason of significant speed degradation);
- add h/w crypto acceleration support.
USB:
- A-MPDU Tx support;
- short GI support;
Other:
- add support for RTL8812AU / RTL8821AU chipsets
(a/b/g/n only; no ac yet);
- split merged code into subparts:
* bus glue (usb/*, pci/*, rtl*/usb/*, rtl*/pci/*)
* common (if_rtwn*)
* chip-specific (rtl*/*)
- various other bugfixes.
Due to code reorganization, module names / requirements were changed too:
urtwn urtwnfw -> rtwn rtwn_usb rtwnfw
rtwn rtwnfw -> rtwn rtwn_pci rtwnfw
Tested with RTL8188CE, RTL8188CUS, RTL8188EU and RTL8821AU.
Tested by: kevlo, garga,
Peter Garshtja <peter.garshtja@ambient-md.com>,
Kevin McAleavey <kevin.mcaleavey@knosproject.com>,
Ilias-Dimitrios Vrachnis <id@vrachnis.com>,
<otacilio.neto@bsd.com.br>
Relnotes: yes
2016-10-17 20:38:24 +00:00
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/* Bits for R12A_CCK_CHECK. */
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#define R12A_CCK_CHECK_BCN1 0x20
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#define R12A_CCK_CHECK_5GHZ 0x80
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/* Bits for R12A_DATA_SEC. */
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#define R12A_DATA_SEC_NO_EXT 0x00
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#define R12A_DATA_SEC_PRIM_UP_20 0x01
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#define R12A_DATA_SEC_PRIM_DOWN_20 0x02
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#define R12A_DATA_SEC_PRIM_UPPER_20 0x03
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#define R12A_DATA_SEC_PRIM_LOWER_20 0x04
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#define R12A_DATA_SEC_PRIM_UP_40 0x90
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#define R12A_DATA_SEC_PRIM_DOWN_40 0xa0
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/* Bits for R12A_HT_SINGLE_AMPDU. */
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#define R12A_HT_SINGLE_AMPDU_PKT_ENA 0x80
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/* Bits for R92C_RCR. */
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#define R12A_RCR_DIS_CHK_14 0x00200000
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#define R12A_RCR_TCP_OFFLD_EN 0x02000000
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#define R12A_RCR_VHT_ACK 0x04000000
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/*
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* Baseband registers.
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*/
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#define R12A_CCK_RPT_FORMAT 0x804
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#define R12A_OFDMCCK_EN 0x808
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#define R12A_RX_PATH R12A_OFDMCCK_EN
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#define R12A_TX_PATH 0x80c
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#define R12A_TXAGC_TABLE_SELECT 0x82c
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#define R12A_PWED_TH 0x830
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#define R12A_BW_INDICATION 0x834
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#define R12A_CCA_ON_SEC 0x838
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#define R12A_L1_PEAK_TH 0x848
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#define R12A_FC_AREA 0x860
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#define R12A_RFMOD 0x8ac
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#define R12A_HSSI_PARAM2 0x8b0
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#define R12A_ADC_BUF_CLK 0x8c4
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#define R12A_ANTSEL_SW 0x900
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#define R12A_SINGLETONE_CONT_TX 0x914
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#define R12A_CCK_RX_PATH 0xa04
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#define R12A_HSSI_PARAM1(chain) (0xc00 + (chain) * 0x200)
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#define R12A_TX_SCALE(chain) (0xc1c + (chain) * 0x200)
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#define R12A_TXAGC_CCK11_1(chain) (0xc20 + (chain) * 0x200)
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#define R12A_TXAGC_OFDM18_6(chain) (0xc24 + (chain) * 0x200)
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#define R12A_TXAGC_OFDM54_24(chain) (0xc28 + (chain) * 0x200)
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#define R12A_TXAGC_MCS3_0(chain) (0xc2c + (chain) * 0x200)
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#define R12A_TXAGC_MCS7_4(chain) (0xc30 + (chain) * 0x200)
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#define R12A_TXAGC_MCS11_8(chain) (0xc34 + (chain) * 0x200)
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#define R12A_TXAGC_MCS15_12(chain) (0xc38 + (chain) * 0x200)
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#define R12A_TXAGC_NSS1IX3_1IX0(chain) (0xc3c + (chain) * 0x200)
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#define R12A_TXAGC_NSS1IX7_1IX4(chain) (0xc40 + (chain) * 0x200)
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#define R12A_TXAGC_NSS2IX1_1IX8(chain) (0xc44 + (chain) * 0x200)
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#define R12A_TXAGC_NSS2IX5_2IX2(chain) (0xc48 + (chain) * 0x200)
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#define R12A_TXAGC_NSS2IX9_2IX6(chain) (0xc4c + (chain) * 0x200)
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#define R12A_INITIAL_GAIN(chain) (0xc50 + (chain) * 0x200)
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#define R12A_AFE_POWER_1(chain) (0xc60 + (chain) * 0x200)
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#define R12A_AFE_POWER_2(chain) (0xc64 + (chain) * 0x200)
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#define R12A_SLEEP_NAV(chain) (0xc80 + (chain) * 0x200)
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#define R12A_PMPD(chain) (0xc84 + (chain) * 0x200)
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#define R12A_LSSI_PARAM(chain) (0xc90 + (chain) * 0x200)
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#define R12A_RFE_PINMUX(chain) (0xcb0 + (chain) * 0x200)
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#define R12A_RFE_INV(chain) (0xcb4 + (chain) * 0x200)
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#define R12A_RFE(chain) (0xcb8 + (chain) * 0x200)
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#define R12A_HSPI_READBACK(chain) (0xd04 + (chain) * 0x40)
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#define R12A_LSSI_READBACK(chain) (0xd08 + (chain) * 0x40)
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/* Bits for R12A_CCK_RPT_FORMAT. */
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#define R12A_CCK_RPT_FORMAT_HIPWR 0x00010000
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/* Bits for R12A_OFDMCCK_EN. */
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#define R12A_OFDMCCK_EN_CCK 0x10000000
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#define R12A_OFDMCCK_EN_OFDM 0x20000000
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/* Bits for R12A_CCA_ON_SEC. */
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#define R12A_CCA_ON_SEC_EXT_CHAN_M 0xf0000000
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#define R12A_CCA_ON_SEC_EXT_CHAN_S 28
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/* Bits for R12A_RFE_PINMUX(i). */
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#define R12A_RFE_PINMUX_PA_A_MASK 0x000000f0
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#define R12A_RFE_PINMUX_LNA_MASK 0x0000f000
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/* Bits for R12A_RFMOD. */
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#define R12A_RFMOD_EXT_CHAN_M 0x3C
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#define R12A_RFMOD_EXT_CHAN_S 2
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/* Bits for R12A_HSSI_PARAM2. */
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#define R12A_HSSI_PARAM2_READ_ADDR_MASK 0xff
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/* Bits for R12A_HSSI_PARAM1(i). */
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#define R12A_HSSI_PARAM1_PI 0x00000004
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/* Bits for R12A_TX_SCALE(i). */
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#define R12A_TX_SCALE_SWING_M 0xffe00000
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#define R12A_TX_SCALE_SWING_S 21
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/* Bits for R12A_TXAGC_CCK11_1(i). */
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#define R12A_TXAGC_CCK1_M 0x000000ff
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#define R12A_TXAGC_CCK1_S 0
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#define R12A_TXAGC_CCK2_M 0x0000ff00
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#define R12A_TXAGC_CCK2_S 8
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#define R12A_TXAGC_CCK55_M 0x00ff0000
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#define R12A_TXAGC_CCK55_S 16
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#define R12A_TXAGC_CCK11_M 0xff000000
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#define R12A_TXAGC_CCK11_S 24
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/* Bits for R12A_TXAGC_OFDM18_6(i). */
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#define R12A_TXAGC_OFDM06_M 0x000000ff
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#define R12A_TXAGC_OFDM06_S 0
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#define R12A_TXAGC_OFDM09_M 0x0000ff00
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#define R12A_TXAGC_OFDM09_S 8
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#define R12A_TXAGC_OFDM12_M 0x00ff0000
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#define R12A_TXAGC_OFDM12_S 16
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#define R12A_TXAGC_OFDM18_M 0xff000000
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#define R12A_TXAGC_OFDM18_S 24
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/* Bits for R12A_TXAGC_OFDM54_24(i). */
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#define R12A_TXAGC_OFDM24_M 0x000000ff
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#define R12A_TXAGC_OFDM24_S 0
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#define R12A_TXAGC_OFDM36_M 0x0000ff00
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#define R12A_TXAGC_OFDM36_S 8
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#define R12A_TXAGC_OFDM48_M 0x00ff0000
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#define R12A_TXAGC_OFDM48_S 16
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#define R12A_TXAGC_OFDM54_M 0xff000000
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#define R12A_TXAGC_OFDM54_S 24
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/* Bits for R12A_TXAGC_MCS3_0(i). */
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#define R12A_TXAGC_MCS0_M 0x000000ff
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#define R12A_TXAGC_MCS0_S 0
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#define R12A_TXAGC_MCS1_M 0x0000ff00
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#define R12A_TXAGC_MCS1_S 8
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#define R12A_TXAGC_MCS2_M 0x00ff0000
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#define R12A_TXAGC_MCS2_S 16
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#define R12A_TXAGC_MCS3_M 0xff000000
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#define R12A_TXAGC_MCS3_S 24
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/* Bits for R12A_TXAGC_MCS7_4(i). */
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#define R12A_TXAGC_MCS4_M 0x000000ff
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#define R12A_TXAGC_MCS4_S 0
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#define R12A_TXAGC_MCS5_M 0x0000ff00
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#define R12A_TXAGC_MCS5_S 8
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#define R12A_TXAGC_MCS6_M 0x00ff0000
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#define R12A_TXAGC_MCS6_S 16
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#define R12A_TXAGC_MCS7_M 0xff000000
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#define R12A_TXAGC_MCS7_S 24
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/* Bits for R12A_TXAGC_MCS11_8(i). */
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#define R12A_TXAGC_MCS8_M 0x000000ff
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#define R12A_TXAGC_MCS8_S 0
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#define R12A_TXAGC_MCS9_M 0x0000ff00
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#define R12A_TXAGC_MCS9_S 8
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#define R12A_TXAGC_MCS10_M 0x00ff0000
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#define R12A_TXAGC_MCS10_S 16
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#define R12A_TXAGC_MCS11_M 0xff000000
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#define R12A_TXAGC_MCS11_S 24
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/* Bits for R12A_TXAGC_MCS15_12(i). */
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#define R12A_TXAGC_MCS12_M 0x000000ff
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#define R12A_TXAGC_MCS12_S 0
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#define R12A_TXAGC_MCS13_M 0x0000ff00
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#define R12A_TXAGC_MCS13_S 8
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#define R12A_TXAGC_MCS14_M 0x00ff0000
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#define R12A_TXAGC_MCS14_S 16
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#define R12A_TXAGC_MCS15_M 0xff000000
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#define R12A_TXAGC_MCS15_S 24
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/*
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* RF (6052) registers.
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*/
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#define R12A_RF_LCK 0xb4
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/* Bits for R12A_RF_LCK. */
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#define R12A_RF_LCK_MODE 0x4000
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#endif /* R12A_REG_H */
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