Update to DRM CVS as of 2005-04-12, bringing many changes:
- Split core DRM routines back into their own module, rather than using the
nasty templated system like before.
- Development-class R300 support in radeon driver (requires userland pieces, of
course).
- Mach64 driver (haven't tested in a while -- my mach64s no longer fit in the
testbox). Covers Rage Pros, Rage Mobility P/M, Rage XL, and some others.
- i915 driver files, which just need to get drm_drv.c fixed to allow attachment
to the drmsub device. Covers i830 through i915 integrated graphics.
- savage driver files, which should require minimal changes to work. Covers the
Savage3D, Savage IX/MX, Savage 4, ProSavage.
- Support for color and texture tiling and HyperZ features of Radeon.
Thanks to: scottl (much p4 handholding)
Jung-uk Kim (helpful prodding)
PR: [1] kern/76879, [2] kern/72548
Submitted by: [1] Alex, lesha at intercaf dot ru
[2] Shaun Jurrens, shaun at shamz dot net
2005-04-16 03:44:47 +00:00
|
|
|
/* mach64_drm.h -- Public header for the mach64 driver -*- linux-c -*-
|
|
|
|
* Created: Thu Nov 30 20:04:32 2000 by gareth@valinux.com
|
2005-11-28 23:13:57 +00:00
|
|
|
*/
|
|
|
|
/*-
|
Update to DRM CVS as of 2005-04-12, bringing many changes:
- Split core DRM routines back into their own module, rather than using the
nasty templated system like before.
- Development-class R300 support in radeon driver (requires userland pieces, of
course).
- Mach64 driver (haven't tested in a while -- my mach64s no longer fit in the
testbox). Covers Rage Pros, Rage Mobility P/M, Rage XL, and some others.
- i915 driver files, which just need to get drm_drv.c fixed to allow attachment
to the drmsub device. Covers i830 through i915 integrated graphics.
- savage driver files, which should require minimal changes to work. Covers the
Savage3D, Savage IX/MX, Savage 4, ProSavage.
- Support for color and texture tiling and HyperZ features of Radeon.
Thanks to: scottl (much p4 handholding)
Jung-uk Kim (helpful prodding)
PR: [1] kern/76879, [2] kern/72548
Submitted by: [1] Alex, lesha at intercaf dot ru
[2] Shaun Jurrens, shaun at shamz dot net
2005-04-16 03:44:47 +00:00
|
|
|
* Copyright 2000 Gareth Hughes
|
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* Copyright 2002 Frank C. Earl
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* Copyright 2002-2003 Leif Delgass
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Gareth Hughes <gareth@valinux.com>
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* Frank C. Earl <fearl@airmail.net>
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* Leif Delgass <ldelgass@retinalburn.net>
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*/
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2005-11-28 23:13:57 +00:00
|
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|
#include <sys/cdefs.h>
|
|
|
|
__FBSDID("$FreeBSD$");
|
|
|
|
|
Update to DRM CVS as of 2005-04-12, bringing many changes:
- Split core DRM routines back into their own module, rather than using the
nasty templated system like before.
- Development-class R300 support in radeon driver (requires userland pieces, of
course).
- Mach64 driver (haven't tested in a while -- my mach64s no longer fit in the
testbox). Covers Rage Pros, Rage Mobility P/M, Rage XL, and some others.
- i915 driver files, which just need to get drm_drv.c fixed to allow attachment
to the drmsub device. Covers i830 through i915 integrated graphics.
- savage driver files, which should require minimal changes to work. Covers the
Savage3D, Savage IX/MX, Savage 4, ProSavage.
- Support for color and texture tiling and HyperZ features of Radeon.
Thanks to: scottl (much p4 handholding)
Jung-uk Kim (helpful prodding)
PR: [1] kern/76879, [2] kern/72548
Submitted by: [1] Alex, lesha at intercaf dot ru
[2] Shaun Jurrens, shaun at shamz dot net
2005-04-16 03:44:47 +00:00
|
|
|
#ifndef __MACH64_DRM_H__
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|
#define __MACH64_DRM_H__
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|
/* WARNING: If you change any of these defines, make sure to change the
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|
|
* defines in the Xserver file (mach64_sarea.h)
|
|
|
|
*/
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|
#ifndef __MACH64_SAREA_DEFINES__
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|
#define __MACH64_SAREA_DEFINES__
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/* What needs to be changed for the current vertex buffer?
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|
* GH: We're going to be pedantic about this. We want the card to do as
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|
* little as possible, so let's avoid having it fetch a whole bunch of
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* register values that don't change all that often, if at all.
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|
*/
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#define MACH64_UPLOAD_DST_OFF_PITCH 0x0001
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#define MACH64_UPLOAD_Z_OFF_PITCH 0x0002
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#define MACH64_UPLOAD_Z_ALPHA_CNTL 0x0004
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#define MACH64_UPLOAD_SCALE_3D_CNTL 0x0008
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#define MACH64_UPLOAD_DP_FOG_CLR 0x0010
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#define MACH64_UPLOAD_DP_WRITE_MASK 0x0020
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#define MACH64_UPLOAD_DP_PIX_WIDTH 0x0040
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#define MACH64_UPLOAD_SETUP_CNTL 0x0080
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#define MACH64_UPLOAD_MISC 0x0100
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#define MACH64_UPLOAD_TEXTURE 0x0200
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#define MACH64_UPLOAD_TEX0IMAGE 0x0400
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#define MACH64_UPLOAD_TEX1IMAGE 0x0800
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|
|
#define MACH64_UPLOAD_CLIPRECTS 0x1000 /* handled client-side */
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|
#define MACH64_UPLOAD_CONTEXT 0x00ff
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|
#define MACH64_UPLOAD_ALL 0x1fff
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/* DMA buffer size
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|
|
*/
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|
#define MACH64_BUFFER_SIZE 16384
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|
|
/* Max number of swaps allowed on the ring
|
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|
|
* before the client must wait
|
|
|
|
*/
|
2006-09-07 23:04:47 +00:00
|
|
|
#define MACH64_MAX_QUEUED_FRAMES 3U
|
Update to DRM CVS as of 2005-04-12, bringing many changes:
- Split core DRM routines back into their own module, rather than using the
nasty templated system like before.
- Development-class R300 support in radeon driver (requires userland pieces, of
course).
- Mach64 driver (haven't tested in a while -- my mach64s no longer fit in the
testbox). Covers Rage Pros, Rage Mobility P/M, Rage XL, and some others.
- i915 driver files, which just need to get drm_drv.c fixed to allow attachment
to the drmsub device. Covers i830 through i915 integrated graphics.
- savage driver files, which should require minimal changes to work. Covers the
Savage3D, Savage IX/MX, Savage 4, ProSavage.
- Support for color and texture tiling and HyperZ features of Radeon.
Thanks to: scottl (much p4 handholding)
Jung-uk Kim (helpful prodding)
PR: [1] kern/76879, [2] kern/72548
Submitted by: [1] Alex, lesha at intercaf dot ru
[2] Shaun Jurrens, shaun at shamz dot net
2005-04-16 03:44:47 +00:00
|
|
|
|
|
|
|
/* Byte offsets for host blit buffer data
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|
|
|
*/
|
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|
#define MACH64_HOSTDATA_BLIT_OFFSET 104
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|
|
/* Keep these small for testing.
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|
|
*/
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|
#define MACH64_NR_SAREA_CLIPRECTS 8
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#define MACH64_CARD_HEAP 0
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#define MACH64_AGP_HEAP 1
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#define MACH64_NR_TEX_HEAPS 2
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|
|
#define MACH64_NR_TEX_REGIONS 64
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|
#define MACH64_LOG_TEX_GRANULARITY 16
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#define MACH64_TEX_MAXLEVELS 1
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#define MACH64_NR_CONTEXT_REGS 15
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#define MACH64_NR_TEXTURE_REGS 4
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|
|
#endif /* __MACH64_SAREA_DEFINES__ */
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|
|
typedef struct {
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|
|
unsigned int dst_off_pitch;
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unsigned int z_off_pitch;
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|
unsigned int z_cntl;
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|
unsigned int alpha_tst_cntl;
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unsigned int scale_3d_cntl;
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unsigned int sc_left_right;
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unsigned int sc_top_bottom;
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unsigned int dp_fog_clr;
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unsigned int dp_write_mask;
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|
unsigned int dp_pix_width;
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|
|
unsigned int dp_mix;
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|
|
unsigned int dp_src;
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|
unsigned int clr_cmp_cntl;
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|
|
unsigned int gui_traj_cntl;
|
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|
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|
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|
|
unsigned int setup_cntl;
|
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|
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|
|
unsigned int tex_size_pitch;
|
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|
|
unsigned int tex_cntl;
|
|
|
|
unsigned int secondary_tex_off;
|
|
|
|
unsigned int tex_offset;
|
|
|
|
} drm_mach64_context_regs_t;
|
|
|
|
|
|
|
|
typedef struct drm_mach64_sarea {
|
|
|
|
/* The channel for communication of state information to the kernel
|
|
|
|
* on firing a vertex dma buffer.
|
|
|
|
*/
|
|
|
|
drm_mach64_context_regs_t context_state;
|
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|
|
unsigned int dirty;
|
|
|
|
unsigned int vertsize;
|
|
|
|
|
|
|
|
/* The current cliprects, or a subset thereof.
|
|
|
|
*/
|
|
|
|
drm_clip_rect_t boxes[MACH64_NR_SAREA_CLIPRECTS];
|
|
|
|
unsigned int nbox;
|
|
|
|
|
|
|
|
/* Counters for client-side throttling of rendering clients.
|
|
|
|
*/
|
|
|
|
unsigned int frames_queued;
|
|
|
|
|
|
|
|
/* Texture memory LRU.
|
|
|
|
*/
|
|
|
|
drm_tex_region_t tex_list[MACH64_NR_TEX_HEAPS][MACH64_NR_TEX_REGIONS +
|
|
|
|
1];
|
|
|
|
unsigned int tex_age[MACH64_NR_TEX_HEAPS];
|
|
|
|
int ctx_owner;
|
|
|
|
} drm_mach64_sarea_t;
|
|
|
|
|
|
|
|
/* WARNING: If you change any of these defines, make sure to change the
|
|
|
|
* defines in the Xserver file (mach64_common.h)
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* Mach64 specific ioctls
|
|
|
|
* The device specific ioctl range is 0x40 to 0x79.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#define DRM_MACH64_INIT 0x00
|
|
|
|
#define DRM_MACH64_IDLE 0x01
|
|
|
|
#define DRM_MACH64_RESET 0x02
|
|
|
|
#define DRM_MACH64_SWAP 0x03
|
|
|
|
#define DRM_MACH64_CLEAR 0x04
|
|
|
|
#define DRM_MACH64_VERTEX 0x05
|
|
|
|
#define DRM_MACH64_BLIT 0x06
|
|
|
|
#define DRM_MACH64_FLUSH 0x07
|
|
|
|
#define DRM_MACH64_GETPARAM 0x08
|
|
|
|
|
|
|
|
#define DRM_IOCTL_MACH64_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_INIT, drm_mach64_init_t)
|
|
|
|
#define DRM_IOCTL_MACH64_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_IDLE )
|
|
|
|
#define DRM_IOCTL_MACH64_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_RESET )
|
|
|
|
#define DRM_IOCTL_MACH64_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_SWAP )
|
|
|
|
#define DRM_IOCTL_MACH64_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_CLEAR, drm_mach64_clear_t)
|
|
|
|
#define DRM_IOCTL_MACH64_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_VERTEX, drm_mach64_vertex_t)
|
|
|
|
#define DRM_IOCTL_MACH64_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_BLIT, drm_mach64_blit_t)
|
|
|
|
#define DRM_IOCTL_MACH64_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_FLUSH )
|
|
|
|
#define DRM_IOCTL_MACH64_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_MACH64_GETPARAM, drm_mach64_getparam_t)
|
|
|
|
|
|
|
|
/* Buffer flags for clears
|
|
|
|
*/
|
|
|
|
#define MACH64_FRONT 0x1
|
|
|
|
#define MACH64_BACK 0x2
|
|
|
|
#define MACH64_DEPTH 0x4
|
|
|
|
|
|
|
|
/* Primitive types for vertex buffers
|
|
|
|
*/
|
|
|
|
#define MACH64_PRIM_POINTS 0x00000000
|
|
|
|
#define MACH64_PRIM_LINES 0x00000001
|
|
|
|
#define MACH64_PRIM_LINE_LOOP 0x00000002
|
|
|
|
#define MACH64_PRIM_LINE_STRIP 0x00000003
|
|
|
|
#define MACH64_PRIM_TRIANGLES 0x00000004
|
|
|
|
#define MACH64_PRIM_TRIANGLE_STRIP 0x00000005
|
|
|
|
#define MACH64_PRIM_TRIANGLE_FAN 0x00000006
|
|
|
|
#define MACH64_PRIM_QUADS 0x00000007
|
|
|
|
#define MACH64_PRIM_QUAD_STRIP 0x00000008
|
|
|
|
#define MACH64_PRIM_POLYGON 0x00000009
|
|
|
|
|
|
|
|
typedef enum _drm_mach64_dma_mode_t {
|
|
|
|
MACH64_MODE_DMA_ASYNC,
|
|
|
|
MACH64_MODE_DMA_SYNC,
|
|
|
|
MACH64_MODE_MMIO
|
|
|
|
} drm_mach64_dma_mode_t;
|
|
|
|
|
|
|
|
typedef struct drm_mach64_init {
|
|
|
|
enum {
|
|
|
|
DRM_MACH64_INIT_DMA = 0x01,
|
|
|
|
DRM_MACH64_CLEANUP_DMA = 0x02
|
|
|
|
} func;
|
|
|
|
|
|
|
|
unsigned long sarea_priv_offset;
|
|
|
|
int is_pci;
|
|
|
|
drm_mach64_dma_mode_t dma_mode;
|
|
|
|
|
|
|
|
unsigned int fb_bpp;
|
|
|
|
unsigned int front_offset, front_pitch;
|
|
|
|
unsigned int back_offset, back_pitch;
|
|
|
|
|
|
|
|
unsigned int depth_bpp;
|
|
|
|
unsigned int depth_offset, depth_pitch;
|
|
|
|
|
|
|
|
unsigned long fb_offset;
|
|
|
|
unsigned long mmio_offset;
|
|
|
|
unsigned long ring_offset;
|
|
|
|
unsigned long buffers_offset;
|
|
|
|
unsigned long agp_textures_offset;
|
|
|
|
} drm_mach64_init_t;
|
|
|
|
|
|
|
|
typedef struct drm_mach64_clear {
|
|
|
|
unsigned int flags;
|
|
|
|
int x, y, w, h;
|
|
|
|
unsigned int clear_color;
|
|
|
|
unsigned int clear_depth;
|
|
|
|
} drm_mach64_clear_t;
|
|
|
|
|
|
|
|
typedef struct drm_mach64_vertex {
|
|
|
|
int prim;
|
|
|
|
void *buf; /* Address of vertex buffer */
|
|
|
|
unsigned long used; /* Number of bytes in buffer */
|
|
|
|
int discard; /* Client finished with buffer? */
|
|
|
|
} drm_mach64_vertex_t;
|
|
|
|
|
|
|
|
typedef struct drm_mach64_blit {
|
|
|
|
int idx;
|
|
|
|
int pitch;
|
|
|
|
int offset;
|
|
|
|
int format;
|
|
|
|
unsigned short x, y;
|
|
|
|
unsigned short width, height;
|
|
|
|
} drm_mach64_blit_t;
|
|
|
|
|
|
|
|
typedef struct drm_mach64_getparam {
|
|
|
|
enum {
|
|
|
|
MACH64_PARAM_FRAMES_QUEUED = 0x01,
|
|
|
|
MACH64_PARAM_IRQ_NR = 0x02
|
|
|
|
} param;
|
|
|
|
void *value;
|
|
|
|
} drm_mach64_getparam_t;
|
|
|
|
|
|
|
|
#endif
|