freebsd-nq/sys/mips/conf/BERI_NETFPGA_MDROOT

#
# BERI_NETFPGA_MDROOT -- Kernel for the SRI/Cambridge "BERI" (Bluespec Extensible
# RISC Implementation) FPGA soft core, as configured in its NetFPGA reference
# configuration.
#
# $FreeBSD$
#

include "std.BERI"

ident		BERI_NETFPGA_MDROOT

options 	HZ=100

options 	FDT
options 	FDT_DTB_STATIC
makeoptions	FDT_DTS_FILE=beri-netfpga.dts

#device		uart
device		altera_jtag_uart

device		bpf

options 	DEVICE_POLLING
device		netfpga10g_nf10bmac
options 	NF10BMAC_64BIT

#
# This kernel configuration uses an embedded memory root file system.
# Adjust the following path and size based on local requirements.
#
options 	MD_ROOT			# MD is a potential root device
options 	MD_ROOT_SIZE=26112	# 25.5MB
options 	ROOTDEVNAME=\"ufs:md0\"
#makeoptions	MFS_IMAGE=/foo/baz/baz/mdroot.img

# end
Add an FDT DTS and MDROOT kernel configuration for BERI on NetFPGA. At this point we only support one CPU, the PIC, and a UART console. Reviewed by: brooks Sponsored by: DARPA, AFRL MFC after: 5 days 2013-12-12 18:08:31 +00:00			`#`
			`# BERI_NETFPGA_MDROOT -- Kernel for the SRI/Cambridge "BERI" (Bluespec Extensible`
			`# RISC Implementation) FPGA soft core, as configured in its NetFPGA reference`
			`# configuration.`
			`#`
			`# $FreeBSD$`
			`#`

Rename BERI_TEMPLATE to std.BERI to be more like other configs. Sponsored by: DARPA, AFRL 2017-02-21 17:34:27 +00:00			`include "std.BERI"`
Add an FDT DTS and MDROOT kernel configuration for BERI on NetFPGA. At this point we only support one CPU, the PIC, and a UART console. Reviewed by: brooks Sponsored by: DARPA, AFRL MFC after: 5 days 2013-12-12 18:08:31 +00:00
			`ident BERI_NETFPGA_MDROOT`

For BERI on NetFPGA assume HZ=100 by default. Remove the uart support in favour of a "jtag-uart" interface imitation providing a much simpler interface, directly exported to the host, allowing the toolchain to be shared with BERI on Altera. [1] Submitted by: Jong Hun HAN (jong.han cl.cam.ac.uk) [1] MFC after: 2 weeks 2014-03-22 13:06:32 +00:00			`options HZ=100`

Add an FDT DTS and MDROOT kernel configuration for BERI on NetFPGA. At this point we only support one CPU, the PIC, and a UART console. Reviewed by: brooks Sponsored by: DARPA, AFRL MFC after: 5 days 2013-12-12 18:08:31 +00:00			`options FDT`
			`options FDT_DTB_STATIC`
			`makeoptions FDT_DTS_FILE=beri-netfpga.dts`

For BERI on NetFPGA assume HZ=100 by default. Remove the uart support in favour of a "jtag-uart" interface imitation providing a much simpler interface, directly exported to the host, allowing the toolchain to be shared with BERI on Altera. [1] Submitted by: Jong Hun HAN (jong.han cl.cam.ac.uk) [1] MFC after: 2 weeks 2014-03-22 13:06:32 +00:00			`#device uart`
			`device altera_jtag_uart`
Add an FDT DTS and MDROOT kernel configuration for BERI on NetFPGA. At this point we only support one CPU, the PIC, and a UART console. Reviewed by: brooks Sponsored by: DARPA, AFRL MFC after: 5 days 2013-12-12 18:08:31 +00:00
Add the initial version of if_nf10bmac(4), a driver to support an NetFPGA-10G Embedded CPU Ethernet Core. The current version operates on a simple PIO based interface connected to a NetFPGA-10G port. To avoid confusion: this driver operates on a CPU running on the FPGA, e.g. BERI/mips, and is not suited for the PCI host interface. MFC after: 1 week Relnotes: yes Sponsored by: DARPA/AFRL 2014-04-17 12:33:26 +00:00			`device bpf`

			`options DEVICE_POLLING`
			`device netfpga10g_nf10bmac`
Introduce opt_netfpga.h and allow setting NF10BMAC_64BIT from mips kernel configs. Switch the BERI_NETFPGA_MDROOT to 64bit by default. Give we have working interrupts also cleanup the extra polling CFLAGS from the module Makefile. MFC after: 2 weeks 2014-06-26 17:20:45 +00:00			`options NF10BMAC_64BIT`
Add the initial version of if_nf10bmac(4), a driver to support an NetFPGA-10G Embedded CPU Ethernet Core. The current version operates on a simple PIO based interface connected to a NetFPGA-10G port. To avoid confusion: this driver operates on a CPU running on the FPGA, e.g. BERI/mips, and is not suited for the PCI host interface. MFC after: 1 week Relnotes: yes Sponsored by: DARPA/AFRL 2014-04-17 12:33:26 +00:00
Add an FDT DTS and MDROOT kernel configuration for BERI on NetFPGA. At this point we only support one CPU, the PIC, and a UART console. Reviewed by: brooks Sponsored by: DARPA, AFRL MFC after: 5 days 2013-12-12 18:08:31 +00:00			`#`
			`# This kernel configuration uses an embedded memory root file system.`
			`# Adjust the following path and size based on local requirements.`
			`#`
			`options MD_ROOT # MD is a potential root device`
			`options MD_ROOT_SIZE=26112 # 25.5MB`
			`options ROOTDEVNAME=\"ufs:md0\"`
			`#makeoptions MFS_IMAGE=/foo/baz/baz/mdroot.img`

			`# end`