2012-08-15 05:37:10 +00:00
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/*-
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* Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bio.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/endian.h>
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#include <sys/kernel.h>
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#include <sys/kthread.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/queue.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/time.h>
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#include <sys/timetc.h>
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#include <sys/watchdog.h>
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#include <sys/kdb.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/resource.h>
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#include <machine/intr.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/mmc/bridge.h>
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#include <dev/mmc/mmcreg.h>
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#include <dev/mmc/mmcbrvar.h>
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#include <arm/lpc/lpcreg.h>
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#include <arm/lpc/lpcvar.h>
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#ifdef DEBUG
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#define debugf(fmt, args...) do { printf("%s(): ", __func__); \
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printf(fmt,##args); } while (0)
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#else
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#define debugf(fmt, args...)
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#endif
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struct lpc_mmc_dmamap_arg {
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bus_addr_t lm_dma_busaddr;
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};
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struct lpc_mmc_softc {
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device_t lm_dev;
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struct mtx lm_mtx;
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struct resource * lm_mem_res;
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struct resource * lm_irq_res;
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bus_space_tag_t lm_bst;
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bus_space_handle_t lm_bsh;
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void * lm_intrhand;
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struct mmc_host lm_host;
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struct mmc_request * lm_req;
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struct mmc_data * lm_data;
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uint32_t lm_flags;
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#define LPC_SD_FLAGS_IGNORECRC (1 << 0)
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int lm_xfer_direction;
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#define DIRECTION_READ 0
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#define DIRECTION_WRITE 1
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int lm_xfer_done;
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int lm_bus_busy;
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bus_dma_tag_t lm_dma_tag;
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bus_dmamap_t lm_dma_map;
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bus_addr_t lm_buffer_phys;
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void * lm_buffer;
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};
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#define LPC_SD_MAX_BLOCKSIZE 1024
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/* XXX */
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#define LPC_MMC_DMACH_READ 1
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#define LPC_MMC_DMACH_WRITE 0
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static int lpc_mmc_probe(device_t);
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static int lpc_mmc_attach(device_t);
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static int lpc_mmc_detach(device_t);
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static void lpc_mmc_intr(void *);
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static void lpc_mmc_cmd(struct lpc_mmc_softc *, struct mmc_command *);
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static void lpc_mmc_setup_xfer(struct lpc_mmc_softc *, struct mmc_data *);
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static int lpc_mmc_update_ios(device_t, device_t);
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static int lpc_mmc_request(device_t, device_t, struct mmc_request *);
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static int lpc_mmc_get_ro(device_t, device_t);
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static int lpc_mmc_acquire_host(device_t, device_t);
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static int lpc_mmc_release_host(device_t, device_t);
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static void lpc_mmc_dma_rxfinish(void *);
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static void lpc_mmc_dma_rxerror(void *);
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static void lpc_mmc_dma_txfinish(void *);
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static void lpc_mmc_dma_txerror(void *);
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static void lpc_mmc_dmamap_cb(void *, bus_dma_segment_t *, int, int);
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#define lpc_mmc_lock(_sc) \
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mtx_lock(&_sc->lm_mtx);
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#define lpc_mmc_unlock(_sc) \
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mtx_unlock(&_sc->lm_mtx);
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#define lpc_mmc_read_4(_sc, _reg) \
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bus_space_read_4(_sc->lm_bst, _sc->lm_bsh, _reg)
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#define lpc_mmc_write_4(_sc, _reg, _value) \
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bus_space_write_4(_sc->lm_bst, _sc->lm_bsh, _reg, _value)
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static struct lpc_dmac_channel_config lpc_mmc_dma_rxconf = {
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.ldc_fcntl = LPC_DMAC_FLOW_D_P2M,
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.ldc_src_periph = LPC_DMAC_SD_ID,
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.ldc_src_width = LPC_DMAC_CH_CONTROL_WIDTH_4,
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.ldc_src_incr = 0,
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.ldc_src_burst = LPC_DMAC_CH_CONTROL_BURST_8,
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.ldc_dst_periph = LPC_DMAC_SD_ID,
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.ldc_dst_width = LPC_DMAC_CH_CONTROL_WIDTH_4,
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.ldc_dst_incr = 1,
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.ldc_dst_burst = LPC_DMAC_CH_CONTROL_BURST_8,
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.ldc_success_handler = lpc_mmc_dma_rxfinish,
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.ldc_error_handler = lpc_mmc_dma_rxerror,
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};
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static struct lpc_dmac_channel_config lpc_mmc_dma_txconf = {
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.ldc_fcntl = LPC_DMAC_FLOW_P_M2P,
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.ldc_src_periph = LPC_DMAC_SD_ID,
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.ldc_src_width = LPC_DMAC_CH_CONTROL_WIDTH_4,
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.ldc_src_incr = 1,
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.ldc_src_burst = LPC_DMAC_CH_CONTROL_BURST_8,
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.ldc_dst_periph = LPC_DMAC_SD_ID,
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.ldc_dst_width = LPC_DMAC_CH_CONTROL_WIDTH_4,
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.ldc_dst_incr = 0,
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.ldc_dst_burst = LPC_DMAC_CH_CONTROL_BURST_8,
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.ldc_success_handler = lpc_mmc_dma_txfinish,
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.ldc_error_handler = lpc_mmc_dma_txerror,
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};
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static int
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lpc_mmc_probe(device_t dev)
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{
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if (!ofw_bus_is_compatible(dev, "lpc,mmc"))
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return (ENXIO);
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device_set_desc(dev, "LPC32x0 MMC/SD controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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lpc_mmc_attach(device_t dev)
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{
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struct lpc_mmc_softc *sc = device_get_softc(dev);
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struct lpc_mmc_dmamap_arg ctx;
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device_t child;
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int rid, err;
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sc->lm_dev = dev;
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sc->lm_req = NULL;
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mtx_init(&sc->lm_mtx, "lpcmmc", "mmc", MTX_DEF);
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rid = 0;
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sc->lm_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (!sc->lm_mem_res) {
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device_printf(dev, "cannot allocate memory window\n");
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return (ENXIO);
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}
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sc->lm_bst = rman_get_bustag(sc->lm_mem_res);
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sc->lm_bsh = rman_get_bushandle(sc->lm_mem_res);
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debugf("virtual register space: 0x%08lx\n", sc->lm_bsh);
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rid = 0;
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sc->lm_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_ACTIVE);
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if (!sc->lm_irq_res) {
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device_printf(dev, "cannot allocate interrupt\n");
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lm_mem_res);
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return (ENXIO);
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}
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if (bus_setup_intr(dev, sc->lm_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
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NULL, lpc_mmc_intr, sc, &sc->lm_intrhand))
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{
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lm_mem_res);
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bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lm_irq_res);
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device_printf(dev, "cannot setup interrupt handler\n");
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return (ENXIO);
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}
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sc->lm_host.f_min = 312500;
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sc->lm_host.f_max = 2500000;
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sc->lm_host.host_ocr = MMC_OCR_300_310 | MMC_OCR_310_320 |
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MMC_OCR_320_330 | MMC_OCR_330_340;
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#if 0
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sc->lm_host.caps = MMC_CAP_4_BIT_DATA;
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#endif
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lpc_pwr_write(dev, LPC_CLKPWR_MS_CTRL,
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LPC_CLKPWR_MS_CTRL_CLOCK_EN | LPC_CLKPWR_MS_CTRL_SD_CLOCK | 1);
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lpc_mmc_write_4(sc, LPC_SD_POWER, LPC_SD_POWER_CTRL_ON);
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device_set_ivars(dev, &sc->lm_host);
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child = device_add_child(dev, "mmc", -1);
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if (!child) {
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device_printf(dev, "attaching MMC bus failed!\n");
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bus_teardown_intr(dev, sc->lm_irq_res, sc->lm_intrhand);
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lm_mem_res);
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bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lm_irq_res);
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return (ENXIO);
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}
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/* Alloc DMA memory */
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err = bus_dma_tag_create(
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bus_get_dma_tag(sc->lm_dev),
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4, 0, /* alignment, boundary */
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BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
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BUS_SPACE_MAXADDR, /* highaddr */
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NULL, NULL, /* filter, filterarg */
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LPC_SD_MAX_BLOCKSIZE, 1, /* maxsize, nsegments */
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LPC_SD_MAX_BLOCKSIZE, 0, /* maxsegsize, flags */
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NULL, NULL, /* lockfunc, lockarg */
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&sc->lm_dma_tag);
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err = bus_dmamem_alloc(sc->lm_dma_tag, (void **)&sc->lm_buffer,
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0, &sc->lm_dma_map);
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if (err) {
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device_printf(dev, "cannot allocate framebuffer\n");
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goto fail;
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}
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err = bus_dmamap_load(sc->lm_dma_tag, sc->lm_dma_map, sc->lm_buffer,
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LPC_SD_MAX_BLOCKSIZE, lpc_mmc_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
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if (err) {
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device_printf(dev, "cannot load DMA map\n");
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goto fail;
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}
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sc->lm_buffer_phys = ctx.lm_dma_busaddr;
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lpc_mmc_dma_rxconf.ldc_handler_arg = (void *)sc;
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err = lpc_dmac_config_channel(dev, LPC_MMC_DMACH_READ, &lpc_mmc_dma_rxconf);
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if (err) {
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device_printf(dev, "cannot allocate RX DMA channel\n");
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goto fail;
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}
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lpc_mmc_dma_txconf.ldc_handler_arg = (void *)sc;
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err = lpc_dmac_config_channel(dev, LPC_MMC_DMACH_WRITE, &lpc_mmc_dma_txconf);
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if (err) {
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device_printf(dev, "cannot allocate TX DMA channel\n");
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goto fail;
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}
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bus_generic_probe(dev);
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bus_generic_attach(dev);
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return (0);
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fail:
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if (sc->lm_intrhand)
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bus_teardown_intr(dev, sc->lm_irq_res, sc->lm_intrhand);
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if (sc->lm_irq_res)
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bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lm_irq_res);
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if (sc->lm_mem_res)
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lm_mem_res);
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return (err);
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}
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static int
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lpc_mmc_detach(device_t dev)
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{
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return (EBUSY);
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}
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static void
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lpc_mmc_intr(void *arg)
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{
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struct lpc_mmc_softc *sc = (struct lpc_mmc_softc *)arg;
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struct mmc_command *cmd;
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uint32_t status;
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status = lpc_mmc_read_4(sc, LPC_SD_STATUS);
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debugf("interrupt: 0x%08x\n", status);
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if (status & LPC_SD_STATUS_CMDCRCFAIL) {
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cmd = sc->lm_req->cmd;
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cmd->error = sc->lm_flags & LPC_SD_FLAGS_IGNORECRC
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? MMC_ERR_NONE : MMC_ERR_BADCRC;
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cmd->resp[0] = lpc_mmc_read_4(sc, LPC_SD_RESP0);
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sc->lm_req->done(sc->lm_req);
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sc->lm_req = NULL;
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lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_CMDCRCFAIL);
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}
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if (status & LPC_SD_STATUS_CMDACTIVE)
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{
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debugf("command active\n");
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cmd = sc->lm_req->cmd;
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cmd->resp[0] = lpc_mmc_read_4(sc, LPC_SD_RESP0);
|
|
|
|
sc->lm_req->done(sc->lm_req);
|
|
|
|
sc->lm_req = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (status & LPC_SD_STATUS_DATATIMEOUT) {
|
|
|
|
device_printf(sc->lm_dev, "data timeout\n");
|
|
|
|
lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_DATATIMEOUT);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (status & LPC_SD_STATUS_TXUNDERRUN) {
|
|
|
|
device_printf(sc->lm_dev, "TX underrun\n");
|
|
|
|
lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_TXUNDERRUN);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (status & LPC_SD_STATUS_CMDRESPEND) {
|
|
|
|
debugf("command response\n");
|
|
|
|
cmd = sc->lm_req->cmd;
|
|
|
|
|
|
|
|
if (cmd->flags & MMC_RSP_136) {
|
|
|
|
cmd->resp[3] = lpc_mmc_read_4(sc, LPC_SD_RESP3);
|
|
|
|
cmd->resp[2] = lpc_mmc_read_4(sc, LPC_SD_RESP2);
|
|
|
|
cmd->resp[1] = lpc_mmc_read_4(sc, LPC_SD_RESP1);
|
|
|
|
}
|
|
|
|
|
|
|
|
cmd->resp[0] = lpc_mmc_read_4(sc, LPC_SD_RESP0);
|
|
|
|
cmd->error = MMC_ERR_NONE;
|
|
|
|
|
|
|
|
if (cmd->data && (cmd->data->flags & MMC_DATA_WRITE))
|
|
|
|
lpc_mmc_setup_xfer(sc, sc->lm_req->cmd->data);
|
|
|
|
|
|
|
|
if (!cmd->data) {
|
|
|
|
sc->lm_req->done(sc->lm_req);
|
|
|
|
sc->lm_req = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_CMDRESPEND);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (status & LPC_SD_STATUS_CMDSENT) {
|
|
|
|
debugf("command sent\n");
|
|
|
|
cmd = sc->lm_req->cmd;
|
|
|
|
cmd->error = MMC_ERR_NONE;
|
|
|
|
sc->lm_req->done(sc->lm_req);
|
|
|
|
sc->lm_req = NULL;
|
|
|
|
lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_CMDSENT);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (status & LPC_SD_STATUS_DATAEND) {
|
|
|
|
if (sc->lm_xfer_direction == DIRECTION_READ)
|
|
|
|
lpc_dmac_start_burst(sc->lm_dev, LPC_DMAC_SD_ID);
|
|
|
|
|
|
|
|
lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_DATAEND);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (status & LPC_SD_STATUS_CMDTIMEOUT) {
|
|
|
|
device_printf(sc->lm_dev, "command response timeout\n");
|
|
|
|
cmd = sc->lm_req->cmd;
|
|
|
|
cmd->error = MMC_ERR_TIMEOUT;
|
|
|
|
sc->lm_req->done(sc->lm_req);
|
|
|
|
sc->lm_req = NULL;
|
|
|
|
lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_CMDTIMEOUT);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (status & LPC_SD_STATUS_STARTBITERR) {
|
|
|
|
device_printf(sc->lm_dev, "start bit error\n");
|
|
|
|
lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_STARTBITERR);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (status & LPC_SD_STATUS_DATACRCFAIL) {
|
|
|
|
device_printf(sc->lm_dev, "data CRC error\n");
|
|
|
|
debugf("data buffer: %p\n", sc->lm_buffer);
|
|
|
|
cmd = sc->lm_req->cmd;
|
|
|
|
cmd->error = MMC_ERR_BADCRC;
|
|
|
|
sc->lm_req->done(sc->lm_req);
|
|
|
|
sc->lm_req = NULL;
|
|
|
|
|
|
|
|
if (sc->lm_xfer_direction == DIRECTION_READ)
|
|
|
|
lpc_dmac_start_burst(sc->lm_dev, LPC_DMAC_SD_ID);
|
|
|
|
|
|
|
|
lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_DATACRCFAIL);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (status & LPC_SD_STATUS_DATABLOCKEND) {
|
|
|
|
debugf("data block end\n");
|
|
|
|
if (sc->lm_xfer_direction == DIRECTION_READ)
|
|
|
|
memcpy(sc->lm_data->data, sc->lm_buffer, sc->lm_data->len);
|
|
|
|
|
|
|
|
if (sc->lm_xfer_direction == DIRECTION_WRITE) {
|
|
|
|
lpc_dmac_disable_channel(sc->lm_dev, LPC_MMC_DMACH_WRITE);
|
|
|
|
lpc_mmc_write_4(sc, LPC_SD_DATACTRL, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
sc->lm_req->done(sc->lm_req);
|
|
|
|
sc->lm_req = NULL;
|
|
|
|
lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_DATABLOCKEND);
|
|
|
|
}
|
|
|
|
|
|
|
|
debugf("done\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
lpc_mmc_request(device_t bus, device_t child, struct mmc_request *req)
|
|
|
|
{
|
|
|
|
struct lpc_mmc_softc *sc = device_get_softc(bus);
|
|
|
|
|
|
|
|
debugf("request: %p\n", req);
|
|
|
|
|
|
|
|
lpc_mmc_lock(sc);
|
|
|
|
if (sc->lm_req)
|
|
|
|
return (EBUSY);
|
|
|
|
|
|
|
|
sc->lm_req = req;
|
|
|
|
|
|
|
|
if (req->cmd->data && req->cmd->data->flags & MMC_DATA_WRITE) {
|
|
|
|
memcpy(sc->lm_buffer, req->cmd->data->data, req->cmd->data->len);
|
|
|
|
lpc_mmc_cmd(sc, req->cmd);
|
|
|
|
lpc_mmc_unlock(sc);
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (req->cmd->data)
|
|
|
|
lpc_mmc_setup_xfer(sc, req->cmd->data);
|
|
|
|
|
|
|
|
lpc_mmc_cmd(sc, req->cmd);
|
|
|
|
lpc_mmc_unlock(sc);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
lpc_mmc_cmd(struct lpc_mmc_softc *sc, struct mmc_command *cmd)
|
|
|
|
{
|
|
|
|
uint32_t cmdreg = 0;
|
|
|
|
|
|
|
|
debugf("cmd: %d arg: 0x%08x\n", cmd->opcode, cmd->arg);
|
|
|
|
|
|
|
|
if (lpc_mmc_read_4(sc, LPC_SD_COMMAND) & LPC_SD_COMMAND_ENABLE) {
|
|
|
|
lpc_mmc_write_4(sc, LPC_SD_COMMAND, 0);
|
|
|
|
DELAY(1000);
|
|
|
|
}
|
|
|
|
|
|
|
|
sc->lm_flags &= ~LPC_SD_FLAGS_IGNORECRC;
|
|
|
|
|
|
|
|
if (cmd->flags & MMC_RSP_PRESENT)
|
|
|
|
cmdreg |= LPC_SD_COMMAND_RESPONSE;
|
|
|
|
|
|
|
|
if (MMC_RSP(cmd->flags) == MMC_RSP_R2)
|
|
|
|
cmdreg |= LPC_SD_COMMAND_LONGRSP;
|
|
|
|
|
|
|
|
if (MMC_RSP(cmd->flags) == MMC_RSP_R3)
|
|
|
|
sc->lm_flags |= LPC_SD_FLAGS_IGNORECRC;
|
|
|
|
|
|
|
|
cmdreg |= LPC_SD_COMMAND_ENABLE;
|
|
|
|
cmdreg |= (cmd->opcode & LPC_SD_COMMAND_CMDINDEXMASK);
|
|
|
|
|
|
|
|
lpc_mmc_write_4(sc, LPC_SD_MASK0, 0xffffffff);
|
|
|
|
lpc_mmc_write_4(sc, LPC_SD_MASK1, 0xffffffff);
|
|
|
|
lpc_mmc_write_4(sc, LPC_SD_ARGUMENT, cmd->arg);
|
|
|
|
lpc_mmc_write_4(sc, LPC_SD_COMMAND, cmdreg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
lpc_mmc_setup_xfer(struct lpc_mmc_softc *sc, struct mmc_data *data)
|
|
|
|
{
|
|
|
|
uint32_t datactrl = 0;
|
|
|
|
int data_words = data->len / 4;
|
|
|
|
|
|
|
|
sc->lm_data = data;
|
|
|
|
sc->lm_xfer_done = 0;
|
|
|
|
|
|
|
|
debugf("data: %p, len: %d, %s\n", data,
|
|
|
|
data->len, (data->flags & MMC_DATA_READ) ? "read" : "write");
|
|
|
|
|
|
|
|
if (data->flags & MMC_DATA_READ) {
|
|
|
|
sc->lm_xfer_direction = DIRECTION_READ;
|
|
|
|
lpc_dmac_setup_transfer(sc->lm_dev, LPC_MMC_DMACH_READ,
|
2014-01-05 18:40:06 +00:00
|
|
|
LPC_SD_PHYS_BASE + LPC_SD_FIFO, sc->lm_buffer_phys,
|
2012-08-15 05:37:10 +00:00
|
|
|
data_words, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (data->flags & MMC_DATA_WRITE) {
|
|
|
|
sc->lm_xfer_direction = DIRECTION_WRITE;
|
|
|
|
lpc_dmac_setup_transfer(sc->lm_dev, LPC_MMC_DMACH_WRITE,
|
2014-01-05 18:40:06 +00:00
|
|
|
sc->lm_buffer_phys, LPC_SD_PHYS_BASE + LPC_SD_FIFO,
|
2012-08-15 05:37:10 +00:00
|
|
|
data_words, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
datactrl |= (sc->lm_xfer_direction
|
|
|
|
? LPC_SD_DATACTRL_WRITE
|
|
|
|
: LPC_SD_DATACTRL_READ);
|
|
|
|
|
|
|
|
datactrl |= LPC_SD_DATACTRL_DMAENABLE | LPC_SD_DATACTRL_ENABLE;
|
|
|
|
datactrl |= (ffs(data->len) - 1) << 4;
|
|
|
|
|
|
|
|
debugf("datactrl: 0x%08x\n", datactrl);
|
|
|
|
|
|
|
|
lpc_mmc_write_4(sc, LPC_SD_DATATIMER, 0xFFFF0000);
|
|
|
|
lpc_mmc_write_4(sc, LPC_SD_DATALENGTH, data->len);
|
|
|
|
lpc_mmc_write_4(sc, LPC_SD_DATACTRL, datactrl);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
lpc_mmc_read_ivar(device_t bus, device_t child, int which,
|
|
|
|
uintptr_t *result)
|
|
|
|
{
|
|
|
|
struct lpc_mmc_softc *sc = device_get_softc(bus);
|
|
|
|
|
|
|
|
switch (which) {
|
|
|
|
default:
|
|
|
|
return (EINVAL);
|
|
|
|
case MMCBR_IVAR_BUS_MODE:
|
|
|
|
*(int *)result = sc->lm_host.ios.bus_mode;
|
|
|
|
break;
|
|
|
|
case MMCBR_IVAR_BUS_WIDTH:
|
|
|
|
*(int *)result = sc->lm_host.ios.bus_width;
|
|
|
|
break;
|
|
|
|
case MMCBR_IVAR_CHIP_SELECT:
|
|
|
|
*(int *)result = sc->lm_host.ios.chip_select;
|
|
|
|
break;
|
|
|
|
case MMCBR_IVAR_CLOCK:
|
|
|
|
*(int *)result = sc->lm_host.ios.clock;
|
|
|
|
break;
|
|
|
|
case MMCBR_IVAR_F_MIN:
|
|
|
|
*(int *)result = sc->lm_host.f_min;
|
|
|
|
break;
|
|
|
|
case MMCBR_IVAR_F_MAX:
|
|
|
|
*(int *)result = sc->lm_host.f_max;
|
|
|
|
break;
|
|
|
|
case MMCBR_IVAR_HOST_OCR:
|
|
|
|
*(int *)result = sc->lm_host.host_ocr;
|
|
|
|
break;
|
|
|
|
case MMCBR_IVAR_MODE:
|
|
|
|
*(int *)result = sc->lm_host.mode;
|
|
|
|
break;
|
|
|
|
case MMCBR_IVAR_OCR:
|
|
|
|
*(int *)result = sc->lm_host.ocr;
|
|
|
|
break;
|
|
|
|
case MMCBR_IVAR_POWER_MODE:
|
|
|
|
*(int *)result = sc->lm_host.ios.power_mode;
|
|
|
|
break;
|
|
|
|
case MMCBR_IVAR_VDD:
|
|
|
|
*(int *)result = sc->lm_host.ios.vdd;
|
|
|
|
break;
|
|
|
|
case MMCBR_IVAR_CAPS:
|
|
|
|
*(int *)result = sc->lm_host.caps;
|
|
|
|
break;
|
|
|
|
case MMCBR_IVAR_MAX_DATA:
|
|
|
|
*(int *)result = 1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
lpc_mmc_write_ivar(device_t bus, device_t child, int which,
|
|
|
|
uintptr_t value)
|
|
|
|
{
|
|
|
|
struct lpc_mmc_softc *sc = device_get_softc(bus);
|
|
|
|
|
|
|
|
switch (which) {
|
|
|
|
default:
|
|
|
|
return (EINVAL);
|
|
|
|
case MMCBR_IVAR_BUS_MODE:
|
|
|
|
sc->lm_host.ios.bus_mode = value;
|
|
|
|
break;
|
|
|
|
case MMCBR_IVAR_BUS_WIDTH:
|
|
|
|
sc->lm_host.ios.bus_width = value;
|
|
|
|
break;
|
|
|
|
case MMCBR_IVAR_CHIP_SELECT:
|
|
|
|
sc->lm_host.ios.chip_select = value;
|
|
|
|
break;
|
|
|
|
case MMCBR_IVAR_CLOCK:
|
|
|
|
sc->lm_host.ios.clock = value;
|
|
|
|
break;
|
|
|
|
case MMCBR_IVAR_MODE:
|
|
|
|
sc->lm_host.mode = value;
|
|
|
|
break;
|
|
|
|
case MMCBR_IVAR_OCR:
|
|
|
|
sc->lm_host.ocr = value;
|
|
|
|
break;
|
|
|
|
case MMCBR_IVAR_POWER_MODE:
|
|
|
|
sc->lm_host.ios.power_mode = value;
|
|
|
|
break;
|
|
|
|
case MMCBR_IVAR_VDD:
|
|
|
|
sc->lm_host.ios.vdd = value;
|
|
|
|
break;
|
|
|
|
/* These are read-only */
|
|
|
|
case MMCBR_IVAR_CAPS:
|
|
|
|
case MMCBR_IVAR_HOST_OCR:
|
|
|
|
case MMCBR_IVAR_F_MIN:
|
|
|
|
case MMCBR_IVAR_F_MAX:
|
|
|
|
case MMCBR_IVAR_MAX_DATA:
|
|
|
|
return (EINVAL);
|
|
|
|
}
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
lpc_mmc_update_ios(device_t bus, device_t child)
|
|
|
|
{
|
|
|
|
struct lpc_mmc_softc *sc = device_get_softc(bus);
|
|
|
|
struct mmc_ios *ios = &sc->lm_host.ios;
|
|
|
|
uint32_t clkdiv = 0, pwr = 0;
|
|
|
|
|
|
|
|
if (ios->bus_width == bus_width_4)
|
|
|
|
clkdiv |= LPC_SD_CLOCK_WIDEBUS;
|
|
|
|
|
|
|
|
/* Calculate clock divider */
|
|
|
|
clkdiv = (LPC_SD_CLK / (2 * ios->clock)) - 1;
|
|
|
|
|
|
|
|
/* Clock rate should not exceed rate requested in ios */
|
|
|
|
if ((LPC_SD_CLK / (2 * (clkdiv + 1))) > ios->clock)
|
|
|
|
clkdiv++;
|
|
|
|
|
|
|
|
debugf("clock: %dHz, clkdiv: %d\n", ios->clock, clkdiv);
|
|
|
|
|
|
|
|
if (ios->bus_width == bus_width_4) {
|
|
|
|
debugf("using wide bus mode\n");
|
|
|
|
clkdiv |= LPC_SD_CLOCK_WIDEBUS;
|
|
|
|
}
|
|
|
|
|
|
|
|
lpc_mmc_write_4(sc, LPC_SD_CLOCK, clkdiv | LPC_SD_CLOCK_ENABLE);
|
|
|
|
|
|
|
|
switch (ios->power_mode) {
|
|
|
|
case power_off:
|
|
|
|
pwr |= LPC_SD_POWER_CTRL_OFF;
|
|
|
|
break;
|
|
|
|
case power_up:
|
|
|
|
pwr |= LPC_SD_POWER_CTRL_UP;
|
|
|
|
break;
|
|
|
|
case power_on:
|
|
|
|
pwr |= LPC_SD_POWER_CTRL_ON;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ios->bus_mode == opendrain)
|
|
|
|
pwr |= LPC_SD_POWER_OPENDRAIN;
|
|
|
|
|
|
|
|
lpc_mmc_write_4(sc, LPC_SD_POWER, pwr);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
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static int
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lpc_mmc_get_ro(device_t bus, device_t child)
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{
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return (0);
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}
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static int
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lpc_mmc_acquire_host(device_t bus, device_t child)
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{
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struct lpc_mmc_softc *sc = device_get_softc(bus);
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int error = 0;
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lpc_mmc_lock(sc);
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while (sc->lm_bus_busy)
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error = mtx_sleep(sc, &sc->lm_mtx, PZERO, "mmcah", 0);
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sc->lm_bus_busy++;
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lpc_mmc_unlock(sc);
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return (error);
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}
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static int
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lpc_mmc_release_host(device_t bus, device_t child)
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{
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struct lpc_mmc_softc *sc = device_get_softc(bus);
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lpc_mmc_lock(sc);
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sc->lm_bus_busy--;
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wakeup(sc);
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lpc_mmc_unlock(sc);
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return (0);
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}
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static void lpc_mmc_dma_rxfinish(void *arg)
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{
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}
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static void lpc_mmc_dma_rxerror(void *arg)
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{
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struct lpc_mmc_softc *sc = (struct lpc_mmc_softc *)arg;
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device_printf(sc->lm_dev, "DMA RX error\n");
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}
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static void lpc_mmc_dma_txfinish(void *arg)
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{
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}
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static void lpc_mmc_dma_txerror(void *arg)
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{
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struct lpc_mmc_softc *sc = (struct lpc_mmc_softc *)arg;
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device_printf(sc->lm_dev, "DMA TX error\n");
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}
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static void
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lpc_mmc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
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{
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struct lpc_mmc_dmamap_arg *ctx;
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if (err)
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return;
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ctx = (struct lpc_mmc_dmamap_arg *)arg;
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ctx->lm_dma_busaddr = segs[0].ds_addr;
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}
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static device_method_t lpc_mmc_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, lpc_mmc_probe),
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DEVMETHOD(device_attach, lpc_mmc_attach),
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DEVMETHOD(device_detach, lpc_mmc_detach),
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/* Bus interface */
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DEVMETHOD(bus_read_ivar, lpc_mmc_read_ivar),
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DEVMETHOD(bus_write_ivar, lpc_mmc_write_ivar),
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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/* MMC bridge interface */
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DEVMETHOD(mmcbr_update_ios, lpc_mmc_update_ios),
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DEVMETHOD(mmcbr_request, lpc_mmc_request),
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DEVMETHOD(mmcbr_get_ro, lpc_mmc_get_ro),
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DEVMETHOD(mmcbr_acquire_host, lpc_mmc_acquire_host),
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DEVMETHOD(mmcbr_release_host, lpc_mmc_release_host),
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{ 0, 0 }
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};
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static devclass_t lpc_mmc_devclass;
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static driver_t lpc_mmc_driver = {
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"lpcmmc",
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lpc_mmc_methods,
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sizeof(struct lpc_mmc_softc),
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};
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DRIVER_MODULE(lpcmmc, simplebus, lpc_mmc_driver, lpc_mmc_devclass, 0, 0);
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