2016-02-16 11:45:46 +00:00
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/*-
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* Copyright (c) 2014-2016 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Allwinner A10/A20 Audio Codec
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/condvar.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/gpio.h>
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#include <machine/bus.h>
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#include <dev/sound/pcm/sound.h>
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#include <dev/sound/chip.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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2016-04-06 23:11:03 +00:00
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#include <dev/extres/clk/clk.h>
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2016-02-16 11:45:46 +00:00
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#include "sunxi_dma_if.h"
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#include "mixer_if.h"
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#include "gpio_if.h"
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#define TX_TRIG_LEVEL 0xf
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#define RX_TRIG_LEVEL 0x7
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#define DRQ_CLR_CNT 0x3
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#define AC_DAC_DPC 0x00
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#define DAC_DPC_EN_DA 0x80000000
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#define AC_DAC_FIFOC 0x04
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#define DAC_FIFOC_FS_SHIFT 29
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#define DAC_FIFOC_FS_MASK (7U << DAC_FIFOC_FS_SHIFT)
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#define DAC_FS_48KHZ 0
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#define DAC_FS_32KHZ 1
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#define DAC_FS_24KHZ 2
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#define DAC_FS_16KHZ 3
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#define DAC_FS_12KHZ 4
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#define DAC_FS_8KHZ 5
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#define DAC_FS_192KHZ 6
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#define DAC_FS_96KHZ 7
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#define DAC_FIFOC_FIFO_MODE_SHIFT 24
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#define DAC_FIFOC_FIFO_MODE_MASK (3U << DAC_FIFOC_FIFO_MODE_SHIFT)
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#define FIFO_MODE_24_31_8 0
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#define FIFO_MODE_16_31_16 0
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#define FIFO_MODE_16_15_0 1
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#define DAC_FIFOC_DRQ_CLR_CNT_SHIFT 21
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#define DAC_FIFOC_DRQ_CLR_CNT_MASK (3U << DAC_FIFOC_DRQ_CLR_CNT_SHIFT)
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#define DAC_FIFOC_TX_TRIG_LEVEL_SHIFT 8
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#define DAC_FIFOC_TX_TRIG_LEVEL_MASK (0x7f << DAC_FIFOC_TX_TRIG_LEVEL_SHIFT)
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#define DAC_FIFOC_MONO_EN (1U << 6)
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#define DAC_FIFOC_TX_BITS (1U << 5)
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#define DAC_FIFOC_DRQ_EN (1U << 4)
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#define DAC_FIFOC_FIFO_FLUSH (1U << 0)
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#define AC_DAC_FIFOS 0x08
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#define AC_DAC_TXDATA 0x0c
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#define AC_DAC_ACTL 0x10
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#define DAC_ACTL_DACAREN (1U << 31)
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#define DAC_ACTL_DACALEN (1U << 30)
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#define DAC_ACTL_MIXEN (1U << 29)
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#define DAC_ACTL_DACPAS (1U << 8)
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#define DAC_ACTL_PAMUTE (1U << 6)
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#define DAC_ACTL_PAVOL_SHIFT 0
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#define DAC_ACTL_PAVOL_MASK (0x3f << DAC_ACTL_PAVOL_SHIFT)
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#define AC_ADC_FIFOC 0x1c
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#define ADC_FIFOC_FS_SHIFT 29
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#define ADC_FIFOC_FS_MASK (7U << ADC_FIFOC_FS_SHIFT)
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#define ADC_FS_48KHZ 0
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#define ADC_FIFOC_EN_AD (1U << 28)
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#define ADC_FIFOC_RX_FIFO_MODE (1U << 24)
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#define ADC_FIFOC_RX_TRIG_LEVEL_SHIFT 8
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#define ADC_FIFOC_RX_TRIG_LEVEL_MASK (0x1f << ADC_FIFOC_RX_TRIG_LEVEL_SHIFT)
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#define ADC_FIFOC_MONO_EN (1U << 7)
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#define ADC_FIFOC_RX_BITS (1U << 6)
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#define ADC_FIFOC_DRQ_EN (1U << 4)
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#define ADC_FIFOC_FIFO_FLUSH (1U << 1)
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#define AC_ADC_FIFOS 0x20
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#define AC_ADC_RXDATA 0x24
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#define AC_ADC_ACTL 0x28
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#define ADC_ACTL_ADCREN (1U << 31)
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#define ADC_ACTL_ADCLEN (1U << 30)
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#define ADC_ACTL_PREG1EN (1U << 29)
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#define ADC_ACTL_PREG2EN (1U << 28)
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#define ADC_ACTL_VMICEN (1U << 27)
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#define ADC_ACTL_ADCG_SHIFT 20
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#define ADC_ACTL_ADCG_MASK (7U << ADC_ACTL_ADCG_SHIFT)
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#define ADC_ACTL_ADCIS_SHIFT 17
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#define ADC_ACTL_ADCIS_MASK (7U << ADC_ACTL_ADCIS_SHIFT)
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#define ADC_IS_LINEIN 0
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#define ADC_IS_FMIN 1
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#define ADC_IS_MIC1 2
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#define ADC_IS_MIC2 3
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#define ADC_IS_MIC1_L_MIC2_R 4
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#define ADC_IS_MIC1_LR_MIC2_LR 5
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#define ADC_IS_OMIX 6
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#define ADC_IS_LINEIN_L_MIC1_R 7
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#define ADC_ACTL_LNRDF (1U << 16)
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#define ADC_ACTL_LNPREG_SHIFT 13
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#define ADC_ACTL_LNPREG_MASK (7U << ADC_ACTL_LNPREG_SHIFT)
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#define ADC_ACTL_PA_EN (1U << 4)
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#define ADC_ACTL_DDE (1U << 3)
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#define AC_DAC_CNT 0x30
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#define AC_ADC_CNT 0x34
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static uint32_t a10codec_fmt[] = {
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SND_FORMAT(AFMT_S16_LE, 1, 0),
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SND_FORMAT(AFMT_S16_LE, 2, 0),
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0
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};
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static struct pcmchan_caps a10codec_pcaps = { 8000, 192000, a10codec_fmt, 0 };
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static struct pcmchan_caps a10codec_rcaps = { 8000, 48000, a10codec_fmt, 0 };
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struct a10codec_info;
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struct a10codec_chinfo {
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struct snd_dbuf *buffer;
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struct pcm_channel *channel;
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struct a10codec_info *parent;
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bus_dmamap_t dmamap;
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void *dmaaddr;
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bus_addr_t physaddr;
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bus_size_t fifo;
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device_t dmac;
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void *dmachan;
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int dir;
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int run;
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uint32_t pos;
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uint32_t format;
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uint32_t blocksize;
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uint32_t speed;
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};
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struct a10codec_info {
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device_t dev;
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struct resource *res[2];
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struct mtx *lock;
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bus_dma_tag_t dmat;
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unsigned dmasize;
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void *ih;
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unsigned drqtype_codec;
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unsigned drqtype_sdram;
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struct a10codec_chinfo play;
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struct a10codec_chinfo rec;
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};
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static struct resource_spec a10codec_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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#define CODEC_READ(sc, reg) bus_read_4((sc)->res[0], (reg))
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#define CODEC_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))
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/*
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* Mixer interface
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*/
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static int
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a10codec_mixer_init(struct snd_mixer *m)
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{
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struct a10codec_info *sc = mix_getdevinfo(m);
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pcell_t prop[4];
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phandle_t node;
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device_t gpio;
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uint32_t val;
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ssize_t len;
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int pin;
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mix_setdevs(m, SOUND_MASK_VOLUME | SOUND_MASK_LINE | SOUND_MASK_RECLEV);
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mix_setrecdevs(m, SOUND_MASK_LINE | SOUND_MASK_LINE1 | SOUND_MASK_MIC);
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/* Unmute input source to PA */
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val = CODEC_READ(sc, AC_DAC_ACTL);
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val |= DAC_ACTL_PAMUTE;
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CODEC_WRITE(sc, AC_DAC_ACTL, val);
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/* Enable PA */
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val = CODEC_READ(sc, AC_ADC_ACTL);
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val |= ADC_ACTL_PA_EN;
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CODEC_WRITE(sc, AC_ADC_ACTL, val);
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/* Unmute PA */
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node = ofw_bus_get_node(sc->dev);
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len = OF_getencprop(node, "allwinner,pa-gpios", prop, sizeof(prop));
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if (len > 0 && (len / sizeof(prop[0])) == 4) {
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gpio = OF_device_from_xref(prop[0]);
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if (gpio != NULL) {
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pin = prop[1] * 32 + prop[2];
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GPIO_PIN_SETFLAGS(gpio, pin, GPIO_PIN_OUTPUT);
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GPIO_PIN_SET(gpio, pin, GPIO_PIN_LOW);
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}
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}
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return (0);
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}
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static const struct a10codec_mixer {
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unsigned reg;
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unsigned mask;
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unsigned shift;
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} a10codec_mixers[SOUND_MIXER_NRDEVICES] = {
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[SOUND_MIXER_VOLUME] = { AC_DAC_ACTL, DAC_ACTL_PAVOL_MASK,
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DAC_ACTL_PAVOL_SHIFT },
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[SOUND_MIXER_LINE] = { AC_ADC_ACTL, ADC_ACTL_LNPREG_MASK,
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ADC_ACTL_LNPREG_SHIFT },
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[SOUND_MIXER_RECLEV] = { AC_ADC_ACTL, ADC_ACTL_ADCG_MASK,
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ADC_ACTL_ADCG_SHIFT },
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};
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static int
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a10codec_mixer_set(struct snd_mixer *m, unsigned dev, unsigned left,
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unsigned right)
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{
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struct a10codec_info *sc = mix_getdevinfo(m);
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uint32_t val;
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unsigned nvol, max;
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max = a10codec_mixers[dev].mask >> a10codec_mixers[dev].shift;
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nvol = (left * max) / 100;
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val = CODEC_READ(sc, a10codec_mixers[dev].reg);
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val &= ~a10codec_mixers[dev].mask;
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val |= (nvol << a10codec_mixers[dev].shift);
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CODEC_WRITE(sc, a10codec_mixers[dev].reg, val);
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left = right = (left * 100) / max;
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return (left | (right << 8));
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}
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static uint32_t
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a10codec_mixer_setrecsrc(struct snd_mixer *m, uint32_t src)
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{
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struct a10codec_info *sc = mix_getdevinfo(m);
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uint32_t val;
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val = CODEC_READ(sc, AC_ADC_ACTL);
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switch (src) {
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case SOUND_MASK_LINE: /* line-in */
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val &= ~ADC_ACTL_ADCIS_MASK;
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val |= (ADC_IS_LINEIN << ADC_ACTL_ADCIS_SHIFT);
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break;
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case SOUND_MASK_MIC: /* MIC1 */
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val &= ~ADC_ACTL_ADCIS_MASK;
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val |= (ADC_IS_MIC1 << ADC_ACTL_ADCIS_SHIFT);
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break;
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case SOUND_MASK_LINE1: /* MIC2 */
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val &= ~ADC_ACTL_ADCIS_MASK;
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val |= (ADC_IS_MIC2 << ADC_ACTL_ADCIS_SHIFT);
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break;
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default:
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break;
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}
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CODEC_WRITE(sc, AC_ADC_ACTL, val);
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switch ((val & ADC_ACTL_ADCIS_MASK) >> ADC_ACTL_ADCIS_SHIFT) {
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case ADC_IS_LINEIN:
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return (SOUND_MASK_LINE);
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case ADC_IS_MIC1:
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return (SOUND_MASK_MIC);
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case ADC_IS_MIC2:
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return (SOUND_MASK_LINE1);
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default:
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return (0);
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}
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}
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static kobj_method_t a10codec_mixer_methods[] = {
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KOBJMETHOD(mixer_init, a10codec_mixer_init),
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KOBJMETHOD(mixer_set, a10codec_mixer_set),
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KOBJMETHOD(mixer_setrecsrc, a10codec_mixer_setrecsrc),
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KOBJMETHOD_END
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};
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MIXER_DECLARE(a10codec_mixer);
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/*
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* Channel interface
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*/
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static void
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a10codec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
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{
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struct a10codec_chinfo *ch = arg;
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if (error != 0)
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return;
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ch->physaddr = segs[0].ds_addr;
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}
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static void
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a10codec_transfer(struct a10codec_chinfo *ch)
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{
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bus_addr_t src, dst;
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int error;
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if (ch->dir == PCMDIR_PLAY) {
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src = ch->physaddr + ch->pos;
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dst = ch->fifo;
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} else {
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src = ch->fifo;
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dst = ch->physaddr + ch->pos;
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}
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|
|
|
|
|
|
error = SUNXI_DMA_TRANSFER(ch->dmac, ch->dmachan, src, dst,
|
|
|
|
ch->blocksize);
|
|
|
|
if (error) {
|
|
|
|
ch->run = 0;
|
|
|
|
device_printf(ch->parent->dev, "DMA transfer failed: %d\n",
|
|
|
|
error);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
a10codec_dmaconfig(struct a10codec_chinfo *ch)
|
|
|
|
{
|
|
|
|
struct a10codec_info *sc = ch->parent;
|
|
|
|
struct sunxi_dma_config conf;
|
|
|
|
|
|
|
|
memset(&conf, 0, sizeof(conf));
|
|
|
|
conf.src_width = conf.dst_width = 16;
|
|
|
|
conf.src_burst_len = conf.dst_burst_len = 4;
|
|
|
|
|
|
|
|
if (ch->dir == PCMDIR_PLAY) {
|
|
|
|
conf.dst_noincr = true;
|
|
|
|
conf.src_drqtype = sc->drqtype_sdram;
|
|
|
|
conf.dst_drqtype = sc->drqtype_codec;
|
|
|
|
} else {
|
|
|
|
conf.src_noincr = true;
|
|
|
|
conf.src_drqtype = sc->drqtype_codec;
|
|
|
|
conf.dst_drqtype = sc->drqtype_sdram;
|
|
|
|
}
|
|
|
|
|
|
|
|
SUNXI_DMA_SET_CONFIG(ch->dmac, ch->dmachan, &conf);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
a10codec_dmaintr(void *priv)
|
|
|
|
{
|
|
|
|
struct a10codec_chinfo *ch = priv;
|
|
|
|
unsigned bufsize;
|
|
|
|
|
|
|
|
bufsize = sndbuf_getsize(ch->buffer);
|
|
|
|
|
|
|
|
ch->pos += ch->blocksize;
|
|
|
|
if (ch->pos >= bufsize)
|
|
|
|
ch->pos -= bufsize;
|
|
|
|
|
|
|
|
if (ch->run) {
|
|
|
|
chn_intr(ch->channel);
|
|
|
|
a10codec_transfer(ch);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned
|
|
|
|
a10codec_fs(struct a10codec_chinfo *ch)
|
|
|
|
{
|
|
|
|
switch (ch->speed) {
|
|
|
|
case 48000:
|
|
|
|
return (DAC_FS_48KHZ);
|
|
|
|
case 24000:
|
|
|
|
return (DAC_FS_24KHZ);
|
|
|
|
case 12000:
|
|
|
|
return (DAC_FS_12KHZ);
|
|
|
|
case 192000:
|
|
|
|
return (DAC_FS_192KHZ);
|
|
|
|
case 32000:
|
|
|
|
return (DAC_FS_32KHZ);
|
|
|
|
case 16000:
|
|
|
|
return (DAC_FS_16KHZ);
|
|
|
|
case 8000:
|
|
|
|
return (DAC_FS_8KHZ);
|
|
|
|
case 96000:
|
|
|
|
return (DAC_FS_96KHZ);
|
|
|
|
default:
|
|
|
|
return (DAC_FS_48KHZ);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
a10codec_start(struct a10codec_chinfo *ch)
|
|
|
|
{
|
|
|
|
struct a10codec_info *sc = ch->parent;
|
|
|
|
uint32_t val;
|
|
|
|
|
|
|
|
ch->pos = 0;
|
|
|
|
|
|
|
|
if (ch->dir == PCMDIR_PLAY) {
|
|
|
|
/* Flush DAC FIFO */
|
|
|
|
CODEC_WRITE(sc, AC_DAC_FIFOC, DAC_FIFOC_FIFO_FLUSH);
|
|
|
|
|
|
|
|
/* Clear DAC FIFO status */
|
|
|
|
CODEC_WRITE(sc, AC_DAC_FIFOS, CODEC_READ(sc, AC_DAC_FIFOS));
|
|
|
|
|
|
|
|
/* Enable DAC analog left/right channels and output mixer */
|
|
|
|
val = CODEC_READ(sc, AC_DAC_ACTL);
|
|
|
|
val |= DAC_ACTL_DACAREN;
|
|
|
|
val |= DAC_ACTL_DACALEN;
|
|
|
|
val |= DAC_ACTL_DACPAS;
|
|
|
|
CODEC_WRITE(sc, AC_DAC_ACTL, val);
|
|
|
|
|
|
|
|
/* Configure DAC DMA channel */
|
|
|
|
a10codec_dmaconfig(ch);
|
|
|
|
|
|
|
|
/* Configure DAC FIFO */
|
|
|
|
CODEC_WRITE(sc, AC_DAC_FIFOC,
|
|
|
|
(AFMT_CHANNEL(ch->format) == 1 ? DAC_FIFOC_MONO_EN : 0) |
|
|
|
|
(a10codec_fs(ch) << DAC_FIFOC_FS_SHIFT) |
|
|
|
|
(FIFO_MODE_16_15_0 << DAC_FIFOC_FIFO_MODE_SHIFT) |
|
|
|
|
(DRQ_CLR_CNT << DAC_FIFOC_DRQ_CLR_CNT_SHIFT) |
|
|
|
|
(TX_TRIG_LEVEL << DAC_FIFOC_TX_TRIG_LEVEL_SHIFT));
|
|
|
|
|
|
|
|
/* Enable DAC DRQ */
|
|
|
|
val = CODEC_READ(sc, AC_DAC_FIFOC);
|
|
|
|
val |= DAC_FIFOC_DRQ_EN;
|
|
|
|
CODEC_WRITE(sc, AC_DAC_FIFOC, val);
|
|
|
|
} else {
|
|
|
|
/* Flush ADC FIFO */
|
|
|
|
CODEC_WRITE(sc, AC_ADC_FIFOC, ADC_FIFOC_FIFO_FLUSH);
|
|
|
|
|
|
|
|
/* Clear ADC FIFO status */
|
|
|
|
CODEC_WRITE(sc, AC_ADC_FIFOS, CODEC_READ(sc, AC_ADC_FIFOS));
|
|
|
|
|
|
|
|
/* Enable ADC analog left/right channels, MIC1 preamp,
|
|
|
|
* and VMIC pin voltage
|
|
|
|
*/
|
|
|
|
val = CODEC_READ(sc, AC_ADC_ACTL);
|
|
|
|
val |= ADC_ACTL_ADCREN;
|
|
|
|
val |= ADC_ACTL_ADCLEN;
|
|
|
|
val |= ADC_ACTL_PREG1EN;
|
|
|
|
val |= ADC_ACTL_VMICEN;
|
|
|
|
CODEC_WRITE(sc, AC_ADC_ACTL, val);
|
|
|
|
|
|
|
|
/* Configure ADC DMA channel */
|
|
|
|
a10codec_dmaconfig(ch);
|
|
|
|
|
|
|
|
/* Configure ADC FIFO */
|
|
|
|
CODEC_WRITE(sc, AC_ADC_FIFOC,
|
|
|
|
ADC_FIFOC_EN_AD |
|
|
|
|
ADC_FIFOC_RX_FIFO_MODE |
|
|
|
|
(AFMT_CHANNEL(ch->format) == 1 ? ADC_FIFOC_MONO_EN : 0) |
|
|
|
|
(a10codec_fs(ch) << ADC_FIFOC_FS_SHIFT) |
|
|
|
|
(RX_TRIG_LEVEL << ADC_FIFOC_RX_TRIG_LEVEL_SHIFT));
|
|
|
|
|
|
|
|
/* Enable ADC DRQ */
|
|
|
|
val = CODEC_READ(sc, AC_ADC_FIFOC);
|
|
|
|
val |= ADC_FIFOC_DRQ_EN;
|
|
|
|
CODEC_WRITE(sc, AC_ADC_FIFOC, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Start DMA transfer */
|
|
|
|
a10codec_transfer(ch);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
a10codec_stop(struct a10codec_chinfo *ch)
|
|
|
|
{
|
|
|
|
struct a10codec_info *sc = ch->parent;
|
|
|
|
uint32_t val;
|
|
|
|
|
|
|
|
/* Disable DMA channel */
|
|
|
|
SUNXI_DMA_HALT(ch->dmac, ch->dmachan);
|
|
|
|
|
|
|
|
if (ch->dir == PCMDIR_PLAY) {
|
|
|
|
/* Disable DAC analog left/right channels and output mixer */
|
|
|
|
val = CODEC_READ(sc, AC_DAC_ACTL);
|
|
|
|
val &= ~DAC_ACTL_DACAREN;
|
|
|
|
val &= ~DAC_ACTL_DACALEN;
|
|
|
|
val &= ~DAC_ACTL_DACPAS;
|
|
|
|
CODEC_WRITE(sc, AC_DAC_ACTL, val);
|
|
|
|
|
|
|
|
/* Disable DAC DRQ */
|
|
|
|
CODEC_WRITE(sc, AC_DAC_FIFOC, 0);
|
|
|
|
} else {
|
|
|
|
/* Disable ADC analog left/right channels, MIC1 preamp,
|
|
|
|
* and VMIC pin voltage
|
|
|
|
*/
|
|
|
|
val = CODEC_READ(sc, AC_ADC_ACTL);
|
|
|
|
val &= ~ADC_ACTL_ADCREN;
|
|
|
|
val &= ~ADC_ACTL_ADCLEN;
|
|
|
|
val &= ~ADC_ACTL_PREG1EN;
|
|
|
|
val &= ~ADC_ACTL_VMICEN;
|
|
|
|
CODEC_WRITE(sc, AC_ADC_ACTL, val);
|
|
|
|
|
|
|
|
/* Disable ADC DRQ */
|
|
|
|
CODEC_WRITE(sc, AC_ADC_FIFOC, 0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void *
|
|
|
|
a10codec_chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
|
|
|
|
struct pcm_channel *c, int dir)
|
|
|
|
{
|
|
|
|
struct a10codec_info *sc = devinfo;
|
|
|
|
struct a10codec_chinfo *ch = dir == PCMDIR_PLAY ? &sc->play : &sc->rec;
|
|
|
|
int error;
|
|
|
|
|
|
|
|
ch->parent = sc;
|
|
|
|
ch->channel = c;
|
|
|
|
ch->buffer = b;
|
|
|
|
ch->dir = dir;
|
|
|
|
ch->fifo = rman_get_start(sc->res[0]) +
|
|
|
|
(dir == PCMDIR_REC ? AC_ADC_RXDATA : AC_DAC_TXDATA);
|
|
|
|
|
|
|
|
ch->dmac = devclass_get_device(devclass_find("a10dmac"), 0);
|
|
|
|
if (ch->dmac == NULL) {
|
|
|
|
device_printf(sc->dev, "cannot find DMA controller\n");
|
|
|
|
return (NULL);
|
|
|
|
}
|
|
|
|
ch->dmachan = SUNXI_DMA_ALLOC(ch->dmac, false, a10codec_dmaintr, ch);
|
|
|
|
if (ch->dmachan == NULL) {
|
|
|
|
device_printf(sc->dev, "cannot allocate DMA channel\n");
|
|
|
|
return (NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
error = bus_dmamem_alloc(sc->dmat, &ch->dmaaddr,
|
|
|
|
BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &ch->dmamap);
|
|
|
|
if (error != 0) {
|
|
|
|
device_printf(sc->dev, "cannot allocate channel buffer\n");
|
|
|
|
return (NULL);
|
|
|
|
}
|
|
|
|
error = bus_dmamap_load(sc->dmat, ch->dmamap, ch->dmaaddr,
|
|
|
|
sc->dmasize, a10codec_dmamap_cb, ch, BUS_DMA_NOWAIT);
|
|
|
|
if (error != 0) {
|
|
|
|
device_printf(sc->dev, "cannot load DMA map\n");
|
|
|
|
return (NULL);
|
|
|
|
}
|
|
|
|
memset(ch->dmaaddr, 0, sc->dmasize);
|
|
|
|
|
|
|
|
if (sndbuf_setup(ch->buffer, ch->dmaaddr, sc->dmasize) != 0) {
|
|
|
|
device_printf(sc->dev, "cannot setup sndbuf\n");
|
|
|
|
return (NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
return (ch);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
a10codec_chan_free(kobj_t obj, void *data)
|
|
|
|
{
|
|
|
|
struct a10codec_chinfo *ch = data;
|
|
|
|
struct a10codec_info *sc = ch->parent;
|
|
|
|
|
|
|
|
SUNXI_DMA_FREE(ch->dmac, ch->dmachan);
|
|
|
|
bus_dmamap_unload(sc->dmat, ch->dmamap);
|
|
|
|
bus_dmamem_free(sc->dmat, ch->dmaaddr, ch->dmamap);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
a10codec_chan_setformat(kobj_t obj, void *data, uint32_t format)
|
|
|
|
{
|
|
|
|
struct a10codec_chinfo *ch = data;
|
|
|
|
|
|
|
|
ch->format = format;
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t
|
|
|
|
a10codec_chan_setspeed(kobj_t obj, void *data, uint32_t speed)
|
|
|
|
{
|
|
|
|
struct a10codec_chinfo *ch = data;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The codec supports full duplex operation but both DAC and ADC
|
|
|
|
* use the same source clock (PLL2). Limit the available speeds to
|
|
|
|
* those supported by a 24576000 Hz input.
|
|
|
|
*/
|
|
|
|
switch (speed) {
|
|
|
|
case 8000:
|
|
|
|
case 12000:
|
|
|
|
case 16000:
|
|
|
|
case 24000:
|
|
|
|
case 32000:
|
|
|
|
case 48000:
|
|
|
|
ch->speed = speed;
|
|
|
|
break;
|
|
|
|
case 96000:
|
|
|
|
case 192000:
|
|
|
|
/* 96 KHz / 192 KHz mode only supported for playback */
|
|
|
|
if (ch->dir == PCMDIR_PLAY) {
|
|
|
|
ch->speed = speed;
|
|
|
|
} else {
|
|
|
|
ch->speed = 48000;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 44100:
|
|
|
|
ch->speed = 48000;
|
|
|
|
break;
|
|
|
|
case 22050:
|
|
|
|
ch->speed = 24000;
|
|
|
|
break;
|
|
|
|
case 11025:
|
|
|
|
ch->speed = 12000;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
ch->speed = 48000;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return (ch->speed);
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t
|
|
|
|
a10codec_chan_setblocksize(kobj_t obj, void *data, uint32_t blocksize)
|
|
|
|
{
|
|
|
|
struct a10codec_chinfo *ch = data;
|
|
|
|
|
|
|
|
ch->blocksize = blocksize & ~3;
|
|
|
|
|
|
|
|
return (ch->blocksize);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
a10codec_chan_trigger(kobj_t obj, void *data, int go)
|
|
|
|
{
|
|
|
|
struct a10codec_chinfo *ch = data;
|
|
|
|
struct a10codec_info *sc = ch->parent;
|
|
|
|
|
|
|
|
if (!PCMTRIG_COMMON(go))
|
|
|
|
return (0);
|
|
|
|
|
|
|
|
snd_mtxlock(sc->lock);
|
|
|
|
switch (go) {
|
|
|
|
case PCMTRIG_START:
|
|
|
|
ch->run = 1;
|
|
|
|
a10codec_start(ch);
|
|
|
|
break;
|
|
|
|
case PCMTRIG_STOP:
|
|
|
|
case PCMTRIG_ABORT:
|
|
|
|
ch->run = 0;
|
|
|
|
a10codec_stop(ch);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
snd_mtxunlock(sc->lock);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t
|
|
|
|
a10codec_chan_getptr(kobj_t obj, void *data)
|
|
|
|
{
|
|
|
|
struct a10codec_chinfo *ch = data;
|
|
|
|
|
|
|
|
return (ch->pos);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct pcmchan_caps *
|
|
|
|
a10codec_chan_getcaps(kobj_t obj, void *data)
|
|
|
|
{
|
|
|
|
struct a10codec_chinfo *ch = data;
|
|
|
|
|
|
|
|
if (ch->dir == PCMDIR_PLAY) {
|
|
|
|
return (&a10codec_pcaps);
|
|
|
|
} else {
|
|
|
|
return (&a10codec_rcaps);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static kobj_method_t a10codec_chan_methods[] = {
|
|
|
|
KOBJMETHOD(channel_init, a10codec_chan_init),
|
|
|
|
KOBJMETHOD(channel_free, a10codec_chan_free),
|
|
|
|
KOBJMETHOD(channel_setformat, a10codec_chan_setformat),
|
|
|
|
KOBJMETHOD(channel_setspeed, a10codec_chan_setspeed),
|
|
|
|
KOBJMETHOD(channel_setblocksize, a10codec_chan_setblocksize),
|
|
|
|
KOBJMETHOD(channel_trigger, a10codec_chan_trigger),
|
|
|
|
KOBJMETHOD(channel_getptr, a10codec_chan_getptr),
|
|
|
|
KOBJMETHOD(channel_getcaps, a10codec_chan_getcaps),
|
|
|
|
KOBJMETHOD_END
|
|
|
|
};
|
|
|
|
CHANNEL_DECLARE(a10codec_chan);
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Device interface
|
|
|
|
*/
|
|
|
|
|
|
|
|
static int
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a10codec_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "allwinner,sun7i-a20-codec"))
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return (ENXIO);
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device_set_desc(dev, "Allwinner Audio Codec");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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a10codec_attach(device_t dev)
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{
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struct a10codec_info *sc;
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char status[SND_STATUSLEN];
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2016-04-06 23:11:03 +00:00
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clk_t clk_apb, clk_codec;
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2016-02-16 11:45:46 +00:00
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uint32_t val;
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int error;
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sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
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sc->dev = dev;
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sc->lock = snd_mtxcreate(device_get_nameunit(dev), "a10codec softc");
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if (bus_alloc_resources(dev, a10codec_spec, sc->res)) {
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device_printf(dev, "cannot allocate resources for device\n");
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error = ENXIO;
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goto fail;
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}
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/* XXX DRQ types should come from FDT, but how? */
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if (ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-codec") ||
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ofw_bus_is_compatible(dev, "allwinner,sun7i-a20-codec")) {
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sc->drqtype_codec = 19;
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sc->drqtype_sdram = 22;
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} else {
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device_printf(dev, "DRQ types not known for this SoC\n");
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error = ENXIO;
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goto fail;
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}
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sc->dmasize = 131072;
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error = bus_dma_tag_create(
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bus_get_dma_tag(dev),
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|
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4, sc->dmasize, /* alignment, boundary */
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BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
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BUS_SPACE_MAXADDR, /* highaddr */
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NULL, NULL, /* filter, filterarg */
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sc->dmasize, 1, /* maxsize, nsegs */
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sc->dmasize, 0, /* maxsegsize, flags */
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NULL, NULL, /* lockfunc, lockarg */
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|
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&sc->dmat);
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|
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if (error != 0) {
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|
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device_printf(dev, "cannot create DMA tag\n");
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|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
2016-04-06 23:11:03 +00:00
|
|
|
/* Get clocks */
|
|
|
|
error = clk_get_by_ofw_name(dev, "apb", &clk_apb);
|
|
|
|
if (error != 0) {
|
|
|
|
device_printf(dev, "cannot find apb clock\n");
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
error = clk_get_by_ofw_name(dev, "codec", &clk_codec);
|
|
|
|
if (error != 0) {
|
|
|
|
device_printf(dev, "cannot find codec clock\n");
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Gating APB clock for codec */
|
|
|
|
error = clk_enable(clk_apb);
|
|
|
|
if (error != 0) {
|
|
|
|
device_printf(dev, "cannot enable apb clock\n");
|
|
|
|
goto fail;
|
|
|
|
}
|
2016-02-16 11:45:46 +00:00
|
|
|
/* Activate audio codec clock. According to the A10 and A20 user
|
|
|
|
* manuals, Audio_pll can be either 24.576MHz or 22.5792MHz. Most
|
|
|
|
* audio sampling rates require an 24.576MHz input clock with the
|
|
|
|
* exception of 44.1kHz, 22.05kHz, and 11.025kHz. Unfortunately,
|
|
|
|
* both capture and playback use the same clock source so to
|
|
|
|
* safely support independent full duplex operation, we use a fixed
|
|
|
|
* 24.576MHz clock source and don't advertise native support for
|
|
|
|
* the three sampling rates that require a 22.5792MHz input.
|
|
|
|
*/
|
2016-04-06 23:11:03 +00:00
|
|
|
error = clk_set_freq(clk_codec, 24576000, CLK_SET_ROUND_DOWN);
|
|
|
|
if (error != 0) {
|
|
|
|
device_printf(dev, "cannot set codec clock frequency\n");
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
/* Enable audio codec clock */
|
|
|
|
error = clk_enable(clk_codec);
|
|
|
|
if (error != 0) {
|
|
|
|
device_printf(dev, "cannot enable codec clock\n");
|
|
|
|
goto fail;
|
|
|
|
}
|
2016-02-16 11:45:46 +00:00
|
|
|
|
|
|
|
/* Enable DAC */
|
|
|
|
val = CODEC_READ(sc, AC_DAC_DPC);
|
|
|
|
val |= DAC_DPC_EN_DA;
|
|
|
|
CODEC_WRITE(sc, AC_DAC_DPC, val);
|
|
|
|
|
|
|
|
#ifdef notdef
|
|
|
|
error = snd_setup_intr(dev, sc->irq, INTR_MPSAFE, a10codec_intr, sc,
|
|
|
|
&sc->ih);
|
|
|
|
if (error != 0) {
|
|
|
|
device_printf(dev, "could not setup interrupt handler\n");
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
if (mixer_init(dev, &a10codec_mixer_class, sc)) {
|
|
|
|
device_printf(dev, "mixer_init failed\n");
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE);
|
|
|
|
|
|
|
|
if (pcm_register(dev, sc, 1, 1)) {
|
|
|
|
device_printf(dev, "pcm_register failed\n");
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
pcm_addchan(dev, PCMDIR_PLAY, &a10codec_chan_class, sc);
|
|
|
|
pcm_addchan(dev, PCMDIR_REC, &a10codec_chan_class, sc);
|
|
|
|
|
|
|
|
snprintf(status, SND_STATUSLEN, "at %s", ofw_bus_get_name(dev));
|
|
|
|
pcm_setstatus(dev, status);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
|
|
|
|
fail:
|
|
|
|
bus_release_resources(dev, a10codec_spec, sc->res);
|
|
|
|
snd_mtxfree(sc->lock);
|
|
|
|
free(sc, M_DEVBUF);
|
|
|
|
|
|
|
|
return (error);
|
|
|
|
}
|
|
|
|
|
|
|
|
static device_method_t a10codec_pcm_methods[] = {
|
|
|
|
/* Device interface */
|
|
|
|
DEVMETHOD(device_probe, a10codec_probe),
|
|
|
|
DEVMETHOD(device_attach, a10codec_attach),
|
|
|
|
|
|
|
|
DEVMETHOD_END
|
|
|
|
};
|
|
|
|
|
|
|
|
static driver_t a10codec_pcm_driver = {
|
|
|
|
"pcm",
|
|
|
|
a10codec_pcm_methods,
|
|
|
|
PCM_SOFTC_SIZE,
|
|
|
|
};
|
|
|
|
|
|
|
|
DRIVER_MODULE(a10codec, simplebus, a10codec_pcm_driver, pcm_devclass, 0, 0);
|
|
|
|
MODULE_DEPEND(a10codec, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
|
|
|
|
MODULE_VERSION(a10codec, 1);
|