1997-08-14 14:01:36 +00:00
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/*-
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* Copyright (c) 1997 Nicolas Souchu
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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1997-08-16 14:07:26 +00:00
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* $Id: ppcreg.h,v 1.1 1997/08/14 14:01:36 msmith Exp $
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1997-08-14 14:01:36 +00:00
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*
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*/
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#ifndef __PPC_H
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#define __PPC_H
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/*
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* Parallel Port Chipset type.
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*/
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#define SMC_UNKNOWN 0x0
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#define SMC_37C665GT 0x1
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#define SMC_37C666GT 0x2
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#define NS_UNKNOWN 0x3
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#define NS_PC87332 0x4
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#define NS_PC87306 0x5
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#define INTEL_820191AA 0x6
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#define GENERIC 0x7
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/*
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* Generic structure to hold parallel port chipset info.
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*/
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struct ppc_data {
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1997-08-16 14:07:26 +00:00
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int ppc_unit;
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1997-08-14 14:01:36 +00:00
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int ppc_type;
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1997-08-16 14:07:26 +00:00
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#define ppc_base ppc_link.base
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1997-08-14 14:01:36 +00:00
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#define ppc_mode ppc_link.mode
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#define ppc_epp ppc_link.epp_protocol
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#define ppc_irq ppc_link.id_irq
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unsigned char ppc_flags;
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struct ppb_link ppc_link;
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};
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/*
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* Parallel Port Chipset errors. XXX
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*/
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#define PPC_ENOPORT 9
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/*
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* Parallel Port Chipset registers.
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*/
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#define PPC_SPP_DTR 0 /* SPP data register */
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#define PPC_SPP_STR 1 /* SPP status register */
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#define PPC_SPP_CTR 2 /* SPP control register */
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#define PPC_EPP_DATA 4 /* EPP data register (8, 16 or 32 bit) */
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#define PPC_ECP_FIFO 0x400 /* ECP fifo register */
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#define PPC_ECP_ECR 0x402 /* ECP extended control register */
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#define r_dtr(ppc) inb((ppc)->ppc_base + PPC_SPP_DTR)
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#define r_str(ppc) inb((ppc)->ppc_base + PPC_SPP_STR)
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#define r_ctr(ppc) inb((ppc)->ppc_base + PPC_SPP_CTR)
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#define r_epp(ppc) inb((ppc)->ppc_base + PPC_EPP_DATA)
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#define r_ecr(ppc) inb((ppc)->ppc_base + PPC_ECP_ECR)
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#define r_fifo(ppc) inb((ppc)->ppc_base + PPC_ECP_FIFO)
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#define w_dtr(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_DTR, byte)
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#define w_str(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_STR, byte)
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#define w_ctr(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_CTR, byte)
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#define w_epp(ppc,byte) outb((ppc)->ppc_base + PPC_EPP_DATA, byte)
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#define w_ecr(ppc,byte) outb((ppc)->ppc_base + PPC_ECP_ECR, byte)
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#define w_fifo(ppc,byte) outb((ppc)->ppc_base + PPC_ECP_FIFO, byte)
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/*
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* Register defines for the PC873xx parts
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*/
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#define PC873_FER 0x00
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#define PC873_PPENABLE (1<<0)
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#define PC873_FAR 0x01
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#define PC873_PTR 0x02
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#define PC873_CFGLOCK (1<<6)
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#define PC873_EPPRDIR (1<<7)
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#define PC873_FCR 0x03
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#define PC873_ZWS (1<<5)
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#define PC873_ZWSPWDN (1<<6)
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#define PC873_PCR 0x04
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#define PC873_EPPEN (1<<0)
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#define PC873_EPP19 (1<<1)
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#define PC873_ECPEN (1<<2)
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#define PC873_ECPCLK (1<<3)
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#define PC873_PMC 0x06
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#define PC873_TUP 0x07
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#define PC873_SID 0x08
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/*
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* Register defines for the SMC FDC37C66xGT parts.
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*/
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/* Init codes */
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#define SMC665_iCODE 0x55
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#define SMC666_iCODE 0x44
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/* Base configuration ports */
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#define SMC66x_CSR 0x3F0
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#define SMC666_CSR 0x370 /* hard-configured value for 666 */
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/* Bits */
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#define SMC_CR1_ADDR 0x3 /* bit 0 and 1 */
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#define SMC_CR1_MODE 0x8 /* bit 3 */
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#define SMC_CR4_EMODE 0x3 /* bits 0 and 1 */
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#define SMC_CR4_EPPTYPE 0x40 /* bit 6 */
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/* Extended modes */
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#define SMC_SPP 0x0 /* SPP */
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#define SMC_EPPSPP 0x1 /* EPP and SPP */
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#define SMC_ECP 0x2 /* ECP */
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#define SMC_ECPEPP 0x3 /* ECP and EPP */
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#endif
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