333 lines
9.3 KiB
C
333 lines
9.3 KiB
C
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2018 Advanced Micro Devices
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifdef DEBUG
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#define dprintf(fmt, args...) do { \
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printf("%s(): ", __func__); \
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printf(fmt,##args); \
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} while (0)
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#else
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#define dprintf(fmt, args...)
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#endif
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#define AMD_GPIO_PREFIX "AMDGPIO"
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#define AMD_GPIO_NUM_PIN_BANK 4
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#define AMD_GPIO_PINS_PER_BANK 64
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#define AMD_GPIO_PINS_MAX 256 /* 4 banks * 64 pins */
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/* Number of pins in each bank */
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#define AMD_GPIO_PINS_BANK0 63
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#define AMD_GPIO_PINS_BANK1 64
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#define AMD_GPIO_PINS_BANK2 56
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#define AMD_GPIO_PINS_BANK3 32
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#define AMD_GPIO_PIN_PRESENT (AMD_GPIO_PINS_BANK0 + \
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AMD_GPIO_PINS_BANK1 + \
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AMD_GPIO_PINS_BANK2 + \
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AMD_GPIO_PINS_BANK3)
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#define AMDGPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)
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/* Register related macros */
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#define AMDGPIO_PIN_REGISTER(pin) (pin * 4)
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#define WAKE_INT_MASTER_REG 0xfc
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#define EOI_MASK (1 << 29)
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#define WAKE_INT_STATUS_REG0 0x2f8
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#define WAKE_INT_STATUS_REG1 0x2fc
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/* Bit definition of 32 bits of each pin register */
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#define DB_TMR_OUT_OFF 0
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#define DB_TMR_OUT_UNIT_OFF 4
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#define DB_CNTRL_OFF 5
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#define DB_TMR_LARGE_OFF 7
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#define LEVEL_TRIG_OFF 8
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#define ACTIVE_LEVEL_OFF 9
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#define INTERRUPT_ENABLE_OFF 11
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#define INTERRUPT_MASK_OFF 12
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#define WAKE_CNTRL_OFF_S0I3 13
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#define WAKE_CNTRL_OFF_S3 14
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#define WAKE_CNTRL_OFF_S4 15
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#define PIN_STS_OFF 16
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#define DRV_STRENGTH_SEL_OFF 17
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#define PULL_UP_SEL_OFF 19
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#define PULL_UP_ENABLE_OFF 20
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#define PULL_DOWN_ENABLE_OFF 21
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#define OUTPUT_VALUE_OFF 22
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#define OUTPUT_ENABLE_OFF 23
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#define SW_CNTRL_IN_OFF 24
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#define SW_CNTRL_EN_OFF 25
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#define INTERRUPT_STS_OFF 28
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#define WAKE_STS_OFF 29
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#define DB_TMR_OUT_MASK 0xFUL
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#define DB_CNTRL_MASK 0x3UL
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#define ACTIVE_LEVEL_MASK 0x3UL
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#define DRV_STRENGTH_SEL_MASK 0x3UL
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#define DB_TYPE_NO_DEBOUNCE 0x0UL
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#define DB_TYPE_PRESERVE_LOW_GLITCH 0x1UL
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#define DB_TYPE_PRESERVE_HIGH_GLITCH 0x2UL
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#define DB_TYPE_REMOVE_GLITCH 0x3UL
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#define EDGE_TRIGGER 0x0UL
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#define LEVEL_TRIGGER 0x1UL
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#define ACTIVE_HIGH 0x0UL
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#define ACTIVE_LOW 0x1UL
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#define BOTH_EDGE 0x2UL
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#define ENABLE_INTERRUPT 0x1UL
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#define DISABLE_INTERRUPT 0x0UL
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#define ENABLE_INTERRUPT_MASK 0x0UL
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#define DISABLE_INTERRUPT_MASK 0x1UL
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#define CLR_INTR_STAT 0x1UL
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#define BIT(bit) (1 << bit)
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#define GPIO_PIN_INFO(p, n) { .pin_num = (p), .pin_name = (n) }
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struct pin_info {
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int pin_num;
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char *pin_name;
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};
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/* Pins exposed to drivers */
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static const struct pin_info kernzp_pins[] = {
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GPIO_PIN_INFO(0, "PIN_0"),
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GPIO_PIN_INFO(1, "PIN_1"),
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GPIO_PIN_INFO(2, "PIN_2"),
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GPIO_PIN_INFO(3, "PIN_3"),
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GPIO_PIN_INFO(4, "PIN_4"),
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GPIO_PIN_INFO(5, "PIN_5"),
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GPIO_PIN_INFO(6, "PIN_6"),
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GPIO_PIN_INFO(7, "PIN_7"),
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GPIO_PIN_INFO(8, "PIN_8"),
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GPIO_PIN_INFO(9, "PIN_9"),
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GPIO_PIN_INFO(10, "PIN_10"),
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GPIO_PIN_INFO(11, "PIN_11"),
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GPIO_PIN_INFO(12, "PIN_12"),
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GPIO_PIN_INFO(13, "PIN_13"),
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GPIO_PIN_INFO(14, "PIN_14"),
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GPIO_PIN_INFO(15, "PIN_15"),
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GPIO_PIN_INFO(16, "PIN_16"),
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GPIO_PIN_INFO(17, "PIN_17"),
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GPIO_PIN_INFO(18, "PIN_18"),
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GPIO_PIN_INFO(19, "PIN_19"),
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GPIO_PIN_INFO(20, "PIN_20"),
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GPIO_PIN_INFO(23, "PIN_23"),
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GPIO_PIN_INFO(24, "PIN_24"),
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GPIO_PIN_INFO(25, "PIN_25"),
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GPIO_PIN_INFO(26, "PIN_26"),
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GPIO_PIN_INFO(39, "PIN_39"),
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GPIO_PIN_INFO(40, "PIN_40"),
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GPIO_PIN_INFO(43, "PIN_43"),
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GPIO_PIN_INFO(46, "PIN_46"),
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GPIO_PIN_INFO(47, "PIN_47"),
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GPIO_PIN_INFO(48, "PIN_48"),
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GPIO_PIN_INFO(49, "PIN_49"),
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GPIO_PIN_INFO(50, "PIN_50"),
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GPIO_PIN_INFO(51, "PIN_51"),
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GPIO_PIN_INFO(52, "PIN_52"),
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GPIO_PIN_INFO(53, "PIN_53"),
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GPIO_PIN_INFO(54, "PIN_54"),
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GPIO_PIN_INFO(55, "PIN_55"),
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GPIO_PIN_INFO(56, "PIN_56"),
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GPIO_PIN_INFO(57, "PIN_57"),
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GPIO_PIN_INFO(58, "PIN_58"),
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GPIO_PIN_INFO(59, "PIN_59"),
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GPIO_PIN_INFO(60, "PIN_60"),
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GPIO_PIN_INFO(61, "PIN_61"),
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GPIO_PIN_INFO(62, "PIN_62"),
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GPIO_PIN_INFO(64, "PIN_64"),
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GPIO_PIN_INFO(65, "PIN_65"),
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GPIO_PIN_INFO(66, "PIN_66"),
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GPIO_PIN_INFO(68, "PIN_68"),
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GPIO_PIN_INFO(69, "PIN_69"),
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GPIO_PIN_INFO(70, "PIN_70"),
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GPIO_PIN_INFO(71, "PIN_71"),
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GPIO_PIN_INFO(72, "PIN_72"),
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GPIO_PIN_INFO(74, "PIN_74"),
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GPIO_PIN_INFO(75, "PIN_75"),
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GPIO_PIN_INFO(76, "PIN_76"),
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GPIO_PIN_INFO(84, "PIN_84"),
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GPIO_PIN_INFO(85, "PIN_85"),
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GPIO_PIN_INFO(86, "PIN_86"),
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GPIO_PIN_INFO(87, "PIN_87"),
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GPIO_PIN_INFO(88, "PIN_88"),
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GPIO_PIN_INFO(89, "PIN_89"),
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GPIO_PIN_INFO(90, "PIN_90"),
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GPIO_PIN_INFO(91, "PIN_91"),
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GPIO_PIN_INFO(92, "PIN_92"),
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GPIO_PIN_INFO(93, "PIN_93"),
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GPIO_PIN_INFO(95, "PIN_95"),
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GPIO_PIN_INFO(96, "PIN_96"),
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GPIO_PIN_INFO(97, "PIN_97"),
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GPIO_PIN_INFO(98, "PIN_98"),
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GPIO_PIN_INFO(99, "PIN_99"),
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GPIO_PIN_INFO(100, "PIN_100"),
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GPIO_PIN_INFO(101, "PIN_101"),
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GPIO_PIN_INFO(102, "PIN_102"),
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GPIO_PIN_INFO(113, "PIN_113"),
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GPIO_PIN_INFO(114, "PIN_114"),
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GPIO_PIN_INFO(115, "PIN_115"),
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GPIO_PIN_INFO(116, "PIN_116"),
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GPIO_PIN_INFO(117, "PIN_117"),
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GPIO_PIN_INFO(118, "PIN_118"),
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GPIO_PIN_INFO(119, "PIN_119"),
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GPIO_PIN_INFO(120, "PIN_120"),
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GPIO_PIN_INFO(121, "PIN_121"),
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GPIO_PIN_INFO(122, "PIN_122"),
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GPIO_PIN_INFO(126, "PIN_126"),
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GPIO_PIN_INFO(129, "PIN_129"),
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GPIO_PIN_INFO(130, "PIN_130"),
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GPIO_PIN_INFO(131, "PIN_131"),
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GPIO_PIN_INFO(132, "PIN_132"),
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GPIO_PIN_INFO(133, "PIN_133"),
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GPIO_PIN_INFO(135, "PIN_135"),
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GPIO_PIN_INFO(136, "PIN_136"),
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GPIO_PIN_INFO(137, "PIN_137"),
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GPIO_PIN_INFO(138, "PIN_138"),
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GPIO_PIN_INFO(139, "PIN_139"),
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GPIO_PIN_INFO(140, "PIN_140"),
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GPIO_PIN_INFO(141, "PIN_141"),
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GPIO_PIN_INFO(142, "PIN_142"),
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GPIO_PIN_INFO(143, "PIN_143"),
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GPIO_PIN_INFO(144, "PIN_144"),
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GPIO_PIN_INFO(145, "PIN_145"),
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GPIO_PIN_INFO(146, "PIN_146"),
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GPIO_PIN_INFO(147, "PIN_147"),
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GPIO_PIN_INFO(148, "PIN_148"),
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GPIO_PIN_INFO(166, "PIN_166"),
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GPIO_PIN_INFO(167, "PIN_167"),
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GPIO_PIN_INFO(168, "PIN_168"),
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GPIO_PIN_INFO(169, "PIN_169"),
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GPIO_PIN_INFO(170, "PIN_170"),
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GPIO_PIN_INFO(171, "PIN_171"),
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GPIO_PIN_INFO(172, "PIN_172"),
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GPIO_PIN_INFO(173, "PIN_173"),
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GPIO_PIN_INFO(174, "PIN_174"),
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GPIO_PIN_INFO(175, "PIN_175"),
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GPIO_PIN_INFO(176, "PIN_176"),
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GPIO_PIN_INFO(177, "PIN_177"),
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};
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#define AMD_GPIO_PINS_EXPOSED nitems(kernzp_pins)
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static const unsigned i2c0_pins[] = {145, 146};
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static const unsigned i2c1_pins[] = {147, 148};
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static const unsigned i2c2_pins[] = {113, 114};
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static const unsigned i2c3_pins[] = {19, 20};
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static const unsigned i2c4_pins[] = {149, 150};
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static const unsigned i2c5_pins[] = {151, 152};
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static const unsigned uart0_pins[] = {135, 136, 137, 138, 139};
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static const unsigned uart1_pins[] = {140, 141, 142, 143, 144};
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struct amd_pingroup {
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const char *name;
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const unsigned *pins;
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unsigned npins;
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};
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static const struct amd_pingroup kernzp_groups[] = {
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{
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.name = "i2c0",
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.pins = i2c0_pins,
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.npins = 2,
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},
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{
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.name = "i2c1",
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.pins = i2c1_pins,
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.npins = 2,
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},
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{
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.name = "i2c2",
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.pins = i2c2_pins,
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.npins = 2,
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},
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{
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.name = "i2c3",
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.pins = i2c3_pins,
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.npins = 2,
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},
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{
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.name = "i2c4",
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.pins = i2c4_pins,
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.npins = 2,
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},
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{
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.name = "i2c5",
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.pins = i2c5_pins,
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.npins = 2,
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},
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{
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.name = "uart0",
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.pins = uart0_pins,
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.npins = 5,
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},
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{
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.name = "uart1",
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.pins = uart1_pins,
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.npins = 5,
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},
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};
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/* Macros for driver mutex locking */
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#define AMDGPIO_LOCK_INIT(_sc) \
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mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
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"amdgpio", MTX_SPIN)
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#define AMDGPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
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#define AMDGPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
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#define AMDGPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
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#define AMDGPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
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#define AMDGPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED)
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struct amdgpio_softc {
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ACPI_HANDLE sc_handle;
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device_t sc_dev;
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device_t sc_busdev;
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const char* sc_bank_prefix;
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int sc_nbanks;
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int sc_npins;
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int sc_ngroups;
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struct mtx sc_mtx;
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struct resource *sc_res[AMD_GPIO_NUM_PIN_BANK + 1];
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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struct gpio_pin sc_gpio_pins[AMD_GPIO_PINS_MAX];
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const struct pin_info *sc_pin_info;
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const struct amd_pingroup *sc_groups;
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};
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struct amdgpio_sysctl {
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struct amdgpio_softc *sc;
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uint32_t pin;
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};
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