2010-03-03 15:05:58 +00:00
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/*-
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* Copyright (c) 2010 George V. Neville-Neil <gnn@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_HWPMC_MIPS24K_H_
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#define _DEV_HWPMC_MIPS24K_H_
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#define MIPS24K_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | \
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PMC_CAP_SYSTEM | PMC_CAP_EDGE | \
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PMC_CAP_THRESHOLD | PMC_CAP_READ | \
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PMC_CAP_WRITE | PMC_CAP_INVERT | \
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PMC_CAP_QUALIFIER)
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2011-10-07 06:13:38 +00:00
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#define MIPS24K_PMC_INTERRUPT_ENABLE 0x10 /* Enable interrupts */
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2010-03-03 15:05:58 +00:00
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#define MIPS24K_PMC_USER_ENABLE 0x08 /* Count in USER mode */
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#define MIPS24K_PMC_SUPER_ENABLE 0x04 /* Count in SUPERVISOR mode */
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#define MIPS24K_PMC_KERNEL_ENABLE 0x02 /* Count in KERNEL mode */
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#define MIPS24K_PMC_ENABLE (MIPS24K_PMC_USER_ENABLE | \
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MIPS24K_PMC_SUPER_ENABLE | \
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MIPS24K_PMC_KERNEL_ENABLE)
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2011-10-07 06:13:38 +00:00
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/*
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* Interrupts are posted when bit 31 of the relevant
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* counter is set.
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*/
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#define MIPS24K_RELOAD_COUNT_TO_PERFCTR_VALUE(R) (0x80000000 - (R))
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#define MIPS24K_PERFCTR_VALUE_TO_RELOAD_COUNT(P) ((P) - 0x80000000)
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2010-03-03 15:05:58 +00:00
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#define MIPS24K_PMC_SELECT 0x4 /* Which bit position the event starts at. */
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#define MIPS24K_PMC_OFFSET 2 /* Control registers are 0, 2, 4, etc. */
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#define MIPS24K_PMC_MORE 0x800000 /* Test for more PMCs (bit 31) */
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#ifdef _KERNEL
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/* MD extension for 'struct pmc' */
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struct pmc_md_mips24k_pmc {
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uint32_t pm_mips24k_evsel;
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};
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#endif /* _KERNEL */
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#endif /* _DEV_HWPMC_MIPS_H_ */
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