229 lines
9.4 KiB
C
229 lines
9.4 KiB
C
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/*
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* Copyright (c) 1999 HAYAKAWA Koichi. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by HAYAKAWA Koichi.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* $Id: pccbbreg.h,v 1.4 1999/08/02 01:35:50 kanaoka Exp $ */
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/* $FreeBSD$ */
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#ifndef _DEV_PCI_PCCBBREG_H_
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#define _DEV_PCI_PCCBBREG_H_
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#define PCI_SOCKBASE 0x10 /* Socket Base Address Register */
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#define PCI_BUSNUM 0x18 /* latency timer, Subordinate bus number */
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#define PCI_BCR_INTR 0x3C /* intr line, intr pin, bridge control regs */
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#define PCI_LEGACY 0x44 /* legacy IO register address (32 bits) */
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#define PCI_CBCTRL 0x90 /* Retry status, Card ctrl, Device ctrl */
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#define PCI_CLASS_INTERFACE_MASK 0xffffff00
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#define PCI_CLASS_INTERFACE_YENTA 0x06070000
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#define PCI_BHLC_REG 0x0c
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#define PCI_LATTIMER_SHIFT 8
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#define PCI_LATTIMER_MASK 0xff
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#define PCI_LATTIMER(bhlcr) \
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(((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK)
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#define PCI_SOCKBASE 0x10 /* Socket Base Address Register */
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#define PCI_BUSNUM 0x18 /* latency timer, Subordinate bus number */
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#define PCI_BCR_INTR 0x3C /* intr line, intr pin, bridge control regs */
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#define PCI_LEGACY 0x44 /* legacy IO register address (32 bits) */
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#define PCI_CBCTRL 0x90 /* Retry status, Card ctrl, Device ctrl */
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#define CB_SOCKET_EVENT 0x00 /* offset of cardbus socket event reg */
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#define CB_SOCKET_MASK 0x04 /* offset of cardbus socket mask register */
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#define CB_SOCKET_STAT 0x08 /* offset of cardbus socket present-state */
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#define CB_SOCKET_FORCE 0x0c /* offset of cardbus socket force event */
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#define CB_SOCKET_CTRL 0x10 /* offset of cardbus socket control reg */
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/* CardBus latency timer, Subordinate bus no, CardBus bus no and PCI bus no */
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#define PCI_CB_LSCP_REG 0x18
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/* CardBus memory and io windows */
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#define PCI_CB_MEMBASE0 0x1c
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#define PCI_CB_MEMLIMIT0 0x20
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#define PCI_CB_MEMBASE1 0x24
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#define PCI_CB_MEMLIMIT1 0x28
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#define PCI_CB_IOBASE0 0x2c
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#define PCI_CB_IOLIMIT0 0x30
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#define PCI_CB_IOBASE1 0x34
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#define PCI_CB_IOLIMIT1 0x38
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/* PCI_CB_LSCP_REG */
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#define PCI_CB_LATENCY_SHIFT 24
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#define PCI_CB_LATENCY_MASK 0xff
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#define PCI_CB_LATENCY(x) (((x) >> PCI_CB_LATENCY_SHIFT) & PCI_CB_LATENCY_MASK)
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/* PCI_BCR_INTR bits for generic PCI-CardBus bridge */
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#define CB_BCR_INTR_IREQ_ENABLE 0x0800000
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#define CB_BCR_WRITE_POST_ENABLE 0x4000000
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/* PCI_CBCTRL bits for TI PCI113X */
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#define PCI113X_CBCTRL_INT_SERIAL 0x040000
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#define PCI113X_CBCTRL_INT_ISA 0x020000
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#define PCI113X_CBCTRL_INT_MASK 0x060000
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#define PCI113X_CBCTRL_RIENB 0x8000 /* Ring indicate output enable */
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#define PCI113X_CBCTRL_ZVENAB 0x4000 /* ZV mode enable */
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#define PCI113X_CBCTRL_PCI_IRQ_ENA 0x2000 /* PCI intr enable (funct and CSC) */
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#define PCI113X_CBCTRL_PCI_INTR 0x1000 /* PCI functional intr req */
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#define PCI113X_CBCTRL_PCI_CSC 0x0800 /* CSC intr route to PCI */
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#define PCI113X_CBCTRL_PCI_CSC_D 0x0400 /* unknown */
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#define PCI113X_CBCTRL_SPK_ENA 0x0200 /* Speaker enable */
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#define PCI113X_CBCTRL_INTR_DET 0x0100 /* functional interrupt detect */
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/* PCI_CBCTRL bits for TI PCI12XX */
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#define PCI12XX_CBCTRL_INT_SERIAL 0x040000
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#define PCI12XX_CBCTRL_INT_ISA 0x020000
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#define PCI12XX_CBCTRL_INT_PCI 0x000000
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#define PCI12XX_CBCTRL_INT_MASK 0x060000
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#define PCI12XX_CBCTRL_RIENB 0x8000 /* Ring indicate output enable */
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#define PCI12XX_CBCTRL_ZVENAB 0x4000 /* ZV mode enable */
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#define PCI12XX_CBCTRL_AUD2MUX 0x0400 /* unknown */
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#define PCI12XX_CBCTRL_SPK_ENA 0x0200 /* Speaker enable */
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#define PCI12XX_CBCTRL_INTR_DET 0x0100 /* functional interrupt detect */
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/* PCI_BCR_INTR additional bit for RF5C46[567] */
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#define CB_BCRI_RL_3E0_ENA 0x08000000
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#define CB_BCRI_RL_3E2_ENA 0x10000000
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/*
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* Special resister definition for Toshiba ToPIC95/97
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* These values are borrowed from pcmcia-cs/Linux.
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*/
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#define TOPIC_SOCKET_CTRL 0x90
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# define TOPIC_SOCKET_CTRL_SCR_IRQSEL 0x00000001 /* PCI intr */
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#define TOPIC_SLOT_CTRL 0xa0
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# define TOPIC_SLOT_CTRL_SLOTON 0x00000080
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# define TOPIC_SLOT_CTRL_SLOTEN 0x00000040
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# define TOPIC_SLOT_CTRL_ID_LOCK 0x00000020
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# define TOPIC_SLOT_CTRL_ID_WP 0x00000010
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# define TOPIC_SLOT_CTRL_PORT_MASK 0x0000000c
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# define TOPIC_SLOT_CTRL_PORT_SHIFT 2
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# define TOPIC_SLOT_CTRL_OSF_MASK 0x00000003
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# define TOPIC_SLOT_CTRL_OSF_SHIFT 0
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# define TOPIC_SLOT_CTRL_INTB 0x00002000
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# define TOPIC_SLOT_CTRL_INTA 0x00001000
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# define TOPIC_SLOT_CTRL_INT_MASK 0x00003000
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# define TOPIC_SLOT_CTRL_CLOCK_MASK 0x00000c00
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# define TOPIC_SLOT_CTRL_CLOCK_2 0x00000800 /* PCI Clock/2 */
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# define TOPIC_SLOT_CTRL_CLOCK_1 0x00000400 /* PCI Clock */
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# define TOPIC_SLOT_CTRL_CLOCK_0 0x00000000 /* no clock */
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# define TOPIC_SLOT_CTRL_CARDBUS 0x80000000
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# define TOPIC_SLOT_CTRL_VS1 0x04000000
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# define TOPIC_SLOT_CTRL_VS2 0x02000000
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# define TOPIC_SLOT_CTRL_SWDETECT 0x01000000
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#define TOPIC_REG_CTRL 0x00a4
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# define TOPIC_REG_CTRL_RESUME_RESET 0x80000000
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# define TOPIC_REG_CTRL_REMOVE_RESET 0x40000000
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# define TOPIC97_REG_CTRL_CLKRUN_ENA 0x20000000
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# define TOPIC97_REG_CTRL_TESTMODE 0x10000000
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# define TOPIC97_REG_CTRL_IOPLUP 0x08000000
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# define TOPIC_REG_CTRL_BUFOFF_PWROFF 0x02000000
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# define TOPIC_REG_CTRL_BUFOFF_SIGOFF 0x01000000
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# define TOPIC97_REG_CTRL_CB_DEV_MASK 0x0000f800
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# define TOPIC97_REG_CTRL_CB_DEV_SHIFT 11
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# define TOPIC97_REG_CTRL_RI_DISABLE 0x00000004
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# define TOPIC97_REG_CTRL_CAUDIO_OFF 0x00000002
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# define TOPIC_REG_CTRL_CAUDIO_INVERT 0x00000001
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/* socket event register (CB_SOCKET_EVENT) elements */
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#define CB_SOCKET_EVENT_CSTS 0x01 /* CARDSTS event occurs */
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#define CB_SOCKET_EVENT_CD 0x06 /* CD event occurs */
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#define CB_SOCKET_EVENT_CD1 0x02 /* CD1 event occurs */
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#define CB_SOCKET_EVENT_CD2 0x04 /* CD2 event occurs */
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#define CB_SOCKET_EVENT_POWER 0x08 /* Power cycle event occurs */
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/* socket mask register (CB_SOCKET_MASK) elements */
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#define CB_SOCKET_MASK_CSTS 0x01 /* CARDSTS event mask */
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#define CB_SOCKET_MASK_CD 0x06 /* CD event mask */
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#define CB_SOCKET_MASK_POWER 0x08 /* Power cycle event mask */
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/* socket present-state register (CB_SOCKET_STAT) elements */
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#define CB_SOCKET_STAT_CARDSTS 0x01 /* card status change bit */
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#define CB_SOCKET_STAT_CD1 0x02 /* card detect 1 */
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#define CB_SOCKET_STAT_CD2 0x04 /* card detect 2 */
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#define CB_SOCKET_STAT_CD 0x06 /* card detect 1 and 2 */
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#define CB_SOCKET_STAT_PWRCYCLE 0x08 /* power cycle */
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#define CB_SOCKET_STAT_16BIT 0x010 /* 16-bit card */
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#define CB_SOCKET_STAT_CB 0x020 /* cardbus card */
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#define CB_SOCKET_STAT_IREQ 0x040 /* READY(~IREQ)//(~CINT) bit */
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#define CB_SOCKET_STAT_NOTCARD 0x080 /* Inserted card is unrecognisable */
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#define CB_SOCKET_STAT_DATALOST 0x0100 /* data lost */
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#define CB_SOCKET_STAT_BADVCC 0x0200 /* Bad Vcc Request */
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#define CB_SOCKET_STAT_5VCARD 0x0400 /* 5 V Card */
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#define CB_SOCKET_STAT_3VCARD 0x0800 /* 3.3 V Card */
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#define CB_SOCKET_STAT_XVCARD 0x01000 /* X.X V Card */
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#define CB_SOCKET_STAT_YVCARD 0x02000 /* Y.Y V Card */
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#define CB_SOCKET_STAT_5VSOCK 0x10000000 /* 5 V Socket */
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#define CB_SOCKET_STAT_3VSOCK 0x20000000 /* 3.3 V Socket */
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#define CB_SOCKET_STAT_XVSOCK 0x20000000 /* X.X V Socket */
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#define CB_SOCKET_STAT_YVSOCK 0x20000000 /* Y.Y V Socket */
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/* socket force event register (CB_SOCKET_FORCE) elements */
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#define CB_SOCKET_FORCE_BADVCC 0x0200 /* Bad Vcc Request */
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/* socket control register (CB_SOCKET_CTRL) elements */
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#define CB_SOCKET_CTRL_VPPMASK 0x07
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#define CB_SOCKET_CTRL_VPP_OFF 0x00
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#define CB_SOCKET_CTRL_VPP_12V 0x01
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#define CB_SOCKET_CTRL_VPP_5V 0x02
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#define CB_SOCKET_CTRL_VPP_3V 0x03
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#define CB_SOCKET_CTRL_VPP_XV 0x04
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#define CB_SOCKET_CTRL_VPP_YV 0x05
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#define CB_SOCKET_CTRL_VCCMASK 0x070
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#define CB_SOCKET_CTRL_VCC_OFF 0x000
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#define CB_SOCKET_CTRL_VCC_5V 0x020
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#define CB_SOCKET_CTRL_VCC_3V 0x030
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#define CB_SOCKET_CTRL_VCC_XV 0x040
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#define CB_SOCKET_CTRL_VCC_YV 0x050
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#define CB_SOCKET_CTRL_STOPCLK 0x080
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/* PCCARD VOLTAGE */
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#define PCCARD_VCC_UKN 0x00 /* unknown */
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#define PCCARD_VCC_5V 0x01
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#define PCCARD_VCC_3V 0x02
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#define PCCARD_VCC_XV 0x04
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#define PCCARD_VCC_YV 0x08
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#endif /* _DEV_PCI_PCCBBREG_H_ */
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