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freebsd-nq/sys/dev/aic7xxx/aic79xx_pci.c

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Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
/*
* Product specific probe and attach routines for:
* aic7901 and aic7902 SCSI controllers
*
* Copyright (c) 1994-2001 Justin T. Gibbs.
Identify new controllers and the aic7901A. Move interrupt enable to the OSM. Remove some debugging messages. Remove chip bug workarounds for non-production asics.
2002-08-31 06:52:27 +00:00
* Copyright (c) 2000-2002 Adaptec Inc.
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
aic79xx.c: Allow 500us between pauses in ahd_pause_and_flushwork(). The maximum we will wait is now 500ms. In the same routine, remove any attempt to clear ENSELO. Let the firmware do it once the current selection has completed. This avoids some race conditions having to do with non-packetized completions and the auto-clearing of ENSELO on packetized completions. Also avoid attempts to clear critical sections when interrups are pending. We are going to loop again anyway, so clearing critical sections is a waste of time. It also may not be possible to clear a critical section if the source of the interrupt was a SEQINT. aic79xx_pci.c: Use the Generic 9005 mask when looking for generic 7901B parts. This allows the driver to attach to 7901B parts on motherboards using a non-Adaptec subvendor ID. aic79xx_inline.h: Test for the SCBRAM_RD_BUG against the bugs field, not the flags field in the softc. aic79xx.c: Cancel pending transactions on devices that respond with a selection timeout. This decreases the duration of timeout recovery when a device disappears. aic79xx.c: Don't bother forcing renegotiation on a selection timeout now that we use the device reset handler to abort any pending commands on the target. The device reset handler already takes us down to async narrow and forces a renegotiation. In the device reset handlers, only send a BDR sent async event if the status is not CAM_SEL_TIMEOUT. This avoids sending this event in the selection timeout case aic79xx.c: Modify the Core timeout handler to verify that another command has the potential to timeout before passing off a command timeout as due to some other command. This safety measure is added in response to a timeout recovery failure on H2B where it appears that incoming reselection status was lost during a drive pull test. In that case, the recovery handler continued to wait for the command that was active on the bus indefinetly. While the root cause of the above issue is still being determined seems a prudent safeguard. aic79xx_pci.c: Add a specific probe entry for the Dell OEM 39320(B). aic79xx.c: aic79xx.h: aic79xx.reg: aic79xx.seq: Modify the aic79xx firmware to never cross a cacheline or ADB boundary when DMA'ing completion entries to the host. In PCI mode, at least in 32/33 configurations, the SCB DMA engine may lose its place in the data-stream should the target force a retry on something other than an 8byte aligned boundary. In PCI-X mode, we do this to avoid split transactions since many chipsets seem to be unable to format proper split completions to continue the data transfer. The above change allows us to drop our completion entries from 8 bytes to 4. We were using 8 byte entries to ensure that PCI retries could only occur on an 8byte aligned boundary. Now that the sequencer guarantees this by splitting up completions, we can safely drop the size to 4 bytes (2 byte tag, one byte SG_RESID, one byte pad). Both the split-completion and PCI retry problems only show up under high tag load when interrupt coalescing is being especially effective. The switch from a 2byte completion entry to an 8 byte entry to solve the PCI problem increased the chance of incurring a split in PCI-X mode when multiple transactions were completed at once. Dropping the completion size to 4 bytes also means that we can complete more commands in a single DMA (128byte FIFO -> 32 commands instead of 16). aic79xx.c: Modify the SCSIINT handler to defer clearing sequencer critical sections to the individual interrupt handlers. This allows us to immediately disable any outgoing selections in the case of an unexpected busfree so we don't inadvertantly clear ENSELO *after* a new selection has started. Doing so may cause the sequencer to miss a successful selection. In ahd_update_pending_scbs(), only clear ENSELO if the bus is currently busy and a selection is not already in progress or the sequencer has yet to handle a pending selection. While we want to ensure that the selection for the SCB at the head of the selection queue is restarted so that any change in negotiation request can take effect, we can't clobber pending selection state without confusing the sequencer into missing a selection.
2004-05-11 20:46:05 +00:00
* $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#88 $
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
*/
#ifdef __linux__
#include "aic79xx_osm.h"
#include "aic79xx_inline.h"
#else
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
#include <dev/aic7xxx/aic79xx_osm.h>
#include <dev/aic7xxx/aic79xx_inline.h>
#endif
static __inline uint64_t
ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
{
uint64_t id;
id = subvendor
| (subdevice << 16)
| ((uint64_t)vendor << 32)
| ((uint64_t)device << 48);
return (id);
}
#define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
aic79xx.c: aic79xx.seq: Convert the COMPLETE_DMA_SCB list to an "stailq". This allows us to safely keep the SCB that is currently being DMA'ed back the host on the head of the list while processing completions off of the bus. The newly completed SCBs are appended to the tail of the queue. In the past, we just dequeued the SCB that was in flight from the list, but this could result in a lost completion should the host perform certain types of error recovery that must cancel all in-flight SCB DMA operations. Switch from using a 16bit completion entry, holding just the tag and the completion valid bit, to a 64bit completion entry that also contains a "status packet valid" indicator. This solves two problems: o The SCB DMA engine on at least Rev B. silicon does not properly deal with a PCI disconnect that occurs at a non-64bit aligned offset in the chips "source buffer". When the transfer is resumed, the DMA engine continues at the correct offset, but may wrap to the head of the buffer causing duplicate completions to be reported to the host. By using a completion buffer in host memory that is 64bit aligned and using 64bit completion entries, such disconnects should only occur at aligned addresses. This assumes that the host bridge will only disconnect on cache-line boundaries and that cache-lines are multpiles of 64bits. o By embedding the status information in the completion entry we can avoid an extra memory reference to the HSCB for commands that complete without error. Use the comparison of a "host freeze count" and a "sequencer freeze count" to allow the host to process most SCBs that complete with non-zero status without having to clear critical sections. Instead the host can just pause the sequencer, performs any necessary cleanup in the waiting for selection list, increments its freeze count on the controller, and unpauses. This is only possible because the sequencer defers completions of SCBs with bad status until after all pending selections have completed. The sequencer then avoids referencing any data structures the host may touch during completion of the SCB until the freeze counts match. aic79xx.c: Change the strategy for allocating our sentinal HSCB for the QINFIFO. In the past, this allocation was tacked onto the QOUTFIFO allocation. Now that the qoutfifo has grown to accomodate larger completion entries, the old approach will result in a 64byte allocation that costs an extra page of coherent memory. We now do this extra allocation via ahd_alloc_scbs() where the "unused space" can be used to allocate "normal" HSCBs. In our packetized busfree handler, use the ENSELO bit to differentiate between packetized and non-packetized unexpected busfree events that occur just after selection, but before the sequencer has had the oportunity to service the selection. When cleaning out the waiting for selection list, use the SCSI mode instead of the command channel mode. The SCB pointer in the command channel mode may be referenced by the SCB dma engine even while the sequencer is paused, whereas the SCSI mode SCB pointer is only accessed by the sequencer. Print the "complete on qfreeze" sequencer SCB completion list in ahd_dump_card_state(). This list holds all SCB completions that are deferred until a pending select-out qfreeze event has taken effect. aic79xx.h: Add definitions and structures to handle the new SCB completion scheme. Add a controller flag that indicates if the controller is in HostRAID mode. aic79xx.reg: Remove macros used for toggling from one data fifo mode to the other. They have not been in use for some time. Add scratch ram fields for our new qfreeze count scheme, converting the complete dma list into an "stailq", and providing for the "complete on qfreeze" SCB completion list. Some other fields were moved to retain proper field alignment (alignment >= field size in bytes). aic79xx.seq: Add code to our idle loop to: o Process deferred completions once a qfreeze event has taken full effect. o Thaw the queue once the sequencer and host qfreeze counts match. Generate 64bit completion entries passing the SCB_SGPTR field as the "good status" indicator. The first bit in this field is only set if we have a valid status packet to send to the host. Convert the COMPLETE_DMA_SCB list to an "stailq". When using "setjmp" to register an idle loop handler, do not combine the "ret" with the block move to pop the stack address in the same instruction. At least on the A, this results in a return to the setjmp caller, not to the new address at the top of the stack. Since we want the latter (we want the newly registered handler to only be invoked from the idle loop), we must use a separate ret instruction. Add a few missing critical sections. Close a race condition that can occur on Rev A. silicon. If both FIFOs happen to be allocated before the sequencer has a chance to service the FIFO that was allocated first, we must take special care to service the FIFO that is not active on the SCSI bus first. This guarantees that a FIFO will be freed to handle any snapshot requests for the FIFO that is still on the bus. Chosing the incorrect FIFO will result in deadlock. Update comments. aic79xx_inline.h Correct the offset calculation for the syncing of our qoutfifo. Update ahd_check_cmdcmpltqueues() for the larger completion entries. aic79xx_pci.c: Attach to HostRAID controllers by default. In the future I may add a sysctl to modify the behavior, but since FreeBSD does not have any HostRAID drivers, failing to attach just results in more email and bug reports for the author. MFC After: 1week
2004-02-04 16:38:38 +00:00
#define ID_ALL_IROC_MASK 0xFF7FFFFFFFFFFFFFull
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
#define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
#define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull
aic79xx.c: aic79xx.seq: Convert the COMPLETE_DMA_SCB list to an "stailq". This allows us to safely keep the SCB that is currently being DMA'ed back the host on the head of the list while processing completions off of the bus. The newly completed SCBs are appended to the tail of the queue. In the past, we just dequeued the SCB that was in flight from the list, but this could result in a lost completion should the host perform certain types of error recovery that must cancel all in-flight SCB DMA operations. Switch from using a 16bit completion entry, holding just the tag and the completion valid bit, to a 64bit completion entry that also contains a "status packet valid" indicator. This solves two problems: o The SCB DMA engine on at least Rev B. silicon does not properly deal with a PCI disconnect that occurs at a non-64bit aligned offset in the chips "source buffer". When the transfer is resumed, the DMA engine continues at the correct offset, but may wrap to the head of the buffer causing duplicate completions to be reported to the host. By using a completion buffer in host memory that is 64bit aligned and using 64bit completion entries, such disconnects should only occur at aligned addresses. This assumes that the host bridge will only disconnect on cache-line boundaries and that cache-lines are multpiles of 64bits. o By embedding the status information in the completion entry we can avoid an extra memory reference to the HSCB for commands that complete without error. Use the comparison of a "host freeze count" and a "sequencer freeze count" to allow the host to process most SCBs that complete with non-zero status without having to clear critical sections. Instead the host can just pause the sequencer, performs any necessary cleanup in the waiting for selection list, increments its freeze count on the controller, and unpauses. This is only possible because the sequencer defers completions of SCBs with bad status until after all pending selections have completed. The sequencer then avoids referencing any data structures the host may touch during completion of the SCB until the freeze counts match. aic79xx.c: Change the strategy for allocating our sentinal HSCB for the QINFIFO. In the past, this allocation was tacked onto the QOUTFIFO allocation. Now that the qoutfifo has grown to accomodate larger completion entries, the old approach will result in a 64byte allocation that costs an extra page of coherent memory. We now do this extra allocation via ahd_alloc_scbs() where the "unused space" can be used to allocate "normal" HSCBs. In our packetized busfree handler, use the ENSELO bit to differentiate between packetized and non-packetized unexpected busfree events that occur just after selection, but before the sequencer has had the oportunity to service the selection. When cleaning out the waiting for selection list, use the SCSI mode instead of the command channel mode. The SCB pointer in the command channel mode may be referenced by the SCB dma engine even while the sequencer is paused, whereas the SCSI mode SCB pointer is only accessed by the sequencer. Print the "complete on qfreeze" sequencer SCB completion list in ahd_dump_card_state(). This list holds all SCB completions that are deferred until a pending select-out qfreeze event has taken effect. aic79xx.h: Add definitions and structures to handle the new SCB completion scheme. Add a controller flag that indicates if the controller is in HostRAID mode. aic79xx.reg: Remove macros used for toggling from one data fifo mode to the other. They have not been in use for some time. Add scratch ram fields for our new qfreeze count scheme, converting the complete dma list into an "stailq", and providing for the "complete on qfreeze" SCB completion list. Some other fields were moved to retain proper field alignment (alignment >= field size in bytes). aic79xx.seq: Add code to our idle loop to: o Process deferred completions once a qfreeze event has taken full effect. o Thaw the queue once the sequencer and host qfreeze counts match. Generate 64bit completion entries passing the SCB_SGPTR field as the "good status" indicator. The first bit in this field is only set if we have a valid status packet to send to the host. Convert the COMPLETE_DMA_SCB list to an "stailq". When using "setjmp" to register an idle loop handler, do not combine the "ret" with the block move to pop the stack address in the same instruction. At least on the A, this results in a return to the setjmp caller, not to the new address at the top of the stack. Since we want the latter (we want the newly registered handler to only be invoked from the idle loop), we must use a separate ret instruction. Add a few missing critical sections. Close a race condition that can occur on Rev A. silicon. If both FIFOs happen to be allocated before the sequencer has a chance to service the FIFO that was allocated first, we must take special care to service the FIFO that is not active on the SCSI bus first. This guarantees that a FIFO will be freed to handle any snapshot requests for the FIFO that is still on the bus. Chosing the incorrect FIFO will result in deadlock. Update comments. aic79xx_inline.h Correct the offset calculation for the syncing of our qoutfifo. Update ahd_check_cmdcmpltqueues() for the larger completion entries. aic79xx_pci.c: Attach to HostRAID controllers by default. In the future I may add a sysctl to modify the behavior, but since FreeBSD does not have any HostRAID drivers, failing to attach just results in more email and bug reports for the author. MFC After: 1week
2004-02-04 16:38:38 +00:00
#define ID_9005_GENERIC_IROC_MASK 0xFF70FFFF00000000ull
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
#define ID_AIC7901 0x800F9005FFFF9005ull
Identify new controllers and the aic7901A. Move interrupt enable to the OSM. Remove some debugging messages. Remove chip bug workarounds for non-production asics.
2002-08-31 06:52:27 +00:00
#define ID_AHA_29320A 0x8000900500609005ull
Add 7901B support. Sort IDs based on chip type. Remove IROC IDs. We'll switch to using the IROC masks if/when we want to start attaching to IROC controllers. Approved by: RE
2003-05-26 21:15:52 +00:00
#define ID_AHA_29320ALP 0x8017900500449005ull
#define ID_AIC7901A 0x801E9005FFFF9005ull
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
#define ID_AHA_29320LP 0x8014900500449005ull
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
#define ID_AIC7902 0x801F9005FFFF9005ull
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
#define ID_AIC7902_B 0x801D9005FFFF9005ull
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
#define ID_AHA_39320 0x8010900500409005ull
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
#define ID_AHA_29320 0x8012900500429005ull
#define ID_AHA_29320B 0x8013900500439005ull
Add 7901B support. Sort IDs based on chip type. Remove IROC IDs. We'll switch to using the IROC masks if/when we want to start attaching to IROC controllers. Approved by: RE
2003-05-26 21:15:52 +00:00
#define ID_AHA_39320_B 0x8015900500409005ull
aic79xx.c: Allow 500us between pauses in ahd_pause_and_flushwork(). The maximum we will wait is now 500ms. In the same routine, remove any attempt to clear ENSELO. Let the firmware do it once the current selection has completed. This avoids some race conditions having to do with non-packetized completions and the auto-clearing of ENSELO on packetized completions. Also avoid attempts to clear critical sections when interrups are pending. We are going to loop again anyway, so clearing critical sections is a waste of time. It also may not be possible to clear a critical section if the source of the interrupt was a SEQINT. aic79xx_pci.c: Use the Generic 9005 mask when looking for generic 7901B parts. This allows the driver to attach to 7901B parts on motherboards using a non-Adaptec subvendor ID. aic79xx_inline.h: Test for the SCBRAM_RD_BUG against the bugs field, not the flags field in the softc. aic79xx.c: Cancel pending transactions on devices that respond with a selection timeout. This decreases the duration of timeout recovery when a device disappears. aic79xx.c: Don't bother forcing renegotiation on a selection timeout now that we use the device reset handler to abort any pending commands on the target. The device reset handler already takes us down to async narrow and forces a renegotiation. In the device reset handlers, only send a BDR sent async event if the status is not CAM_SEL_TIMEOUT. This avoids sending this event in the selection timeout case aic79xx.c: Modify the Core timeout handler to verify that another command has the potential to timeout before passing off a command timeout as due to some other command. This safety measure is added in response to a timeout recovery failure on H2B where it appears that incoming reselection status was lost during a drive pull test. In that case, the recovery handler continued to wait for the command that was active on the bus indefinetly. While the root cause of the above issue is still being determined seems a prudent safeguard. aic79xx_pci.c: Add a specific probe entry for the Dell OEM 39320(B). aic79xx.c: aic79xx.h: aic79xx.reg: aic79xx.seq: Modify the aic79xx firmware to never cross a cacheline or ADB boundary when DMA'ing completion entries to the host. In PCI mode, at least in 32/33 configurations, the SCB DMA engine may lose its place in the data-stream should the target force a retry on something other than an 8byte aligned boundary. In PCI-X mode, we do this to avoid split transactions since many chipsets seem to be unable to format proper split completions to continue the data transfer. The above change allows us to drop our completion entries from 8 bytes to 4. We were using 8 byte entries to ensure that PCI retries could only occur on an 8byte aligned boundary. Now that the sequencer guarantees this by splitting up completions, we can safely drop the size to 4 bytes (2 byte tag, one byte SG_RESID, one byte pad). Both the split-completion and PCI retry problems only show up under high tag load when interrupt coalescing is being especially effective. The switch from a 2byte completion entry to an 8 byte entry to solve the PCI problem increased the chance of incurring a split in PCI-X mode when multiple transactions were completed at once. Dropping the completion size to 4 bytes also means that we can complete more commands in a single DMA (128byte FIFO -> 32 commands instead of 16). aic79xx.c: Modify the SCSIINT handler to defer clearing sequencer critical sections to the individual interrupt handlers. This allows us to immediately disable any outgoing selections in the case of an unexpected busfree so we don't inadvertantly clear ENSELO *after* a new selection has started. Doing so may cause the sequencer to miss a successful selection. In ahd_update_pending_scbs(), only clear ENSELO if the bus is currently busy and a selection is not already in progress or the sequencer has yet to handle a pending selection. While we want to ensure that the selection for the SCB at the head of the selection queue is restarted so that any change in negotiation request can take effect, we can't clobber pending selection state without confusing the sequencer into missing a selection.
2004-05-11 20:46:05 +00:00
#define ID_AHA_39320_B_DELL 0x8015900501681028ull
aic79xx.c: Clear the LQICRC_NLQ status should it pop up after we have already handled the SCSIPERR. During some streaming operations this status can be delayed until the stream ends. Without this change, the driver would complain about a "Missing case in ahd_handle_scsiint". In the LQOBUSFREE handler... Don't return the LQOMGR back to the idle state until after we have cleaned up ENSELO and any status related to this selection. The last thing we need is the LQO manager starting another select-out before we have updated the execution queue. It is not clear whether the LQOMGR would, or would not start a new selection early. Make sure ENSELO is off prior to clearing SELDO by flushing device writes. Move assignment of the next target SCB pointer inside of an if to make the code clearer. The effect is the same. Dump card state in both "Unexpected PKT busfree" paths. In ahd_reset(), set the chip to SCSI mode before reading SXFRCTL1. That register only exists in the SCSI mode. Also set the mode explicitly to the SCSI mode after chip reset due to paranoia. Re-arrange code so that SXFRCTL1 is restored as quickly after the chip reset as possible. S/G structurs must be 8byte aligned. Make this official by saying so in our DMA tag. Disable CIO bus stretch on MDFFSTAT if SHVALID is about to come true. This can cause a CIO bus lockup if a PCI or PCI-X error occurs while the stretch is occurring - the host cannot service the PCI-X error since the CIO bus is locked out and SHVALID will never resolve. The stretch was added in the Rev B to simplify the wait for SHVALID to resolve, but the code to do this in the open source sequencer is so simple it was never removed. Consistently use MAX_OFFSET for the user max syncrate set from non-volatile storage. This ensures that the offset does not conflict with AH?_OFFSET_UNKNOWN. Have ahd_pause_and_flushwork set the mode to ensure that it has access to the registers it checks. Also modify the checking of intstat so that the check against 0xFF can actually succeed if the INT_PEND mask is something other than 0xFF. Although there are no cardbus U320 controllers, this check may be needed to recover from a hot-plug PCI removal that occurs without informing the driver. Fix a typo. sg_prefetch_cnt -> sg_prefetch_align. This fixes an infinite loop at card initialization if the cacheline size is 0. aic79xx.h: Add AHD_EARLY_REQ_BUG bug flag. Fix spelling errors. Include the CDB's length just after the CDB pointer in the DMA'ed CDB case. Change AH?_OFFSET_UNKNOWN to 0xFF. This is a value that the curr->offset can never be, unlike '0' which we previously used. This fixes code that only checks for a non-zero offset to determine if a sync negotiation is required since it will fire in the unknown case even if the goal is async. aic79xx.reg: Add comments for LQISTAT bits indicating their names in the 7902 data book. We use slightly different and more descriptive names in the firmware. Fix spelling errors. Include the CDB's length just after the CDB pointer in the DMA'ed CDB case. aic79xx.seq: Update comments regarding rundown of the GSFIFO to reflect reality. Fix spelling errors. Since we use an 8byte address and 1 byte length, shorten the size of a block move for the legacy DMA'ed CDB case from 11 to 9 bytes. Remove code that, assuming the abort pending feature worked, would set MK_MESSAGE in the SCB's control byte on completion to catch invalid reselections. Since we don't see interrupts for completed selections, this status update could occur prior to us noticing the SELDO. The "select-out" queue logic will get confused by the MK_MESSAGE bit being set as this is used to catch packatized connections where we select-out with ATN. Since the abort pending feature doesn't work on any released controllers yet, this code was never executed. Add support for the AHD_EARLY_REQ_BUG. Don't ignore persistent REQ assertions just because they were asserted within the bus settle delay window. This allows us to tolerate devices like the GEM318 that violate the SCSI spec. Remove unintentional settnig of SG_CACHE_AVAIL. Writing this bit should have no effect, but who knows... On the Rev A, we must wait for HDMAENACK before loading additional segments to avoid clobbering the address of the first segment in the S/G FIFO. This resolves data-corruption issues with certain IBM (now Hitachi) and Fujitsu U320 drives. Rearrange calc_residual to avoid an extra jmp instruction. On RevA Silicon, if the target returns us to data-out after we have already trained for data-out, it is possible for us to transition the free running clock to data-valid before the required 100ns P1 setup time (8 P1 assertions in fast-160 mode). This will only happen if this L-Q is a continuation of a data transfer for which we have already prefetched data into our FIFO (LQ/Data followed by LQ/Data for the same write transaction). This can cause some target implementations to miss the first few data transfers on the bus. We detect this situation by noticing that this is the first data transfer after an LQ (LQIWORKONLQ true), that the data transfer is a continuation of a transfer already setup in our FIFO (SAVEPTRS interrupt), and that the transaction is a write (DIRECTION set in DFCNTRL). The delay is performed by disabling SCSIEN until we see the first REQ from the target. Only compile in snapshot savepointers handler for RevA silicon where it is enabled. Handle the cfg4icmd packetized interrupt. We just need to load the address and count, start the DMA, and CLRCHN once the transfer is complete. Fix an oversight in the overrun handler for packetized status operations. We need to wait for either CTXTDONE or an overrun when checking for an overrun. The previous code did not wait and thus could decide that no overrun had occurred even though an overrun will occur on the next data-valid req. Add some comment to this section for clarity. Use LAST_SEG_DONE instead of LASTSDONE for testing transfer completion in the packetized status case. LASTSDONE may come up more quickly since it only records completion on the SCSI side, but since LAST_SEG_DONE is used everywhere else (and needs to be), this is less confusing. Add a missing invalidation of the longjmp address in the non-pack handler. This code needs additional review. aic79xx_inline.h: Fix spelling error. aic79xx_osm.c: Set the cdb length for CDBs dma'ed from host memory. Add a comment indicating that, should CAM start supporting cdbs larger than 16bytes, the driver could store the CDB in the status buffer. aic79xx_pci.c: Add a table entry for the 39320A. Added a missing comma to an error string table. Fix spelling errors.
2003-02-27 23:23:16 +00:00
#define ID_AHA_39320A 0x8016900500409005ull
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
#define ID_AHA_39320D 0x8011900500419005ull
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
#define ID_AHA_39320D_B 0x801C900500419005ull
#define ID_AHA_39320D_HP 0x8011900500AC0E11ull
#define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
#define ID_AIC7902_PCI_REV_A4 0x3
Identify new controllers and the aic7901A. Move interrupt enable to the OSM. Remove some debugging messages. Remove chip bug workarounds for non-production asics.
2002-08-31 06:52:27 +00:00
#define ID_AIC7902_PCI_REV_B0 0x10
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
#define SUBID_HP 0x0E11
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
aic79xx.c: aic79xx.seq: Convert the COMPLETE_DMA_SCB list to an "stailq". This allows us to safely keep the SCB that is currently being DMA'ed back the host on the head of the list while processing completions off of the bus. The newly completed SCBs are appended to the tail of the queue. In the past, we just dequeued the SCB that was in flight from the list, but this could result in a lost completion should the host perform certain types of error recovery that must cancel all in-flight SCB DMA operations. Switch from using a 16bit completion entry, holding just the tag and the completion valid bit, to a 64bit completion entry that also contains a "status packet valid" indicator. This solves two problems: o The SCB DMA engine on at least Rev B. silicon does not properly deal with a PCI disconnect that occurs at a non-64bit aligned offset in the chips "source buffer". When the transfer is resumed, the DMA engine continues at the correct offset, but may wrap to the head of the buffer causing duplicate completions to be reported to the host. By using a completion buffer in host memory that is 64bit aligned and using 64bit completion entries, such disconnects should only occur at aligned addresses. This assumes that the host bridge will only disconnect on cache-line boundaries and that cache-lines are multpiles of 64bits. o By embedding the status information in the completion entry we can avoid an extra memory reference to the HSCB for commands that complete without error. Use the comparison of a "host freeze count" and a "sequencer freeze count" to allow the host to process most SCBs that complete with non-zero status without having to clear critical sections. Instead the host can just pause the sequencer, performs any necessary cleanup in the waiting for selection list, increments its freeze count on the controller, and unpauses. This is only possible because the sequencer defers completions of SCBs with bad status until after all pending selections have completed. The sequencer then avoids referencing any data structures the host may touch during completion of the SCB until the freeze counts match. aic79xx.c: Change the strategy for allocating our sentinal HSCB for the QINFIFO. In the past, this allocation was tacked onto the QOUTFIFO allocation. Now that the qoutfifo has grown to accomodate larger completion entries, the old approach will result in a 64byte allocation that costs an extra page of coherent memory. We now do this extra allocation via ahd_alloc_scbs() where the "unused space" can be used to allocate "normal" HSCBs. In our packetized busfree handler, use the ENSELO bit to differentiate between packetized and non-packetized unexpected busfree events that occur just after selection, but before the sequencer has had the oportunity to service the selection. When cleaning out the waiting for selection list, use the SCSI mode instead of the command channel mode. The SCB pointer in the command channel mode may be referenced by the SCB dma engine even while the sequencer is paused, whereas the SCSI mode SCB pointer is only accessed by the sequencer. Print the "complete on qfreeze" sequencer SCB completion list in ahd_dump_card_state(). This list holds all SCB completions that are deferred until a pending select-out qfreeze event has taken effect. aic79xx.h: Add definitions and structures to handle the new SCB completion scheme. Add a controller flag that indicates if the controller is in HostRAID mode. aic79xx.reg: Remove macros used for toggling from one data fifo mode to the other. They have not been in use for some time. Add scratch ram fields for our new qfreeze count scheme, converting the complete dma list into an "stailq", and providing for the "complete on qfreeze" SCB completion list. Some other fields were moved to retain proper field alignment (alignment >= field size in bytes). aic79xx.seq: Add code to our idle loop to: o Process deferred completions once a qfreeze event has taken full effect. o Thaw the queue once the sequencer and host qfreeze counts match. Generate 64bit completion entries passing the SCB_SGPTR field as the "good status" indicator. The first bit in this field is only set if we have a valid status packet to send to the host. Convert the COMPLETE_DMA_SCB list to an "stailq". When using "setjmp" to register an idle loop handler, do not combine the "ret" with the block move to pop the stack address in the same instruction. At least on the A, this results in a return to the setjmp caller, not to the new address at the top of the stack. Since we want the latter (we want the newly registered handler to only be invoked from the idle loop), we must use a separate ret instruction. Add a few missing critical sections. Close a race condition that can occur on Rev A. silicon. If both FIFOs happen to be allocated before the sequencer has a chance to service the FIFO that was allocated first, we must take special care to service the FIFO that is not active on the SCSI bus first. This guarantees that a FIFO will be freed to handle any snapshot requests for the FIFO that is still on the bus. Chosing the incorrect FIFO will result in deadlock. Update comments. aic79xx_inline.h Correct the offset calculation for the syncing of our qoutfifo. Update ahd_check_cmdcmpltqueues() for the larger completion entries. aic79xx_pci.c: Attach to HostRAID controllers by default. In the future I may add a sysctl to modify the behavior, but since FreeBSD does not have any HostRAID drivers, failing to attach just results in more email and bug reports for the author. MFC After: 1week
2004-02-04 16:38:38 +00:00
#define DEVID_9005_HOSTRAID(id) ((id) & 0x80)
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
#define DEVID_9005_TYPE(id) ((id) & 0xF)
#define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
#define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */
#define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
#define DEVID_9005_MFUNC(id) ((id) & 0x10)
#define DEVID_9005_PACKETIZED(id) ((id) & 0x8000)
#define SUBID_9005_TYPE(id) ((id) & 0xF)
#define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */
#define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
#define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0)
#define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20)
#define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6)
#define SUBID_9005_SEEPTYPE_NONE 0x0
#define SUBID_9005_SEEPTYPE_4K 0x1
Add 7901B support. Sort IDs based on chip type. Remove IROC IDs. We'll switch to using the IROC masks if/when we want to start attaching to IROC controllers. Approved by: RE
2003-05-26 21:15:52 +00:00
static ahd_device_setup_t ahd_aic7901_setup;
Identify new controllers and the aic7901A. Move interrupt enable to the OSM. Remove some debugging messages. Remove chip bug workarounds for non-production asics.
2002-08-31 06:52:27 +00:00
static ahd_device_setup_t ahd_aic7901A_setup;
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
static ahd_device_setup_t ahd_aic7902_setup;
aic79xx.h: Add a 7901A specific feature definition. aic79xx_pci.c: Split out the general aic790X setup into it's own setup handler that works on single and dual controllers. Adjust all other PCI setup handlers to initialize the chips basic features and type before calling the generic handler. Turn off a few Rev B workarounds that are not required on the 7901B.
2003-06-28 04:39:49 +00:00
static ahd_device_setup_t ahd_aic790X_setup;
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
struct ahd_pci_identity ahd_pci_ident_table [] =
{
Add 7901B support. Sort IDs based on chip type. Remove IROC IDs. We'll switch to using the IROC masks if/when we want to start attaching to IROC controllers. Approved by: RE
2003-05-26 21:15:52 +00:00
/* aic7901 based controllers */
{
ID_AHA_29320A,
ID_ALL_MASK,
"Adaptec 29320A Ultra320 SCSI adapter",
ahd_aic7901_setup
},
{
ID_AHA_29320ALP,
ID_ALL_MASK,
"Adaptec 29320ALP Ultra320 SCSI adapter",
ahd_aic7901_setup
},
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
/* aic7901A based controllers */
{
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
ID_AHA_29320LP,
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
ID_ALL_MASK,
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
"Adaptec 29320LP Ultra320 SCSI adapter",
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
ahd_aic7901A_setup
},
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
/* aic7902 based controllers */
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
{
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
ID_AHA_29320,
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
ID_ALL_MASK,
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
"Adaptec 29320 Ultra320 SCSI adapter",
ahd_aic7902_setup
Add 7901B support. Sort IDs based on chip type. Remove IROC IDs. We'll switch to using the IROC masks if/when we want to start attaching to IROC controllers. Approved by: RE
2003-05-26 21:15:52 +00:00
},
{
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
ID_AHA_29320B,
Add 7901B support. Sort IDs based on chip type. Remove IROC IDs. We'll switch to using the IROC masks if/when we want to start attaching to IROC controllers. Approved by: RE
2003-05-26 21:15:52 +00:00
ID_ALL_MASK,
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
"Adaptec 29320B Ultra320 SCSI adapter",
ahd_aic7902_setup
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
},
{
ID_AHA_39320,
ID_ALL_MASK,
"Adaptec 39320 Ultra320 SCSI adapter",
ahd_aic7902_setup
},
Add 7901B support. Sort IDs based on chip type. Remove IROC IDs. We'll switch to using the IROC masks if/when we want to start attaching to IROC controllers. Approved by: RE
2003-05-26 21:15:52 +00:00
{
ID_AHA_39320_B,
ID_ALL_MASK,
"Adaptec 39320 Ultra320 SCSI adapter",
ahd_aic7902_setup
},
aic79xx.c: Allow 500us between pauses in ahd_pause_and_flushwork(). The maximum we will wait is now 500ms. In the same routine, remove any attempt to clear ENSELO. Let the firmware do it once the current selection has completed. This avoids some race conditions having to do with non-packetized completions and the auto-clearing of ENSELO on packetized completions. Also avoid attempts to clear critical sections when interrups are pending. We are going to loop again anyway, so clearing critical sections is a waste of time. It also may not be possible to clear a critical section if the source of the interrupt was a SEQINT. aic79xx_pci.c: Use the Generic 9005 mask when looking for generic 7901B parts. This allows the driver to attach to 7901B parts on motherboards using a non-Adaptec subvendor ID. aic79xx_inline.h: Test for the SCBRAM_RD_BUG against the bugs field, not the flags field in the softc. aic79xx.c: Cancel pending transactions on devices that respond with a selection timeout. This decreases the duration of timeout recovery when a device disappears. aic79xx.c: Don't bother forcing renegotiation on a selection timeout now that we use the device reset handler to abort any pending commands on the target. The device reset handler already takes us down to async narrow and forces a renegotiation. In the device reset handlers, only send a BDR sent async event if the status is not CAM_SEL_TIMEOUT. This avoids sending this event in the selection timeout case aic79xx.c: Modify the Core timeout handler to verify that another command has the potential to timeout before passing off a command timeout as due to some other command. This safety measure is added in response to a timeout recovery failure on H2B where it appears that incoming reselection status was lost during a drive pull test. In that case, the recovery handler continued to wait for the command that was active on the bus indefinetly. While the root cause of the above issue is still being determined seems a prudent safeguard. aic79xx_pci.c: Add a specific probe entry for the Dell OEM 39320(B). aic79xx.c: aic79xx.h: aic79xx.reg: aic79xx.seq: Modify the aic79xx firmware to never cross a cacheline or ADB boundary when DMA'ing completion entries to the host. In PCI mode, at least in 32/33 configurations, the SCB DMA engine may lose its place in the data-stream should the target force a retry on something other than an 8byte aligned boundary. In PCI-X mode, we do this to avoid split transactions since many chipsets seem to be unable to format proper split completions to continue the data transfer. The above change allows us to drop our completion entries from 8 bytes to 4. We were using 8 byte entries to ensure that PCI retries could only occur on an 8byte aligned boundary. Now that the sequencer guarantees this by splitting up completions, we can safely drop the size to 4 bytes (2 byte tag, one byte SG_RESID, one byte pad). Both the split-completion and PCI retry problems only show up under high tag load when interrupt coalescing is being especially effective. The switch from a 2byte completion entry to an 8 byte entry to solve the PCI problem increased the chance of incurring a split in PCI-X mode when multiple transactions were completed at once. Dropping the completion size to 4 bytes also means that we can complete more commands in a single DMA (128byte FIFO -> 32 commands instead of 16). aic79xx.c: Modify the SCSIINT handler to defer clearing sequencer critical sections to the individual interrupt handlers. This allows us to immediately disable any outgoing selections in the case of an unexpected busfree so we don't inadvertantly clear ENSELO *after* a new selection has started. Doing so may cause the sequencer to miss a successful selection. In ahd_update_pending_scbs(), only clear ENSELO if the bus is currently busy and a selection is not already in progress or the sequencer has yet to handle a pending selection. While we want to ensure that the selection for the SCB at the head of the selection queue is restarted so that any change in negotiation request can take effect, we can't clobber pending selection state without confusing the sequencer into missing a selection.
2004-05-11 20:46:05 +00:00
{
ID_AHA_39320_B_DELL,
ID_ALL_MASK,
"Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter",
ahd_aic7902_setup
},
aic79xx.c: Clear the LQICRC_NLQ status should it pop up after we have already handled the SCSIPERR. During some streaming operations this status can be delayed until the stream ends. Without this change, the driver would complain about a "Missing case in ahd_handle_scsiint". In the LQOBUSFREE handler... Don't return the LQOMGR back to the idle state until after we have cleaned up ENSELO and any status related to this selection. The last thing we need is the LQO manager starting another select-out before we have updated the execution queue. It is not clear whether the LQOMGR would, or would not start a new selection early. Make sure ENSELO is off prior to clearing SELDO by flushing device writes. Move assignment of the next target SCB pointer inside of an if to make the code clearer. The effect is the same. Dump card state in both "Unexpected PKT busfree" paths. In ahd_reset(), set the chip to SCSI mode before reading SXFRCTL1. That register only exists in the SCSI mode. Also set the mode explicitly to the SCSI mode after chip reset due to paranoia. Re-arrange code so that SXFRCTL1 is restored as quickly after the chip reset as possible. S/G structurs must be 8byte aligned. Make this official by saying so in our DMA tag. Disable CIO bus stretch on MDFFSTAT if SHVALID is about to come true. This can cause a CIO bus lockup if a PCI or PCI-X error occurs while the stretch is occurring - the host cannot service the PCI-X error since the CIO bus is locked out and SHVALID will never resolve. The stretch was added in the Rev B to simplify the wait for SHVALID to resolve, but the code to do this in the open source sequencer is so simple it was never removed. Consistently use MAX_OFFSET for the user max syncrate set from non-volatile storage. This ensures that the offset does not conflict with AH?_OFFSET_UNKNOWN. Have ahd_pause_and_flushwork set the mode to ensure that it has access to the registers it checks. Also modify the checking of intstat so that the check against 0xFF can actually succeed if the INT_PEND mask is something other than 0xFF. Although there are no cardbus U320 controllers, this check may be needed to recover from a hot-plug PCI removal that occurs without informing the driver. Fix a typo. sg_prefetch_cnt -> sg_prefetch_align. This fixes an infinite loop at card initialization if the cacheline size is 0. aic79xx.h: Add AHD_EARLY_REQ_BUG bug flag. Fix spelling errors. Include the CDB's length just after the CDB pointer in the DMA'ed CDB case. Change AH?_OFFSET_UNKNOWN to 0xFF. This is a value that the curr->offset can never be, unlike '0' which we previously used. This fixes code that only checks for a non-zero offset to determine if a sync negotiation is required since it will fire in the unknown case even if the goal is async. aic79xx.reg: Add comments for LQISTAT bits indicating their names in the 7902 data book. We use slightly different and more descriptive names in the firmware. Fix spelling errors. Include the CDB's length just after the CDB pointer in the DMA'ed CDB case. aic79xx.seq: Update comments regarding rundown of the GSFIFO to reflect reality. Fix spelling errors. Since we use an 8byte address and 1 byte length, shorten the size of a block move for the legacy DMA'ed CDB case from 11 to 9 bytes. Remove code that, assuming the abort pending feature worked, would set MK_MESSAGE in the SCB's control byte on completion to catch invalid reselections. Since we don't see interrupts for completed selections, this status update could occur prior to us noticing the SELDO. The "select-out" queue logic will get confused by the MK_MESSAGE bit being set as this is used to catch packatized connections where we select-out with ATN. Since the abort pending feature doesn't work on any released controllers yet, this code was never executed. Add support for the AHD_EARLY_REQ_BUG. Don't ignore persistent REQ assertions just because they were asserted within the bus settle delay window. This allows us to tolerate devices like the GEM318 that violate the SCSI spec. Remove unintentional settnig of SG_CACHE_AVAIL. Writing this bit should have no effect, but who knows... On the Rev A, we must wait for HDMAENACK before loading additional segments to avoid clobbering the address of the first segment in the S/G FIFO. This resolves data-corruption issues with certain IBM (now Hitachi) and Fujitsu U320 drives. Rearrange calc_residual to avoid an extra jmp instruction. On RevA Silicon, if the target returns us to data-out after we have already trained for data-out, it is possible for us to transition the free running clock to data-valid before the required 100ns P1 setup time (8 P1 assertions in fast-160 mode). This will only happen if this L-Q is a continuation of a data transfer for which we have already prefetched data into our FIFO (LQ/Data followed by LQ/Data for the same write transaction). This can cause some target implementations to miss the first few data transfers on the bus. We detect this situation by noticing that this is the first data transfer after an LQ (LQIWORKONLQ true), that the data transfer is a continuation of a transfer already setup in our FIFO (SAVEPTRS interrupt), and that the transaction is a write (DIRECTION set in DFCNTRL). The delay is performed by disabling SCSIEN until we see the first REQ from the target. Only compile in snapshot savepointers handler for RevA silicon where it is enabled. Handle the cfg4icmd packetized interrupt. We just need to load the address and count, start the DMA, and CLRCHN once the transfer is complete. Fix an oversight in the overrun handler for packetized status operations. We need to wait for either CTXTDONE or an overrun when checking for an overrun. The previous code did not wait and thus could decide that no overrun had occurred even though an overrun will occur on the next data-valid req. Add some comment to this section for clarity. Use LAST_SEG_DONE instead of LASTSDONE for testing transfer completion in the packetized status case. LASTSDONE may come up more quickly since it only records completion on the SCSI side, but since LAST_SEG_DONE is used everywhere else (and needs to be), this is less confusing. Add a missing invalidation of the longjmp address in the non-pack handler. This code needs additional review. aic79xx_inline.h: Fix spelling error. aic79xx_osm.c: Set the cdb length for CDBs dma'ed from host memory. Add a comment indicating that, should CAM start supporting cdbs larger than 16bytes, the driver could store the CDB in the status buffer. aic79xx_pci.c: Add a table entry for the 39320A. Added a missing comma to an error string table. Fix spelling errors.
2003-02-27 23:23:16 +00:00
{
ID_AHA_39320A,
ID_ALL_MASK,
"Adaptec 39320A Ultra320 SCSI adapter",
ahd_aic7902_setup
},
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
{
ID_AHA_39320D,
ID_ALL_MASK,
"Adaptec 39320D Ultra320 SCSI adapter",
ahd_aic7902_setup
},
{
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
ID_AHA_39320D_HP,
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
ID_ALL_MASK,
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
"Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
ahd_aic7902_setup
},
Identify new controllers and the aic7901A. Move interrupt enable to the OSM. Remove some debugging messages. Remove chip bug workarounds for non-production asics.
2002-08-31 06:52:27 +00:00
{
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
ID_AHA_39320D_B,
Identify new controllers and the aic7901A. Move interrupt enable to the OSM. Remove some debugging messages. Remove chip bug workarounds for non-production asics.
2002-08-31 06:52:27 +00:00
ID_ALL_MASK,
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
"Adaptec 39320D Ultra320 SCSI adapter",
Identify new controllers and the aic7901A. Move interrupt enable to the OSM. Remove some debugging messages. Remove chip bug workarounds for non-production asics.
2002-08-31 06:52:27 +00:00
ahd_aic7902_setup
},
{
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
ID_AHA_39320D_B_HP,
Identify new controllers and the aic7901A. Move interrupt enable to the OSM. Remove some debugging messages. Remove chip bug workarounds for non-production asics.
2002-08-31 06:52:27 +00:00
ID_ALL_MASK,
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
"Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
Identify new controllers and the aic7901A. Move interrupt enable to the OSM. Remove some debugging messages. Remove chip bug workarounds for non-production asics.
2002-08-31 06:52:27 +00:00
ahd_aic7902_setup
},
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
/* Generic chip probes for devices we don't know 'exactly' */
Add 7901B support. Sort IDs based on chip type. Remove IROC IDs. We'll switch to using the IROC masks if/when we want to start attaching to IROC controllers. Approved by: RE
2003-05-26 21:15:52 +00:00
{
aic79xx.c: aic79xx.seq: Convert the COMPLETE_DMA_SCB list to an "stailq". This allows us to safely keep the SCB that is currently being DMA'ed back the host on the head of the list while processing completions off of the bus. The newly completed SCBs are appended to the tail of the queue. In the past, we just dequeued the SCB that was in flight from the list, but this could result in a lost completion should the host perform certain types of error recovery that must cancel all in-flight SCB DMA operations. Switch from using a 16bit completion entry, holding just the tag and the completion valid bit, to a 64bit completion entry that also contains a "status packet valid" indicator. This solves two problems: o The SCB DMA engine on at least Rev B. silicon does not properly deal with a PCI disconnect that occurs at a non-64bit aligned offset in the chips "source buffer". When the transfer is resumed, the DMA engine continues at the correct offset, but may wrap to the head of the buffer causing duplicate completions to be reported to the host. By using a completion buffer in host memory that is 64bit aligned and using 64bit completion entries, such disconnects should only occur at aligned addresses. This assumes that the host bridge will only disconnect on cache-line boundaries and that cache-lines are multpiles of 64bits. o By embedding the status information in the completion entry we can avoid an extra memory reference to the HSCB for commands that complete without error. Use the comparison of a "host freeze count" and a "sequencer freeze count" to allow the host to process most SCBs that complete with non-zero status without having to clear critical sections. Instead the host can just pause the sequencer, performs any necessary cleanup in the waiting for selection list, increments its freeze count on the controller, and unpauses. This is only possible because the sequencer defers completions of SCBs with bad status until after all pending selections have completed. The sequencer then avoids referencing any data structures the host may touch during completion of the SCB until the freeze counts match. aic79xx.c: Change the strategy for allocating our sentinal HSCB for the QINFIFO. In the past, this allocation was tacked onto the QOUTFIFO allocation. Now that the qoutfifo has grown to accomodate larger completion entries, the old approach will result in a 64byte allocation that costs an extra page of coherent memory. We now do this extra allocation via ahd_alloc_scbs() where the "unused space" can be used to allocate "normal" HSCBs. In our packetized busfree handler, use the ENSELO bit to differentiate between packetized and non-packetized unexpected busfree events that occur just after selection, but before the sequencer has had the oportunity to service the selection. When cleaning out the waiting for selection list, use the SCSI mode instead of the command channel mode. The SCB pointer in the command channel mode may be referenced by the SCB dma engine even while the sequencer is paused, whereas the SCSI mode SCB pointer is only accessed by the sequencer. Print the "complete on qfreeze" sequencer SCB completion list in ahd_dump_card_state(). This list holds all SCB completions that are deferred until a pending select-out qfreeze event has taken effect. aic79xx.h: Add definitions and structures to handle the new SCB completion scheme. Add a controller flag that indicates if the controller is in HostRAID mode. aic79xx.reg: Remove macros used for toggling from one data fifo mode to the other. They have not been in use for some time. Add scratch ram fields for our new qfreeze count scheme, converting the complete dma list into an "stailq", and providing for the "complete on qfreeze" SCB completion list. Some other fields were moved to retain proper field alignment (alignment >= field size in bytes). aic79xx.seq: Add code to our idle loop to: o Process deferred completions once a qfreeze event has taken full effect. o Thaw the queue once the sequencer and host qfreeze counts match. Generate 64bit completion entries passing the SCB_SGPTR field as the "good status" indicator. The first bit in this field is only set if we have a valid status packet to send to the host. Convert the COMPLETE_DMA_SCB list to an "stailq". When using "setjmp" to register an idle loop handler, do not combine the "ret" with the block move to pop the stack address in the same instruction. At least on the A, this results in a return to the setjmp caller, not to the new address at the top of the stack. Since we want the latter (we want the newly registered handler to only be invoked from the idle loop), we must use a separate ret instruction. Add a few missing critical sections. Close a race condition that can occur on Rev A. silicon. If both FIFOs happen to be allocated before the sequencer has a chance to service the FIFO that was allocated first, we must take special care to service the FIFO that is not active on the SCSI bus first. This guarantees that a FIFO will be freed to handle any snapshot requests for the FIFO that is still on the bus. Chosing the incorrect FIFO will result in deadlock. Update comments. aic79xx_inline.h Correct the offset calculation for the syncing of our qoutfifo. Update ahd_check_cmdcmpltqueues() for the larger completion entries. aic79xx_pci.c: Attach to HostRAID controllers by default. In the future I may add a sysctl to modify the behavior, but since FreeBSD does not have any HostRAID drivers, failing to attach just results in more email and bug reports for the author. MFC After: 1week
2004-02-04 16:38:38 +00:00
ID_AIC7901 & ID_9005_GENERIC_MASK,
aic79xx.c: Allow 500us between pauses in ahd_pause_and_flushwork(). The maximum we will wait is now 500ms. In the same routine, remove any attempt to clear ENSELO. Let the firmware do it once the current selection has completed. This avoids some race conditions having to do with non-packetized completions and the auto-clearing of ENSELO on packetized completions. Also avoid attempts to clear critical sections when interrups are pending. We are going to loop again anyway, so clearing critical sections is a waste of time. It also may not be possible to clear a critical section if the source of the interrupt was a SEQINT. aic79xx_pci.c: Use the Generic 9005 mask when looking for generic 7901B parts. This allows the driver to attach to 7901B parts on motherboards using a non-Adaptec subvendor ID. aic79xx_inline.h: Test for the SCBRAM_RD_BUG against the bugs field, not the flags field in the softc. aic79xx.c: Cancel pending transactions on devices that respond with a selection timeout. This decreases the duration of timeout recovery when a device disappears. aic79xx.c: Don't bother forcing renegotiation on a selection timeout now that we use the device reset handler to abort any pending commands on the target. The device reset handler already takes us down to async narrow and forces a renegotiation. In the device reset handlers, only send a BDR sent async event if the status is not CAM_SEL_TIMEOUT. This avoids sending this event in the selection timeout case aic79xx.c: Modify the Core timeout handler to verify that another command has the potential to timeout before passing off a command timeout as due to some other command. This safety measure is added in response to a timeout recovery failure on H2B where it appears that incoming reselection status was lost during a drive pull test. In that case, the recovery handler continued to wait for the command that was active on the bus indefinetly. While the root cause of the above issue is still being determined seems a prudent safeguard. aic79xx_pci.c: Add a specific probe entry for the Dell OEM 39320(B). aic79xx.c: aic79xx.h: aic79xx.reg: aic79xx.seq: Modify the aic79xx firmware to never cross a cacheline or ADB boundary when DMA'ing completion entries to the host. In PCI mode, at least in 32/33 configurations, the SCB DMA engine may lose its place in the data-stream should the target force a retry on something other than an 8byte aligned boundary. In PCI-X mode, we do this to avoid split transactions since many chipsets seem to be unable to format proper split completions to continue the data transfer. The above change allows us to drop our completion entries from 8 bytes to 4. We were using 8 byte entries to ensure that PCI retries could only occur on an 8byte aligned boundary. Now that the sequencer guarantees this by splitting up completions, we can safely drop the size to 4 bytes (2 byte tag, one byte SG_RESID, one byte pad). Both the split-completion and PCI retry problems only show up under high tag load when interrupt coalescing is being especially effective. The switch from a 2byte completion entry to an 8 byte entry to solve the PCI problem increased the chance of incurring a split in PCI-X mode when multiple transactions were completed at once. Dropping the completion size to 4 bytes also means that we can complete more commands in a single DMA (128byte FIFO -> 32 commands instead of 16). aic79xx.c: Modify the SCSIINT handler to defer clearing sequencer critical sections to the individual interrupt handlers. This allows us to immediately disable any outgoing selections in the case of an unexpected busfree so we don't inadvertantly clear ENSELO *after* a new selection has started. Doing so may cause the sequencer to miss a successful selection. In ahd_update_pending_scbs(), only clear ENSELO if the bus is currently busy and a selection is not already in progress or the sequencer has yet to handle a pending selection. While we want to ensure that the selection for the SCB at the head of the selection queue is restarted so that any change in negotiation request can take effect, we can't clobber pending selection state without confusing the sequencer into missing a selection.
2004-05-11 20:46:05 +00:00
ID_9005_GENERIC_MASK,
Add 7901B support. Sort IDs based on chip type. Remove IROC IDs. We'll switch to using the IROC masks if/when we want to start attaching to IROC controllers. Approved by: RE
2003-05-26 21:15:52 +00:00
"Adaptec AIC7901 Ultra320 SCSI adapter",
ahd_aic7901_setup
},
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
{
Last minute fixes to ahc and ahd: ahd_pci.c: Retrieve the allow_memio hint from the resource manager to determine whether or not to try PCI MEMIO. aic79xx_osm.h: aic7xxx_osm.h: Don't wrongly abuse the callout_reset() interface when trying to abuse timeouts generated from the CAM layer. This fixes the console freeze and lost timeout problem that many have reported, especially on SMP systems. aic79xx_pci.c aic7xxx_pci.c Rewrite the MEMIO test routine to prevent certain broken chipsets from trying to burst multiple DWORDs to the registers. Also make the routine better detect byte merging by the host bridge and deal with it. aic79xx.reg: Correct an incorrect register definition. Approved by: re (rwatson, jhb)
2002-12-04 22:51:29 +00:00
ID_AIC7901A & ID_DEV_VENDOR_MASK,
ID_DEV_VENDOR_MASK,
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
"Adaptec AIC7901A Ultra320 SCSI adapter",
ahd_aic7901A_setup
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
},
{
ID_AIC7902 & ID_9005_GENERIC_MASK,
ID_9005_GENERIC_MASK,
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
"Adaptec AIC7902 Ultra320 SCSI adapter",
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
ahd_aic7902_setup
}
};
const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table);
#define DEVCONFIG 0x40
#define PCIXINITPAT 0x0000E000ul
#define PCIXINIT_PCI33_66 0x0000E000ul
#define PCIXINIT_PCIX50_66 0x0000C000ul
#define PCIXINIT_PCIX66_100 0x0000A000ul
#define PCIXINIT_PCIX100_133 0x00008000ul
#define PCI_BUS_MODES_INDEX(devconfig) \
(((devconfig) & PCIXINITPAT) >> 13)
static const char *pci_bus_modes[] =
{
"PCI bus mode unknown",
"PCI bus mode unknown",
"PCI bus mode unknown",
"PCI bus mode unknown",
"PCI-X 101-133Mhz",
"PCI-X 67-100Mhz",
"PCI-X 50-66Mhz",
"PCI 33 or 66Mhz"
};
#define TESTMODE 0x00000800ul
#define IRDY_RST 0x00000200ul
#define FRAME_RST 0x00000100ul
#define PCI64BIT 0x00000080ul
#define MRDCEN 0x00000040ul
#define ENDIANSEL 0x00000020ul
#define MIXQWENDIANEN 0x00000008ul
#define DACEN 0x00000004ul
#define STPWLEVEL 0x00000002ul
#define QWENDIANSEL 0x00000001ul
#define DEVCONFIG1 0x44
#define PREQDIS 0x01
#define CSIZE_LATTIME 0x0c
#define CACHESIZE 0x000000fful
#define LATTIME 0x0000ff00ul
static int ahd_check_extport(struct ahd_softc *ahd);
static void ahd_configure_termination(struct ahd_softc *ahd,
u_int adapter_control);
static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat);
struct ahd_pci_identity *
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
ahd_find_pci_device(aic_dev_softc_t pci)
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
{
uint64_t full_id;
uint16_t device;
uint16_t vendor;
uint16_t subdevice;
uint16_t subvendor;
struct ahd_pci_identity *entry;
u_int i;
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
vendor = aic_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
device = aic_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
subvendor = aic_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
subdevice = aic_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
full_id = ahd_compose_id(device,
vendor,
subdevice,
subvendor);
aic79xx.c: aic79xx.seq: Convert the COMPLETE_DMA_SCB list to an "stailq". This allows us to safely keep the SCB that is currently being DMA'ed back the host on the head of the list while processing completions off of the bus. The newly completed SCBs are appended to the tail of the queue. In the past, we just dequeued the SCB that was in flight from the list, but this could result in a lost completion should the host perform certain types of error recovery that must cancel all in-flight SCB DMA operations. Switch from using a 16bit completion entry, holding just the tag and the completion valid bit, to a 64bit completion entry that also contains a "status packet valid" indicator. This solves two problems: o The SCB DMA engine on at least Rev B. silicon does not properly deal with a PCI disconnect that occurs at a non-64bit aligned offset in the chips "source buffer". When the transfer is resumed, the DMA engine continues at the correct offset, but may wrap to the head of the buffer causing duplicate completions to be reported to the host. By using a completion buffer in host memory that is 64bit aligned and using 64bit completion entries, such disconnects should only occur at aligned addresses. This assumes that the host bridge will only disconnect on cache-line boundaries and that cache-lines are multpiles of 64bits. o By embedding the status information in the completion entry we can avoid an extra memory reference to the HSCB for commands that complete without error. Use the comparison of a "host freeze count" and a "sequencer freeze count" to allow the host to process most SCBs that complete with non-zero status without having to clear critical sections. Instead the host can just pause the sequencer, performs any necessary cleanup in the waiting for selection list, increments its freeze count on the controller, and unpauses. This is only possible because the sequencer defers completions of SCBs with bad status until after all pending selections have completed. The sequencer then avoids referencing any data structures the host may touch during completion of the SCB until the freeze counts match. aic79xx.c: Change the strategy for allocating our sentinal HSCB for the QINFIFO. In the past, this allocation was tacked onto the QOUTFIFO allocation. Now that the qoutfifo has grown to accomodate larger completion entries, the old approach will result in a 64byte allocation that costs an extra page of coherent memory. We now do this extra allocation via ahd_alloc_scbs() where the "unused space" can be used to allocate "normal" HSCBs. In our packetized busfree handler, use the ENSELO bit to differentiate between packetized and non-packetized unexpected busfree events that occur just after selection, but before the sequencer has had the oportunity to service the selection. When cleaning out the waiting for selection list, use the SCSI mode instead of the command channel mode. The SCB pointer in the command channel mode may be referenced by the SCB dma engine even while the sequencer is paused, whereas the SCSI mode SCB pointer is only accessed by the sequencer. Print the "complete on qfreeze" sequencer SCB completion list in ahd_dump_card_state(). This list holds all SCB completions that are deferred until a pending select-out qfreeze event has taken effect. aic79xx.h: Add definitions and structures to handle the new SCB completion scheme. Add a controller flag that indicates if the controller is in HostRAID mode. aic79xx.reg: Remove macros used for toggling from one data fifo mode to the other. They have not been in use for some time. Add scratch ram fields for our new qfreeze count scheme, converting the complete dma list into an "stailq", and providing for the "complete on qfreeze" SCB completion list. Some other fields were moved to retain proper field alignment (alignment >= field size in bytes). aic79xx.seq: Add code to our idle loop to: o Process deferred completions once a qfreeze event has taken full effect. o Thaw the queue once the sequencer and host qfreeze counts match. Generate 64bit completion entries passing the SCB_SGPTR field as the "good status" indicator. The first bit in this field is only set if we have a valid status packet to send to the host. Convert the COMPLETE_DMA_SCB list to an "stailq". When using "setjmp" to register an idle loop handler, do not combine the "ret" with the block move to pop the stack address in the same instruction. At least on the A, this results in a return to the setjmp caller, not to the new address at the top of the stack. Since we want the latter (we want the newly registered handler to only be invoked from the idle loop), we must use a separate ret instruction. Add a few missing critical sections. Close a race condition that can occur on Rev A. silicon. If both FIFOs happen to be allocated before the sequencer has a chance to service the FIFO that was allocated first, we must take special care to service the FIFO that is not active on the SCSI bus first. This guarantees that a FIFO will be freed to handle any snapshot requests for the FIFO that is still on the bus. Chosing the incorrect FIFO will result in deadlock. Update comments. aic79xx_inline.h Correct the offset calculation for the syncing of our qoutfifo. Update ahd_check_cmdcmpltqueues() for the larger completion entries. aic79xx_pci.c: Attach to HostRAID controllers by default. In the future I may add a sysctl to modify the behavior, but since FreeBSD does not have any HostRAID drivers, failing to attach just results in more email and bug reports for the author. MFC After: 1week
2004-02-04 16:38:38 +00:00
/*
* If we are configured to attach to HostRAID
* controllers, mask out the IROC/HostRAID bit
* in the
*/
if (ahd_attach_to_HostRAID_controllers)
full_id &= ID_ALL_IROC_MASK;
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
for (i = 0; i < ahd_num_pci_devs; i++) {
entry = &ahd_pci_ident_table[i];
if (entry->full_id == (full_id & entry->id_mask)) {
/* Honor exclusion entries. */
if (entry->name == NULL)
return (NULL);
return (entry);
}
}
return (NULL);
}
int
ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry)
{
struct scb_data *shared_scb_data;
u_long l;
u_int command;
uint32_t devconfig;
aic79xx.c: aic79xx.seq: Convert the COMPLETE_DMA_SCB list to an "stailq". This allows us to safely keep the SCB that is currently being DMA'ed back the host on the head of the list while processing completions off of the bus. The newly completed SCBs are appended to the tail of the queue. In the past, we just dequeued the SCB that was in flight from the list, but this could result in a lost completion should the host perform certain types of error recovery that must cancel all in-flight SCB DMA operations. Switch from using a 16bit completion entry, holding just the tag and the completion valid bit, to a 64bit completion entry that also contains a "status packet valid" indicator. This solves two problems: o The SCB DMA engine on at least Rev B. silicon does not properly deal with a PCI disconnect that occurs at a non-64bit aligned offset in the chips "source buffer". When the transfer is resumed, the DMA engine continues at the correct offset, but may wrap to the head of the buffer causing duplicate completions to be reported to the host. By using a completion buffer in host memory that is 64bit aligned and using 64bit completion entries, such disconnects should only occur at aligned addresses. This assumes that the host bridge will only disconnect on cache-line boundaries and that cache-lines are multpiles of 64bits. o By embedding the status information in the completion entry we can avoid an extra memory reference to the HSCB for commands that complete without error. Use the comparison of a "host freeze count" and a "sequencer freeze count" to allow the host to process most SCBs that complete with non-zero status without having to clear critical sections. Instead the host can just pause the sequencer, performs any necessary cleanup in the waiting for selection list, increments its freeze count on the controller, and unpauses. This is only possible because the sequencer defers completions of SCBs with bad status until after all pending selections have completed. The sequencer then avoids referencing any data structures the host may touch during completion of the SCB until the freeze counts match. aic79xx.c: Change the strategy for allocating our sentinal HSCB for the QINFIFO. In the past, this allocation was tacked onto the QOUTFIFO allocation. Now that the qoutfifo has grown to accomodate larger completion entries, the old approach will result in a 64byte allocation that costs an extra page of coherent memory. We now do this extra allocation via ahd_alloc_scbs() where the "unused space" can be used to allocate "normal" HSCBs. In our packetized busfree handler, use the ENSELO bit to differentiate between packetized and non-packetized unexpected busfree events that occur just after selection, but before the sequencer has had the oportunity to service the selection. When cleaning out the waiting for selection list, use the SCSI mode instead of the command channel mode. The SCB pointer in the command channel mode may be referenced by the SCB dma engine even while the sequencer is paused, whereas the SCSI mode SCB pointer is only accessed by the sequencer. Print the "complete on qfreeze" sequencer SCB completion list in ahd_dump_card_state(). This list holds all SCB completions that are deferred until a pending select-out qfreeze event has taken effect. aic79xx.h: Add definitions and structures to handle the new SCB completion scheme. Add a controller flag that indicates if the controller is in HostRAID mode. aic79xx.reg: Remove macros used for toggling from one data fifo mode to the other. They have not been in use for some time. Add scratch ram fields for our new qfreeze count scheme, converting the complete dma list into an "stailq", and providing for the "complete on qfreeze" SCB completion list. Some other fields were moved to retain proper field alignment (alignment >= field size in bytes). aic79xx.seq: Add code to our idle loop to: o Process deferred completions once a qfreeze event has taken full effect. o Thaw the queue once the sequencer and host qfreeze counts match. Generate 64bit completion entries passing the SCB_SGPTR field as the "good status" indicator. The first bit in this field is only set if we have a valid status packet to send to the host. Convert the COMPLETE_DMA_SCB list to an "stailq". When using "setjmp" to register an idle loop handler, do not combine the "ret" with the block move to pop the stack address in the same instruction. At least on the A, this results in a return to the setjmp caller, not to the new address at the top of the stack. Since we want the latter (we want the newly registered handler to only be invoked from the idle loop), we must use a separate ret instruction. Add a few missing critical sections. Close a race condition that can occur on Rev A. silicon. If both FIFOs happen to be allocated before the sequencer has a chance to service the FIFO that was allocated first, we must take special care to service the FIFO that is not active on the SCSI bus first. This guarantees that a FIFO will be freed to handle any snapshot requests for the FIFO that is still on the bus. Chosing the incorrect FIFO will result in deadlock. Update comments. aic79xx_inline.h Correct the offset calculation for the syncing of our qoutfifo. Update ahd_check_cmdcmpltqueues() for the larger completion entries. aic79xx_pci.c: Attach to HostRAID controllers by default. In the future I may add a sysctl to modify the behavior, but since FreeBSD does not have any HostRAID drivers, failing to attach just results in more email and bug reports for the author. MFC After: 1week
2004-02-04 16:38:38 +00:00
uint16_t device;
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
uint16_t subvendor;
int error;
shared_scb_data = NULL;
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
ahd->description = entry->name;
aic79xx.c: aic79xx.seq: Convert the COMPLETE_DMA_SCB list to an "stailq". This allows us to safely keep the SCB that is currently being DMA'ed back the host on the head of the list while processing completions off of the bus. The newly completed SCBs are appended to the tail of the queue. In the past, we just dequeued the SCB that was in flight from the list, but this could result in a lost completion should the host perform certain types of error recovery that must cancel all in-flight SCB DMA operations. Switch from using a 16bit completion entry, holding just the tag and the completion valid bit, to a 64bit completion entry that also contains a "status packet valid" indicator. This solves two problems: o The SCB DMA engine on at least Rev B. silicon does not properly deal with a PCI disconnect that occurs at a non-64bit aligned offset in the chips "source buffer". When the transfer is resumed, the DMA engine continues at the correct offset, but may wrap to the head of the buffer causing duplicate completions to be reported to the host. By using a completion buffer in host memory that is 64bit aligned and using 64bit completion entries, such disconnects should only occur at aligned addresses. This assumes that the host bridge will only disconnect on cache-line boundaries and that cache-lines are multpiles of 64bits. o By embedding the status information in the completion entry we can avoid an extra memory reference to the HSCB for commands that complete without error. Use the comparison of a "host freeze count" and a "sequencer freeze count" to allow the host to process most SCBs that complete with non-zero status without having to clear critical sections. Instead the host can just pause the sequencer, performs any necessary cleanup in the waiting for selection list, increments its freeze count on the controller, and unpauses. This is only possible because the sequencer defers completions of SCBs with bad status until after all pending selections have completed. The sequencer then avoids referencing any data structures the host may touch during completion of the SCB until the freeze counts match. aic79xx.c: Change the strategy for allocating our sentinal HSCB for the QINFIFO. In the past, this allocation was tacked onto the QOUTFIFO allocation. Now that the qoutfifo has grown to accomodate larger completion entries, the old approach will result in a 64byte allocation that costs an extra page of coherent memory. We now do this extra allocation via ahd_alloc_scbs() where the "unused space" can be used to allocate "normal" HSCBs. In our packetized busfree handler, use the ENSELO bit to differentiate between packetized and non-packetized unexpected busfree events that occur just after selection, but before the sequencer has had the oportunity to service the selection. When cleaning out the waiting for selection list, use the SCSI mode instead of the command channel mode. The SCB pointer in the command channel mode may be referenced by the SCB dma engine even while the sequencer is paused, whereas the SCSI mode SCB pointer is only accessed by the sequencer. Print the "complete on qfreeze" sequencer SCB completion list in ahd_dump_card_state(). This list holds all SCB completions that are deferred until a pending select-out qfreeze event has taken effect. aic79xx.h: Add definitions and structures to handle the new SCB completion scheme. Add a controller flag that indicates if the controller is in HostRAID mode. aic79xx.reg: Remove macros used for toggling from one data fifo mode to the other. They have not been in use for some time. Add scratch ram fields for our new qfreeze count scheme, converting the complete dma list into an "stailq", and providing for the "complete on qfreeze" SCB completion list. Some other fields were moved to retain proper field alignment (alignment >= field size in bytes). aic79xx.seq: Add code to our idle loop to: o Process deferred completions once a qfreeze event has taken full effect. o Thaw the queue once the sequencer and host qfreeze counts match. Generate 64bit completion entries passing the SCB_SGPTR field as the "good status" indicator. The first bit in this field is only set if we have a valid status packet to send to the host. Convert the COMPLETE_DMA_SCB list to an "stailq". When using "setjmp" to register an idle loop handler, do not combine the "ret" with the block move to pop the stack address in the same instruction. At least on the A, this results in a return to the setjmp caller, not to the new address at the top of the stack. Since we want the latter (we want the newly registered handler to only be invoked from the idle loop), we must use a separate ret instruction. Add a few missing critical sections. Close a race condition that can occur on Rev A. silicon. If both FIFOs happen to be allocated before the sequencer has a chance to service the FIFO that was allocated first, we must take special care to service the FIFO that is not active on the SCSI bus first. This guarantees that a FIFO will be freed to handle any snapshot requests for the FIFO that is still on the bus. Chosing the incorrect FIFO will result in deadlock. Update comments. aic79xx_inline.h Correct the offset calculation for the syncing of our qoutfifo. Update ahd_check_cmdcmpltqueues() for the larger completion entries. aic79xx_pci.c: Attach to HostRAID controllers by default. In the future I may add a sysctl to modify the behavior, but since FreeBSD does not have any HostRAID drivers, failing to attach just results in more email and bug reports for the author. MFC After: 1week
2004-02-04 16:38:38 +00:00
/*
* Record if this is a HostRAID board.
*/
device = aic_pci_read_config(ahd->dev_softc,
PCIR_DEVICE, /*bytes*/2);
if (DEVID_9005_HOSTRAID(device))
ahd->flags |= AHD_HOSTRAID_BOARD;
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
/*
* Record if this is an HP board.
*/
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
subvendor = aic_pci_read_config(ahd->dev_softc,
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
PCIR_SUBVEND_0, /*bytes*/2);
if (subvendor == SUBID_HP)
ahd->flags |= AHD_HP_BOARD;
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
error = entry->setup(ahd);
if (error != 0)
return (error);
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) {
ahd->chip |= AHD_PCI;
/* Disable PCIX workarounds when running in PCI mode. */
ahd->bugs &= ~AHD_PCIX_BUG_MASK;
} else {
ahd->chip |= AHD_PCIX;
}
ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)];
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
aic_power_state_change(ahd, AIC_POWER_STATE_D0);
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
error = ahd_pci_map_registers(ahd);
if (error != 0)
return (error);
/*
* If we need to support high memory, enable dual
* address cycles. This bit must be set to enable
* high address bit generation even if we are on a
* 64bit bus (PCI64BIT set in devconfig).
*/
if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) {
uint32_t devconfig;
if (bootverbose)
printf("%s: Enabling 39Bit Addressing\n",
ahd_name(ahd));
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
devconfig = aic_pci_read_config(ahd->dev_softc,
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
DEVCONFIG, /*bytes*/4);
devconfig |= DACEN;
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
aic_pci_write_config(ahd->dev_softc, DEVCONFIG,
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
devconfig, /*bytes*/4);
}
/* Ensure busmastering is enabled */
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
command = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
command |= PCIM_CMD_BUSMASTEREN;
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
error = ahd_softc_init(ahd);
if (error != 0)
return (error);
ahd->bus_intr = ahd_pci_intr;
aic7770.c: aic79xx.c: aic79xx.h: aic79xx_pci.c: aic7xxx.c: aic7xxx.h: aic7xxx_pci.c: Switch ah?_reset() to take an additional "reinit" argument. Use this instead of init_level to determin if the chip should be fully reinitialized after a chip reset. This is required so that ah?_shutdown() can reset the chip without side-effects. aic79xx.c: Implement ahd_suspend() and ahd_resume(). aic7xxx.c: Change ahc_loadseq() to *not* restart the sequencer. This brings the loadseq behavior in line with that of the 7902 driver and also simplifies the init routine. Correct the resume routine to enable interrupts and restart the sequencer.
2003-06-06 23:48:19 +00:00
error = ahd_reset(ahd, /*reinit*/FALSE);
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
if (error != 0)
return (ENXIO);
ahd->pci_cachesize =
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
aic_pci_read_config(ahd->dev_softc, CSIZE_LATTIME,
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
/*bytes*/1) & CACHESIZE;
ahd->pci_cachesize *= 4;
ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
/* See if we have a SEEPROM and perform auto-term */
error = ahd_check_extport(ahd);
if (error != 0)
return (error);
/* Core initialization */
error = ahd_init(ahd);
if (error != 0)
return (error);
/*
* Allow interrupts now that we are completely setup.
*/
error = ahd_pci_map_int(ahd);
if (error != 0)
return (error);
ahd_list_lock(&l);
/*
* Link this softc in with all other ahd instances.
*/
ahd_softc_insert(ahd);
ahd_list_unlock(&l);
return (0);
}
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
/*
* Perform some simple tests that should catch situations where
* our registers are invalidly mapped.
*/
int
ahd_pci_test_register_access(struct ahd_softc *ahd)
{
Clear stale PCI errors during our test for successfully mapping our registers. This avoids the disabling of memory mapped I/O just because some other driver probe happened to touch our registers.
2003-06-06 23:52:34 +00:00
uint32_t cmd;
u_int targpcistat;
u_int pci_status1;
int error;
uint8_t hcntrl;
Last minute fixes to ahc and ahd: ahd_pci.c: Retrieve the allow_memio hint from the resource manager to determine whether or not to try PCI MEMIO. aic79xx_osm.h: aic7xxx_osm.h: Don't wrongly abuse the callout_reset() interface when trying to abuse timeouts generated from the CAM layer. This fixes the console freeze and lost timeout problem that many have reported, especially on SMP systems. aic79xx_pci.c aic7xxx_pci.c Rewrite the MEMIO test routine to prevent certain broken chipsets from trying to burst multiple DWORDs to the registers. Also make the routine better detect byte merging by the host bridge and deal with it. aic79xx.reg: Correct an incorrect register definition. Approved by: re (rwatson, jhb)
2002-12-04 22:51:29 +00:00
error = EIO;
aic79xx.c: Implement the SCB_SILENT flag. This is useful for hushing up the driver during DV or other operations that we expect to cause transmission errors. The messages will still print if the SHOW_MASKED_ERRORS debug option is enabled. Save and restore the NEGOADDR address when setting new transfer settings. The sequencer performs lookups in the negotiation table too and it expects NEGOADDR to remain consistent across pause/unpause sessions. Consistently use "offset" instead of "period" to determine if we are running sync or not. Add a SHOW_MESSAGES diagnostic for when we assert ATN during message processing. Print out IU, QAS, and RTI features when showing transfer options. Limit the syncrate after all option conformance changes have taken place in ahd_devlimited_syncrate. Changes in options may change the final syncrate we accept. Keep a copy of the hs_mailbox in our softc so that we can perform read/modify/write operations on the hs_mailbox without having to pause the sequencer to read the last written value. Use the ENINT_COALESS flag in the hs_mailbox to toggle interrupt coalessing. Add entrypoints for enabling interrupt coalessing and setting both a timeout (how long to wait for commands to be coalessed) and a maximum commands to coaless value. Add a statistics timer that decides when to enable or disable interrupt coalessing based on load. Add a routine, ahd_reset_cmds_pending() which is used to update the CMDS_PENDING sequencer variable whenever error recovery compeltes SCBs without notifying the sequencer. Since ahd_reset_cmds_pending is called during ahd_unpause() only if we've aborted SCBs, its call to ahd_flush_qoutfifo should not cause recursion through ahd_run_qoutfifo(). A panic has been added to ensure that this recursion does not occur. In ahd_search_qinfifo, update the CMDS_PENDING sequencer variable directly. ahd_search_qinififo can be called in situations where using ahd_reset_cmds_pending() might cause recursion. Since we can safely determine the exact number to reduce CMDS_PENDING by in this scenario without running the qoutfifo, the manual update is sufficient. Clean up diagnostics. Add ahd_flush_qoutfifo() which will run the qoutfifo as well as complete any commands sitting on the sequencer's COMPLETE_SCB lists or the good status FIFO. Use this routine in several places that did similar things in an add-hoc, but incomplete, fashion. A call to this routine was also added to ahd_abort_scbs() to close a race. In ahd_pause_and_flushwork() only return once selections are safely disabled. Flush all completed commands via ahd_flush_qoutfifo(). Remove "Now packetized" diagnostic now that this information is incorperated into the actual negotiation messages that are displayed. When forcing renegotiation, don't clober the current ppr_options. Much of the driver uses this information to determine if we are currently packetized or not. Remove some stray spaces at column 1 in ahd_set_tags. When complaining about getting a host message loop request with no pending messages, print out the SCB_CONTROL register down on the card. Modify the ahd_sent_msg() routine to handle a search for an outgoing identify message. Use this to detect a msg reject on an identify message which typically indicates that the target thought we were packetized. Force a renegotiation in this case. In ahd_search_qinfifo(), wait more effectively for SCB DMA activities to cease. We also disable SCB fetch operations since we are about to change the qinfifo and any fetch in progress will likely be invalidated. In ahd_qinfifo_count(), fix the qinfifo empty case. In ahd_dump_card_state(), print out CCSCBCTL in the correct mode. If we are a narrow controller, don't set the current width to unknown when forcing a future negotiation. This just confuses the code into attempting a wide negotiation on a narrow bus. Add support for task management function completions. Modify ahd_handle_devreset so that it can handle lun resets in addition to target resets. Use ahd_handle_devreset for lun and target reset task management functions. Handle the abort task TMF race case better. We now wait until any current selections are over and then set the TMF back to zero. This should cause the sequencer to ignore the abort TMF completion should it occur. Correct a bug in the illegal phase handler that caused us to drop down to narrow when handling the unexpected command phase case after 3rd party reset of a packetized device. Indicate the features, bugs, and flags set in the softc that are used to control firmware patch download when booting verbose. aic79xx.h: Add coalessing and HS_MAILBOX fields. Add per-softc variables for the stats "daemon". Add a debug option for interrupt coalessing activities. Add two new softc flags: o AHD_UPDATE_PEND_CMDS Run ahd_reset_cmds_pending() on the next unpause. o AHD_RUNNING_QOUTFIFO Used to catch recursion through ahd_run_qoutfifo(). aic79xx.reg: Correct register addresses related to the software timer and the DFDBCTL register. Add constants paramaterizing the software timer. Add scratch ram locations for storing interrupt coalessing tunables. Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2. In at least the REV A, these are writable bits. We make use of that for a swtimer workaround in the sequencer. Since HS_MAILBOX autoclears, provide a sequencer variable to store its contents. Add SEQINT codes for handling task management completions. aic79xx.seq: Correct ignore wide residue processing check for a wide negotiation being in effect. We must be in the SCSI register window in order to access the negotiation table. Use the software timer and a commands completed count to implement interrupt coalessing. The command complete is deferred until either the maximum command threshold or a the expiration of a command deferral timer. If we have more SCBs to complete to the host (sitting in COMPLETE_SCB lists), always try to coaless them up to our coalessing limit. If coalessing is enabled, but we have fewer commands oustanting than the host's min coalessing limit, complete the command immediately. Add code to track the number of commands outstanding. Commands are outstanding from the time they are placed into the execution queue until the DMA to post completion is setup. Add a workaround for intvec_2 interrupts on the H2A4. In H2A4, the mode pointer is not saved for intvec2, but is restored on iret. This can lead to the restoration of a bogus mode ptr. Manually clear the intmask bits and do a normal return to compensate. We use intvec_2 to track interrupt coalessing timeouts. Since we cannot disable the swtimer's countdown, simply mask its interrupt once we no longer care about it firing. In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime we are notified of an HS_MAILBOX update via the HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a local copy of persistant portions of the HS_MAILBOX as the mailbox auto-clears on any read. Move the test for the cfg4istat interrupt up an instruction to hopefully close a race between the next outgoing selection and our disabling of selections. Add a missing ret to the last instruction in load_overrun_buf. Add notifications to the host of task management completions as well as the completions for commands that completed successfully before their corresponding TMF could be sent. Hold a critical section during select-out processing until we have a fully identified connection. This removes a race condition with the legacy abort handler. Correct a few spelling errors in some comments. aic79xx_inline.h: Call ahd_reset_cmds_pending() in ahd_unpause if required. Update cmdcmplt interrupt statistics in our interrupt handler. Allow callers to ahd_send_scb() to set the task management function. aic79xx_pci.c: Disable SERR and pause the controller prior to performing our mmapped I/O test. The U320 controllers do not support "auto-access-pause". aic79xx_osm.c: Set the task management function now that ahd_send_scb() doesn't do it for us. We also perform a lun reset in response to BDR requests to packetized devices.
2003-01-20 20:17:35 +00:00
/*
* Enable PCI error interrupt status, but suppress NMIs
* generated by SERR raised due to target aborts.
*/
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
cmd = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
aic79xx.c: Implement the SCB_SILENT flag. This is useful for hushing up the driver during DV or other operations that we expect to cause transmission errors. The messages will still print if the SHOW_MASKED_ERRORS debug option is enabled. Save and restore the NEGOADDR address when setting new transfer settings. The sequencer performs lookups in the negotiation table too and it expects NEGOADDR to remain consistent across pause/unpause sessions. Consistently use "offset" instead of "period" to determine if we are running sync or not. Add a SHOW_MESSAGES diagnostic for when we assert ATN during message processing. Print out IU, QAS, and RTI features when showing transfer options. Limit the syncrate after all option conformance changes have taken place in ahd_devlimited_syncrate. Changes in options may change the final syncrate we accept. Keep a copy of the hs_mailbox in our softc so that we can perform read/modify/write operations on the hs_mailbox without having to pause the sequencer to read the last written value. Use the ENINT_COALESS flag in the hs_mailbox to toggle interrupt coalessing. Add entrypoints for enabling interrupt coalessing and setting both a timeout (how long to wait for commands to be coalessed) and a maximum commands to coaless value. Add a statistics timer that decides when to enable or disable interrupt coalessing based on load. Add a routine, ahd_reset_cmds_pending() which is used to update the CMDS_PENDING sequencer variable whenever error recovery compeltes SCBs without notifying the sequencer. Since ahd_reset_cmds_pending is called during ahd_unpause() only if we've aborted SCBs, its call to ahd_flush_qoutfifo should not cause recursion through ahd_run_qoutfifo(). A panic has been added to ensure that this recursion does not occur. In ahd_search_qinfifo, update the CMDS_PENDING sequencer variable directly. ahd_search_qinififo can be called in situations where using ahd_reset_cmds_pending() might cause recursion. Since we can safely determine the exact number to reduce CMDS_PENDING by in this scenario without running the qoutfifo, the manual update is sufficient. Clean up diagnostics. Add ahd_flush_qoutfifo() which will run the qoutfifo as well as complete any commands sitting on the sequencer's COMPLETE_SCB lists or the good status FIFO. Use this routine in several places that did similar things in an add-hoc, but incomplete, fashion. A call to this routine was also added to ahd_abort_scbs() to close a race. In ahd_pause_and_flushwork() only return once selections are safely disabled. Flush all completed commands via ahd_flush_qoutfifo(). Remove "Now packetized" diagnostic now that this information is incorperated into the actual negotiation messages that are displayed. When forcing renegotiation, don't clober the current ppr_options. Much of the driver uses this information to determine if we are currently packetized or not. Remove some stray spaces at column 1 in ahd_set_tags. When complaining about getting a host message loop request with no pending messages, print out the SCB_CONTROL register down on the card. Modify the ahd_sent_msg() routine to handle a search for an outgoing identify message. Use this to detect a msg reject on an identify message which typically indicates that the target thought we were packetized. Force a renegotiation in this case. In ahd_search_qinfifo(), wait more effectively for SCB DMA activities to cease. We also disable SCB fetch operations since we are about to change the qinfifo and any fetch in progress will likely be invalidated. In ahd_qinfifo_count(), fix the qinfifo empty case. In ahd_dump_card_state(), print out CCSCBCTL in the correct mode. If we are a narrow controller, don't set the current width to unknown when forcing a future negotiation. This just confuses the code into attempting a wide negotiation on a narrow bus. Add support for task management function completions. Modify ahd_handle_devreset so that it can handle lun resets in addition to target resets. Use ahd_handle_devreset for lun and target reset task management functions. Handle the abort task TMF race case better. We now wait until any current selections are over and then set the TMF back to zero. This should cause the sequencer to ignore the abort TMF completion should it occur. Correct a bug in the illegal phase handler that caused us to drop down to narrow when handling the unexpected command phase case after 3rd party reset of a packetized device. Indicate the features, bugs, and flags set in the softc that are used to control firmware patch download when booting verbose. aic79xx.h: Add coalessing and HS_MAILBOX fields. Add per-softc variables for the stats "daemon". Add a debug option for interrupt coalessing activities. Add two new softc flags: o AHD_UPDATE_PEND_CMDS Run ahd_reset_cmds_pending() on the next unpause. o AHD_RUNNING_QOUTFIFO Used to catch recursion through ahd_run_qoutfifo(). aic79xx.reg: Correct register addresses related to the software timer and the DFDBCTL register. Add constants paramaterizing the software timer. Add scratch ram locations for storing interrupt coalessing tunables. Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2. In at least the REV A, these are writable bits. We make use of that for a swtimer workaround in the sequencer. Since HS_MAILBOX autoclears, provide a sequencer variable to store its contents. Add SEQINT codes for handling task management completions. aic79xx.seq: Correct ignore wide residue processing check for a wide negotiation being in effect. We must be in the SCSI register window in order to access the negotiation table. Use the software timer and a commands completed count to implement interrupt coalessing. The command complete is deferred until either the maximum command threshold or a the expiration of a command deferral timer. If we have more SCBs to complete to the host (sitting in COMPLETE_SCB lists), always try to coaless them up to our coalessing limit. If coalessing is enabled, but we have fewer commands oustanting than the host's min coalessing limit, complete the command immediately. Add code to track the number of commands outstanding. Commands are outstanding from the time they are placed into the execution queue until the DMA to post completion is setup. Add a workaround for intvec_2 interrupts on the H2A4. In H2A4, the mode pointer is not saved for intvec2, but is restored on iret. This can lead to the restoration of a bogus mode ptr. Manually clear the intmask bits and do a normal return to compensate. We use intvec_2 to track interrupt coalessing timeouts. Since we cannot disable the swtimer's countdown, simply mask its interrupt once we no longer care about it firing. In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime we are notified of an HS_MAILBOX update via the HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a local copy of persistant portions of the HS_MAILBOX as the mailbox auto-clears on any read. Move the test for the cfg4istat interrupt up an instruction to hopefully close a race between the next outgoing selection and our disabling of selections. Add a missing ret to the last instruction in load_overrun_buf. Add notifications to the host of task management completions as well as the completions for commands that completed successfully before their corresponding TMF could be sent. Hold a critical section during select-out processing until we have a fully identified connection. This removes a race condition with the legacy abort handler. Correct a few spelling errors in some comments. aic79xx_inline.h: Call ahd_reset_cmds_pending() in ahd_unpause if required. Update cmdcmplt interrupt statistics in our interrupt handler. Allow callers to ahd_send_scb() to set the task management function. aic79xx_pci.c: Disable SERR and pause the controller prior to performing our mmapped I/O test. The U320 controllers do not support "auto-access-pause". aic79xx_osm.c: Set the task management function now that ahd_send_scb() doesn't do it for us. We also perform a lun reset in response to BDR requests to packetized devices.
2003-01-20 20:17:35 +00:00
cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
/*
* First a simple test to see if any
* registers can be read. Reading
* HCNTRL has no side effects and has
* at least one bit that is guaranteed to
* be zero so it is a good register to
* use for this test.
*/
aic79xx.c: Implement the SCB_SILENT flag. This is useful for hushing up the driver during DV or other operations that we expect to cause transmission errors. The messages will still print if the SHOW_MASKED_ERRORS debug option is enabled. Save and restore the NEGOADDR address when setting new transfer settings. The sequencer performs lookups in the negotiation table too and it expects NEGOADDR to remain consistent across pause/unpause sessions. Consistently use "offset" instead of "period" to determine if we are running sync or not. Add a SHOW_MESSAGES diagnostic for when we assert ATN during message processing. Print out IU, QAS, and RTI features when showing transfer options. Limit the syncrate after all option conformance changes have taken place in ahd_devlimited_syncrate. Changes in options may change the final syncrate we accept. Keep a copy of the hs_mailbox in our softc so that we can perform read/modify/write operations on the hs_mailbox without having to pause the sequencer to read the last written value. Use the ENINT_COALESS flag in the hs_mailbox to toggle interrupt coalessing. Add entrypoints for enabling interrupt coalessing and setting both a timeout (how long to wait for commands to be coalessed) and a maximum commands to coaless value. Add a statistics timer that decides when to enable or disable interrupt coalessing based on load. Add a routine, ahd_reset_cmds_pending() which is used to update the CMDS_PENDING sequencer variable whenever error recovery compeltes SCBs without notifying the sequencer. Since ahd_reset_cmds_pending is called during ahd_unpause() only if we've aborted SCBs, its call to ahd_flush_qoutfifo should not cause recursion through ahd_run_qoutfifo(). A panic has been added to ensure that this recursion does not occur. In ahd_search_qinfifo, update the CMDS_PENDING sequencer variable directly. ahd_search_qinififo can be called in situations where using ahd_reset_cmds_pending() might cause recursion. Since we can safely determine the exact number to reduce CMDS_PENDING by in this scenario without running the qoutfifo, the manual update is sufficient. Clean up diagnostics. Add ahd_flush_qoutfifo() which will run the qoutfifo as well as complete any commands sitting on the sequencer's COMPLETE_SCB lists or the good status FIFO. Use this routine in several places that did similar things in an add-hoc, but incomplete, fashion. A call to this routine was also added to ahd_abort_scbs() to close a race. In ahd_pause_and_flushwork() only return once selections are safely disabled. Flush all completed commands via ahd_flush_qoutfifo(). Remove "Now packetized" diagnostic now that this information is incorperated into the actual negotiation messages that are displayed. When forcing renegotiation, don't clober the current ppr_options. Much of the driver uses this information to determine if we are currently packetized or not. Remove some stray spaces at column 1 in ahd_set_tags. When complaining about getting a host message loop request with no pending messages, print out the SCB_CONTROL register down on the card. Modify the ahd_sent_msg() routine to handle a search for an outgoing identify message. Use this to detect a msg reject on an identify message which typically indicates that the target thought we were packetized. Force a renegotiation in this case. In ahd_search_qinfifo(), wait more effectively for SCB DMA activities to cease. We also disable SCB fetch operations since we are about to change the qinfifo and any fetch in progress will likely be invalidated. In ahd_qinfifo_count(), fix the qinfifo empty case. In ahd_dump_card_state(), print out CCSCBCTL in the correct mode. If we are a narrow controller, don't set the current width to unknown when forcing a future negotiation. This just confuses the code into attempting a wide negotiation on a narrow bus. Add support for task management function completions. Modify ahd_handle_devreset so that it can handle lun resets in addition to target resets. Use ahd_handle_devreset for lun and target reset task management functions. Handle the abort task TMF race case better. We now wait until any current selections are over and then set the TMF back to zero. This should cause the sequencer to ignore the abort TMF completion should it occur. Correct a bug in the illegal phase handler that caused us to drop down to narrow when handling the unexpected command phase case after 3rd party reset of a packetized device. Indicate the features, bugs, and flags set in the softc that are used to control firmware patch download when booting verbose. aic79xx.h: Add coalessing and HS_MAILBOX fields. Add per-softc variables for the stats "daemon". Add a debug option for interrupt coalessing activities. Add two new softc flags: o AHD_UPDATE_PEND_CMDS Run ahd_reset_cmds_pending() on the next unpause. o AHD_RUNNING_QOUTFIFO Used to catch recursion through ahd_run_qoutfifo(). aic79xx.reg: Correct register addresses related to the software timer and the DFDBCTL register. Add constants paramaterizing the software timer. Add scratch ram locations for storing interrupt coalessing tunables. Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2. In at least the REV A, these are writable bits. We make use of that for a swtimer workaround in the sequencer. Since HS_MAILBOX autoclears, provide a sequencer variable to store its contents. Add SEQINT codes for handling task management completions. aic79xx.seq: Correct ignore wide residue processing check for a wide negotiation being in effect. We must be in the SCSI register window in order to access the negotiation table. Use the software timer and a commands completed count to implement interrupt coalessing. The command complete is deferred until either the maximum command threshold or a the expiration of a command deferral timer. If we have more SCBs to complete to the host (sitting in COMPLETE_SCB lists), always try to coaless them up to our coalessing limit. If coalessing is enabled, but we have fewer commands oustanting than the host's min coalessing limit, complete the command immediately. Add code to track the number of commands outstanding. Commands are outstanding from the time they are placed into the execution queue until the DMA to post completion is setup. Add a workaround for intvec_2 interrupts on the H2A4. In H2A4, the mode pointer is not saved for intvec2, but is restored on iret. This can lead to the restoration of a bogus mode ptr. Manually clear the intmask bits and do a normal return to compensate. We use intvec_2 to track interrupt coalessing timeouts. Since we cannot disable the swtimer's countdown, simply mask its interrupt once we no longer care about it firing. In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime we are notified of an HS_MAILBOX update via the HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a local copy of persistant portions of the HS_MAILBOX as the mailbox auto-clears on any read. Move the test for the cfg4istat interrupt up an instruction to hopefully close a race between the next outgoing selection and our disabling of selections. Add a missing ret to the last instruction in load_overrun_buf. Add notifications to the host of task management completions as well as the completions for commands that completed successfully before their corresponding TMF could be sent. Hold a critical section during select-out processing until we have a fully identified connection. This removes a race condition with the legacy abort handler. Correct a few spelling errors in some comments. aic79xx_inline.h: Call ahd_reset_cmds_pending() in ahd_unpause if required. Update cmdcmplt interrupt statistics in our interrupt handler. Allow callers to ahd_send_scb() to set the task management function. aic79xx_pci.c: Disable SERR and pause the controller prior to performing our mmapped I/O test. The U320 controllers do not support "auto-access-pause". aic79xx_osm.c: Set the task management function now that ahd_send_scb() doesn't do it for us. We also perform a lun reset in response to BDR requests to packetized devices.
2003-01-20 20:17:35 +00:00
hcntrl = ahd_inb(ahd, HCNTRL);
if (hcntrl == 0xFF)
Last minute fixes to ahc and ahd: ahd_pci.c: Retrieve the allow_memio hint from the resource manager to determine whether or not to try PCI MEMIO. aic79xx_osm.h: aic7xxx_osm.h: Don't wrongly abuse the callout_reset() interface when trying to abuse timeouts generated from the CAM layer. This fixes the console freeze and lost timeout problem that many have reported, especially on SMP systems. aic79xx_pci.c aic7xxx_pci.c Rewrite the MEMIO test routine to prevent certain broken chipsets from trying to burst multiple DWORDs to the registers. Also make the routine better detect byte merging by the host bridge and deal with it. aic79xx.reg: Correct an incorrect register definition. Approved by: re (rwatson, jhb)
2002-12-04 22:51:29 +00:00
goto fail;
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
/*
* Next create a situation where write combining
* or read prefetching could be initiated by the
* CPU or host bridge. Our device does not support
* either, so look for data corruption and/or flaged
aic79xx_pci.c: aic7xxx_pci.c: When performing our register test, be careful to avoid resetting the chip when pausing the controller. The test reads the HCNTRL register and then writes it back with the PAUSE bit explicitly set. If the last write to the controller before our probe is to reset it, the CHIPRST bit will still be set, so we must mask it off before the PAUSE operation. On some chip versions, we cannot access registers for a few 100us after a reset, so this inadvertant reset was causing PCI errors to occur on the read to check for paused status. Submitted by: gibbs
2003-09-25 23:36:41 +00:00
* PCI errors. First pause without causing another
* chip reset.
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
*/
aic79xx_pci.c: aic7xxx_pci.c: When performing our register test, be careful to avoid resetting the chip when pausing the controller. The test reads the HCNTRL register and then writes it back with the PAUSE bit explicitly set. If the last write to the controller before our probe is to reset it, the CHIPRST bit will still be set, so we must mask it off before the PAUSE operation. On some chip versions, we cannot access registers for a few 100us after a reset, so this inadvertant reset was causing PCI errors to occur on the read to check for paused status. Submitted by: gibbs
2003-09-25 23:36:41 +00:00
hcntrl &= ~CHIPRST;
aic79xx.c: Implement the SCB_SILENT flag. This is useful for hushing up the driver during DV or other operations that we expect to cause transmission errors. The messages will still print if the SHOW_MASKED_ERRORS debug option is enabled. Save and restore the NEGOADDR address when setting new transfer settings. The sequencer performs lookups in the negotiation table too and it expects NEGOADDR to remain consistent across pause/unpause sessions. Consistently use "offset" instead of "period" to determine if we are running sync or not. Add a SHOW_MESSAGES diagnostic for when we assert ATN during message processing. Print out IU, QAS, and RTI features when showing transfer options. Limit the syncrate after all option conformance changes have taken place in ahd_devlimited_syncrate. Changes in options may change the final syncrate we accept. Keep a copy of the hs_mailbox in our softc so that we can perform read/modify/write operations on the hs_mailbox without having to pause the sequencer to read the last written value. Use the ENINT_COALESS flag in the hs_mailbox to toggle interrupt coalessing. Add entrypoints for enabling interrupt coalessing and setting both a timeout (how long to wait for commands to be coalessed) and a maximum commands to coaless value. Add a statistics timer that decides when to enable or disable interrupt coalessing based on load. Add a routine, ahd_reset_cmds_pending() which is used to update the CMDS_PENDING sequencer variable whenever error recovery compeltes SCBs without notifying the sequencer. Since ahd_reset_cmds_pending is called during ahd_unpause() only if we've aborted SCBs, its call to ahd_flush_qoutfifo should not cause recursion through ahd_run_qoutfifo(). A panic has been added to ensure that this recursion does not occur. In ahd_search_qinfifo, update the CMDS_PENDING sequencer variable directly. ahd_search_qinififo can be called in situations where using ahd_reset_cmds_pending() might cause recursion. Since we can safely determine the exact number to reduce CMDS_PENDING by in this scenario without running the qoutfifo, the manual update is sufficient. Clean up diagnostics. Add ahd_flush_qoutfifo() which will run the qoutfifo as well as complete any commands sitting on the sequencer's COMPLETE_SCB lists or the good status FIFO. Use this routine in several places that did similar things in an add-hoc, but incomplete, fashion. A call to this routine was also added to ahd_abort_scbs() to close a race. In ahd_pause_and_flushwork() only return once selections are safely disabled. Flush all completed commands via ahd_flush_qoutfifo(). Remove "Now packetized" diagnostic now that this information is incorperated into the actual negotiation messages that are displayed. When forcing renegotiation, don't clober the current ppr_options. Much of the driver uses this information to determine if we are currently packetized or not. Remove some stray spaces at column 1 in ahd_set_tags. When complaining about getting a host message loop request with no pending messages, print out the SCB_CONTROL register down on the card. Modify the ahd_sent_msg() routine to handle a search for an outgoing identify message. Use this to detect a msg reject on an identify message which typically indicates that the target thought we were packetized. Force a renegotiation in this case. In ahd_search_qinfifo(), wait more effectively for SCB DMA activities to cease. We also disable SCB fetch operations since we are about to change the qinfifo and any fetch in progress will likely be invalidated. In ahd_qinfifo_count(), fix the qinfifo empty case. In ahd_dump_card_state(), print out CCSCBCTL in the correct mode. If we are a narrow controller, don't set the current width to unknown when forcing a future negotiation. This just confuses the code into attempting a wide negotiation on a narrow bus. Add support for task management function completions. Modify ahd_handle_devreset so that it can handle lun resets in addition to target resets. Use ahd_handle_devreset for lun and target reset task management functions. Handle the abort task TMF race case better. We now wait until any current selections are over and then set the TMF back to zero. This should cause the sequencer to ignore the abort TMF completion should it occur. Correct a bug in the illegal phase handler that caused us to drop down to narrow when handling the unexpected command phase case after 3rd party reset of a packetized device. Indicate the features, bugs, and flags set in the softc that are used to control firmware patch download when booting verbose. aic79xx.h: Add coalessing and HS_MAILBOX fields. Add per-softc variables for the stats "daemon". Add a debug option for interrupt coalessing activities. Add two new softc flags: o AHD_UPDATE_PEND_CMDS Run ahd_reset_cmds_pending() on the next unpause. o AHD_RUNNING_QOUTFIFO Used to catch recursion through ahd_run_qoutfifo(). aic79xx.reg: Correct register addresses related to the software timer and the DFDBCTL register. Add constants paramaterizing the software timer. Add scratch ram locations for storing interrupt coalessing tunables. Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2. In at least the REV A, these are writable bits. We make use of that for a swtimer workaround in the sequencer. Since HS_MAILBOX autoclears, provide a sequencer variable to store its contents. Add SEQINT codes for handling task management completions. aic79xx.seq: Correct ignore wide residue processing check for a wide negotiation being in effect. We must be in the SCSI register window in order to access the negotiation table. Use the software timer and a commands completed count to implement interrupt coalessing. The command complete is deferred until either the maximum command threshold or a the expiration of a command deferral timer. If we have more SCBs to complete to the host (sitting in COMPLETE_SCB lists), always try to coaless them up to our coalessing limit. If coalessing is enabled, but we have fewer commands oustanting than the host's min coalessing limit, complete the command immediately. Add code to track the number of commands outstanding. Commands are outstanding from the time they are placed into the execution queue until the DMA to post completion is setup. Add a workaround for intvec_2 interrupts on the H2A4. In H2A4, the mode pointer is not saved for intvec2, but is restored on iret. This can lead to the restoration of a bogus mode ptr. Manually clear the intmask bits and do a normal return to compensate. We use intvec_2 to track interrupt coalessing timeouts. Since we cannot disable the swtimer's countdown, simply mask its interrupt once we no longer care about it firing. In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime we are notified of an HS_MAILBOX update via the HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a local copy of persistant portions of the HS_MAILBOX as the mailbox auto-clears on any read. Move the test for the cfg4istat interrupt up an instruction to hopefully close a race between the next outgoing selection and our disabling of selections. Add a missing ret to the last instruction in load_overrun_buf. Add notifications to the host of task management completions as well as the completions for commands that completed successfully before their corresponding TMF could be sent. Hold a critical section during select-out processing until we have a fully identified connection. This removes a race condition with the legacy abort handler. Correct a few spelling errors in some comments. aic79xx_inline.h: Call ahd_reset_cmds_pending() in ahd_unpause if required. Update cmdcmplt interrupt statistics in our interrupt handler. Allow callers to ahd_send_scb() to set the task management function. aic79xx_pci.c: Disable SERR and pause the controller prior to performing our mmapped I/O test. The U320 controllers do not support "auto-access-pause". aic79xx_osm.c: Set the task management function now that ahd_send_scb() doesn't do it for us. We also perform a lun reset in response to BDR requests to packetized devices.
2003-01-20 20:17:35 +00:00
ahd_outb(ahd, HCNTRL, hcntrl|PAUSE);
while (ahd_is_paused(ahd) == 0)
;
Clear stale PCI errors during our test for successfully mapping our registers. This avoids the disabling of memory mapped I/O just because some other driver probe happened to touch our registers.
2003-06-06 23:52:34 +00:00
/* Clear any PCI errors that occurred before our driver attached. */
ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
targpcistat = ahd_inb(ahd, TARGPCISTAT);
ahd_outb(ahd, TARGPCISTAT, targpcistat);
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
pci_status1 = aic_pci_read_config(ahd->dev_softc,
Clear stale PCI errors during our test for successfully mapping our registers. This avoids the disabling of memory mapped I/O just because some other driver probe happened to touch our registers.
2003-06-06 23:52:34 +00:00
PCIR_STATUS + 1, /*bytes*/1);
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
Clear stale PCI errors during our test for successfully mapping our registers. This avoids the disabling of memory mapped I/O just because some other driver probe happened to touch our registers.
2003-06-06 23:52:34 +00:00
pci_status1, /*bytes*/1);
ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
ahd_outb(ahd, CLRINT, CLRPCIINT);
aic79xx.c: Implement the SCB_SILENT flag. This is useful for hushing up the driver during DV or other operations that we expect to cause transmission errors. The messages will still print if the SHOW_MASKED_ERRORS debug option is enabled. Save and restore the NEGOADDR address when setting new transfer settings. The sequencer performs lookups in the negotiation table too and it expects NEGOADDR to remain consistent across pause/unpause sessions. Consistently use "offset" instead of "period" to determine if we are running sync or not. Add a SHOW_MESSAGES diagnostic for when we assert ATN during message processing. Print out IU, QAS, and RTI features when showing transfer options. Limit the syncrate after all option conformance changes have taken place in ahd_devlimited_syncrate. Changes in options may change the final syncrate we accept. Keep a copy of the hs_mailbox in our softc so that we can perform read/modify/write operations on the hs_mailbox without having to pause the sequencer to read the last written value. Use the ENINT_COALESS flag in the hs_mailbox to toggle interrupt coalessing. Add entrypoints for enabling interrupt coalessing and setting both a timeout (how long to wait for commands to be coalessed) and a maximum commands to coaless value. Add a statistics timer that decides when to enable or disable interrupt coalessing based on load. Add a routine, ahd_reset_cmds_pending() which is used to update the CMDS_PENDING sequencer variable whenever error recovery compeltes SCBs without notifying the sequencer. Since ahd_reset_cmds_pending is called during ahd_unpause() only if we've aborted SCBs, its call to ahd_flush_qoutfifo should not cause recursion through ahd_run_qoutfifo(). A panic has been added to ensure that this recursion does not occur. In ahd_search_qinfifo, update the CMDS_PENDING sequencer variable directly. ahd_search_qinififo can be called in situations where using ahd_reset_cmds_pending() might cause recursion. Since we can safely determine the exact number to reduce CMDS_PENDING by in this scenario without running the qoutfifo, the manual update is sufficient. Clean up diagnostics. Add ahd_flush_qoutfifo() which will run the qoutfifo as well as complete any commands sitting on the sequencer's COMPLETE_SCB lists or the good status FIFO. Use this routine in several places that did similar things in an add-hoc, but incomplete, fashion. A call to this routine was also added to ahd_abort_scbs() to close a race. In ahd_pause_and_flushwork() only return once selections are safely disabled. Flush all completed commands via ahd_flush_qoutfifo(). Remove "Now packetized" diagnostic now that this information is incorperated into the actual negotiation messages that are displayed. When forcing renegotiation, don't clober the current ppr_options. Much of the driver uses this information to determine if we are currently packetized or not. Remove some stray spaces at column 1 in ahd_set_tags. When complaining about getting a host message loop request with no pending messages, print out the SCB_CONTROL register down on the card. Modify the ahd_sent_msg() routine to handle a search for an outgoing identify message. Use this to detect a msg reject on an identify message which typically indicates that the target thought we were packetized. Force a renegotiation in this case. In ahd_search_qinfifo(), wait more effectively for SCB DMA activities to cease. We also disable SCB fetch operations since we are about to change the qinfifo and any fetch in progress will likely be invalidated. In ahd_qinfifo_count(), fix the qinfifo empty case. In ahd_dump_card_state(), print out CCSCBCTL in the correct mode. If we are a narrow controller, don't set the current width to unknown when forcing a future negotiation. This just confuses the code into attempting a wide negotiation on a narrow bus. Add support for task management function completions. Modify ahd_handle_devreset so that it can handle lun resets in addition to target resets. Use ahd_handle_devreset for lun and target reset task management functions. Handle the abort task TMF race case better. We now wait until any current selections are over and then set the TMF back to zero. This should cause the sequencer to ignore the abort TMF completion should it occur. Correct a bug in the illegal phase handler that caused us to drop down to narrow when handling the unexpected command phase case after 3rd party reset of a packetized device. Indicate the features, bugs, and flags set in the softc that are used to control firmware patch download when booting verbose. aic79xx.h: Add coalessing and HS_MAILBOX fields. Add per-softc variables for the stats "daemon". Add a debug option for interrupt coalessing activities. Add two new softc flags: o AHD_UPDATE_PEND_CMDS Run ahd_reset_cmds_pending() on the next unpause. o AHD_RUNNING_QOUTFIFO Used to catch recursion through ahd_run_qoutfifo(). aic79xx.reg: Correct register addresses related to the software timer and the DFDBCTL register. Add constants paramaterizing the software timer. Add scratch ram locations for storing interrupt coalessing tunables. Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2. In at least the REV A, these are writable bits. We make use of that for a swtimer workaround in the sequencer. Since HS_MAILBOX autoclears, provide a sequencer variable to store its contents. Add SEQINT codes for handling task management completions. aic79xx.seq: Correct ignore wide residue processing check for a wide negotiation being in effect. We must be in the SCSI register window in order to access the negotiation table. Use the software timer and a commands completed count to implement interrupt coalessing. The command complete is deferred until either the maximum command threshold or a the expiration of a command deferral timer. If we have more SCBs to complete to the host (sitting in COMPLETE_SCB lists), always try to coaless them up to our coalessing limit. If coalessing is enabled, but we have fewer commands oustanting than the host's min coalessing limit, complete the command immediately. Add code to track the number of commands outstanding. Commands are outstanding from the time they are placed into the execution queue until the DMA to post completion is setup. Add a workaround for intvec_2 interrupts on the H2A4. In H2A4, the mode pointer is not saved for intvec2, but is restored on iret. This can lead to the restoration of a bogus mode ptr. Manually clear the intmask bits and do a normal return to compensate. We use intvec_2 to track interrupt coalessing timeouts. Since we cannot disable the swtimer's countdown, simply mask its interrupt once we no longer care about it firing. In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime we are notified of an HS_MAILBOX update via the HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a local copy of persistant portions of the HS_MAILBOX as the mailbox auto-clears on any read. Move the test for the cfg4istat interrupt up an instruction to hopefully close a race between the next outgoing selection and our disabling of selections. Add a missing ret to the last instruction in load_overrun_buf. Add notifications to the host of task management completions as well as the completions for commands that completed successfully before their corresponding TMF could be sent. Hold a critical section during select-out processing until we have a fully identified connection. This removes a race condition with the legacy abort handler. Correct a few spelling errors in some comments. aic79xx_inline.h: Call ahd_reset_cmds_pending() in ahd_unpause if required. Update cmdcmplt interrupt statistics in our interrupt handler. Allow callers to ahd_send_scb() to set the task management function. aic79xx_pci.c: Disable SERR and pause the controller prior to performing our mmapped I/O test. The U320 controllers do not support "auto-access-pause". aic79xx_osm.c: Set the task management function now that ahd_send_scb() doesn't do it for us. We also perform a lun reset in response to BDR requests to packetized devices.
2003-01-20 20:17:35 +00:00
ahd_outb(ahd, SEQCTL0, PERRORDIS);
Last minute fixes to ahc and ahd: ahd_pci.c: Retrieve the allow_memio hint from the resource manager to determine whether or not to try PCI MEMIO. aic79xx_osm.h: aic7xxx_osm.h: Don't wrongly abuse the callout_reset() interface when trying to abuse timeouts generated from the CAM layer. This fixes the console freeze and lost timeout problem that many have reported, especially on SMP systems. aic79xx_pci.c aic7xxx_pci.c Rewrite the MEMIO test routine to prevent certain broken chipsets from trying to burst multiple DWORDs to the registers. Also make the routine better detect byte merging by the host bridge and deal with it. aic79xx.reg: Correct an incorrect register definition. Approved by: re (rwatson, jhb)
2002-12-04 22:51:29 +00:00
ahd_outl(ahd, SRAM_BASE, 0x5aa555aa);
if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa)
goto fail;
if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
u_int targpcistat;
ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
targpcistat = ahd_inb(ahd, TARGPCISTAT);
if ((targpcistat & STA) != 0)
goto fail;
}
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
Last minute fixes to ahc and ahd: ahd_pci.c: Retrieve the allow_memio hint from the resource manager to determine whether or not to try PCI MEMIO. aic79xx_osm.h: aic7xxx_osm.h: Don't wrongly abuse the callout_reset() interface when trying to abuse timeouts generated from the CAM layer. This fixes the console freeze and lost timeout problem that many have reported, especially on SMP systems. aic79xx_pci.c aic7xxx_pci.c Rewrite the MEMIO test routine to prevent certain broken chipsets from trying to burst multiple DWORDs to the registers. Also make the routine better detect byte merging by the host bridge and deal with it. aic79xx.reg: Correct an incorrect register definition. Approved by: re (rwatson, jhb)
2002-12-04 22:51:29 +00:00
error = 0;
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
Last minute fixes to ahc and ahd: ahd_pci.c: Retrieve the allow_memio hint from the resource manager to determine whether or not to try PCI MEMIO. aic79xx_osm.h: aic7xxx_osm.h: Don't wrongly abuse the callout_reset() interface when trying to abuse timeouts generated from the CAM layer. This fixes the console freeze and lost timeout problem that many have reported, especially on SMP systems. aic79xx_pci.c aic7xxx_pci.c Rewrite the MEMIO test routine to prevent certain broken chipsets from trying to burst multiple DWORDs to the registers. Also make the routine better detect byte merging by the host bridge and deal with it. aic79xx.reg: Correct an incorrect register definition. Approved by: re (rwatson, jhb)
2002-12-04 22:51:29 +00:00
fail:
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
targpcistat = ahd_inb(ahd, TARGPCISTAT);
/* Silently clear any latched errors. */
ahd_outb(ahd, TARGPCISTAT, targpcistat);
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
pci_status1 = aic_pci_read_config(ahd->dev_softc,
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
PCIR_STATUS + 1, /*bytes*/1);
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
pci_status1, /*bytes*/1);
Last minute fixes to ahc and ahd: ahd_pci.c: Retrieve the allow_memio hint from the resource manager to determine whether or not to try PCI MEMIO. aic79xx_osm.h: aic7xxx_osm.h: Don't wrongly abuse the callout_reset() interface when trying to abuse timeouts generated from the CAM layer. This fixes the console freeze and lost timeout problem that many have reported, especially on SMP systems. aic79xx_pci.c aic7xxx_pci.c Rewrite the MEMIO test routine to prevent certain broken chipsets from trying to burst multiple DWORDs to the registers. Also make the routine better detect byte merging by the host bridge and deal with it. aic79xx.reg: Correct an incorrect register definition. Approved by: re (rwatson, jhb)
2002-12-04 22:51:29 +00:00
ahd_outb(ahd, CLRINT, CLRPCIINT);
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
}
aic79xx.c: Implement the SCB_SILENT flag. This is useful for hushing up the driver during DV or other operations that we expect to cause transmission errors. The messages will still print if the SHOW_MASKED_ERRORS debug option is enabled. Save and restore the NEGOADDR address when setting new transfer settings. The sequencer performs lookups in the negotiation table too and it expects NEGOADDR to remain consistent across pause/unpause sessions. Consistently use "offset" instead of "period" to determine if we are running sync or not. Add a SHOW_MESSAGES diagnostic for when we assert ATN during message processing. Print out IU, QAS, and RTI features when showing transfer options. Limit the syncrate after all option conformance changes have taken place in ahd_devlimited_syncrate. Changes in options may change the final syncrate we accept. Keep a copy of the hs_mailbox in our softc so that we can perform read/modify/write operations on the hs_mailbox without having to pause the sequencer to read the last written value. Use the ENINT_COALESS flag in the hs_mailbox to toggle interrupt coalessing. Add entrypoints for enabling interrupt coalessing and setting both a timeout (how long to wait for commands to be coalessed) and a maximum commands to coaless value. Add a statistics timer that decides when to enable or disable interrupt coalessing based on load. Add a routine, ahd_reset_cmds_pending() which is used to update the CMDS_PENDING sequencer variable whenever error recovery compeltes SCBs without notifying the sequencer. Since ahd_reset_cmds_pending is called during ahd_unpause() only if we've aborted SCBs, its call to ahd_flush_qoutfifo should not cause recursion through ahd_run_qoutfifo(). A panic has been added to ensure that this recursion does not occur. In ahd_search_qinfifo, update the CMDS_PENDING sequencer variable directly. ahd_search_qinififo can be called in situations where using ahd_reset_cmds_pending() might cause recursion. Since we can safely determine the exact number to reduce CMDS_PENDING by in this scenario without running the qoutfifo, the manual update is sufficient. Clean up diagnostics. Add ahd_flush_qoutfifo() which will run the qoutfifo as well as complete any commands sitting on the sequencer's COMPLETE_SCB lists or the good status FIFO. Use this routine in several places that did similar things in an add-hoc, but incomplete, fashion. A call to this routine was also added to ahd_abort_scbs() to close a race. In ahd_pause_and_flushwork() only return once selections are safely disabled. Flush all completed commands via ahd_flush_qoutfifo(). Remove "Now packetized" diagnostic now that this information is incorperated into the actual negotiation messages that are displayed. When forcing renegotiation, don't clober the current ppr_options. Much of the driver uses this information to determine if we are currently packetized or not. Remove some stray spaces at column 1 in ahd_set_tags. When complaining about getting a host message loop request with no pending messages, print out the SCB_CONTROL register down on the card. Modify the ahd_sent_msg() routine to handle a search for an outgoing identify message. Use this to detect a msg reject on an identify message which typically indicates that the target thought we were packetized. Force a renegotiation in this case. In ahd_search_qinfifo(), wait more effectively for SCB DMA activities to cease. We also disable SCB fetch operations since we are about to change the qinfifo and any fetch in progress will likely be invalidated. In ahd_qinfifo_count(), fix the qinfifo empty case. In ahd_dump_card_state(), print out CCSCBCTL in the correct mode. If we are a narrow controller, don't set the current width to unknown when forcing a future negotiation. This just confuses the code into attempting a wide negotiation on a narrow bus. Add support for task management function completions. Modify ahd_handle_devreset so that it can handle lun resets in addition to target resets. Use ahd_handle_devreset for lun and target reset task management functions. Handle the abort task TMF race case better. We now wait until any current selections are over and then set the TMF back to zero. This should cause the sequencer to ignore the abort TMF completion should it occur. Correct a bug in the illegal phase handler that caused us to drop down to narrow when handling the unexpected command phase case after 3rd party reset of a packetized device. Indicate the features, bugs, and flags set in the softc that are used to control firmware patch download when booting verbose. aic79xx.h: Add coalessing and HS_MAILBOX fields. Add per-softc variables for the stats "daemon". Add a debug option for interrupt coalessing activities. Add two new softc flags: o AHD_UPDATE_PEND_CMDS Run ahd_reset_cmds_pending() on the next unpause. o AHD_RUNNING_QOUTFIFO Used to catch recursion through ahd_run_qoutfifo(). aic79xx.reg: Correct register addresses related to the software timer and the DFDBCTL register. Add constants paramaterizing the software timer. Add scratch ram locations for storing interrupt coalessing tunables. Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2. In at least the REV A, these are writable bits. We make use of that for a swtimer workaround in the sequencer. Since HS_MAILBOX autoclears, provide a sequencer variable to store its contents. Add SEQINT codes for handling task management completions. aic79xx.seq: Correct ignore wide residue processing check for a wide negotiation being in effect. We must be in the SCSI register window in order to access the negotiation table. Use the software timer and a commands completed count to implement interrupt coalessing. The command complete is deferred until either the maximum command threshold or a the expiration of a command deferral timer. If we have more SCBs to complete to the host (sitting in COMPLETE_SCB lists), always try to coaless them up to our coalessing limit. If coalessing is enabled, but we have fewer commands oustanting than the host's min coalessing limit, complete the command immediately. Add code to track the number of commands outstanding. Commands are outstanding from the time they are placed into the execution queue until the DMA to post completion is setup. Add a workaround for intvec_2 interrupts on the H2A4. In H2A4, the mode pointer is not saved for intvec2, but is restored on iret. This can lead to the restoration of a bogus mode ptr. Manually clear the intmask bits and do a normal return to compensate. We use intvec_2 to track interrupt coalessing timeouts. Since we cannot disable the swtimer's countdown, simply mask its interrupt once we no longer care about it firing. In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime we are notified of an HS_MAILBOX update via the HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a local copy of persistant portions of the HS_MAILBOX as the mailbox auto-clears on any read. Move the test for the cfg4istat interrupt up an instruction to hopefully close a race between the next outgoing selection and our disabling of selections. Add a missing ret to the last instruction in load_overrun_buf. Add notifications to the host of task management completions as well as the completions for commands that completed successfully before their corresponding TMF could be sent. Hold a critical section during select-out processing until we have a fully identified connection. This removes a race condition with the legacy abort handler. Correct a few spelling errors in some comments. aic79xx_inline.h: Call ahd_reset_cmds_pending() in ahd_unpause if required. Update cmdcmplt interrupt statistics in our interrupt handler. Allow callers to ahd_send_scb() to set the task management function. aic79xx_pci.c: Disable SERR and pause the controller prior to performing our mmapped I/O test. The U320 controllers do not support "auto-access-pause". aic79xx_osm.c: Set the task management function now that ahd_send_scb() doesn't do it for us. We also perform a lun reset in response to BDR requests to packetized devices.
2003-01-20 20:17:35 +00:00
ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS);
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
Last minute fixes to ahc and ahd: ahd_pci.c: Retrieve the allow_memio hint from the resource manager to determine whether or not to try PCI MEMIO. aic79xx_osm.h: aic7xxx_osm.h: Don't wrongly abuse the callout_reset() interface when trying to abuse timeouts generated from the CAM layer. This fixes the console freeze and lost timeout problem that many have reported, especially on SMP systems. aic79xx_pci.c aic7xxx_pci.c Rewrite the MEMIO test routine to prevent certain broken chipsets from trying to burst multiple DWORDs to the registers. Also make the routine better detect byte merging by the host bridge and deal with it. aic79xx.reg: Correct an incorrect register definition. Approved by: re (rwatson, jhb)
2002-12-04 22:51:29 +00:00
return (error);
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
}
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
/*
* Check the external port logic for a serial eeprom
* and termination/cable detection contrls.
*/
static int
ahd_check_extport(struct ahd_softc *ahd)
{
Correct spelling errors. Switch to handling bad SCSI status as a sequencer interrupt instead of having the kernel proccess these failures via the completion queue. This is done because: o The old scheme required us to pause the sequencer and clear critical sections for each SCB. It seems that these pause actions, if coincident with a sequencer FIFO interrupt, would result in a FIFO interrupt getting lost or directing to the wrong FIFO. This caused hangs when the driver was stressed under high "queue full" loads. o The completion code assumed that it was always called with the sequencer running. This may not be the case in timeout processing where completions occur manually via ahd_pause_and_flushwork(). o With this scheme, the extra expense of clearing critical sections is avoided since the sequencer will only self pause once all pending selections have cleared and it is not in a critical section. aic79xx.c Add code to handle the new BAD_SCB_STATUS sequencer interrupt code. This just redirects the SCB through the already existing ahd_complete_scb() code path. Remove code in ahd_handle_scsi_status() that paused the sequencer, made sure that no selections where pending, and cleared critical sections. Bad status SCBs are now only processed when all of these conditions are true. aic79xx.reg: Add the BAD_SCB_STATUS sequencer interrupt code. aic79xx.seq: When completing an SCB upload to the host, if we are doing this because the SCB contains non-zero SCSI status, defer completing the SCB until there are no pending selection events. When completing these SCBs, use the new BAD_SCB_STATUS sequencer interrupt. For all other uploaded SCBs (currently only for underruns), the SCB is completed via the normal done queue. Additionally, keep the SCB that is currently being uploaded on the COMPLETE_DMA_SCB list until the dma is completed, not just until the DMA is started. This ensures that the DMA is restarted properly should the host disable the DMA transfer for some reason. In our RevA workaround for Maxtor drives, guard against the host pausing us while trying to pause I/O until the first data-valid REQ by clearing the current snapshot so that we can tell if the transfer has completed prior to us noticing the REQINIT status. In cfg4data_intr, shave off an instruction before getting the data path running by adding an entrypoint to the overrun handler to also increment the FIFO use count. In the overrun handler, be sure to clear our LONGJMP address in both exit paths. Perform a few sequencer optimizations. aic79xx.c: Print the full path from the SCB when a packetized status overrun occurs. Remove references to LONGJMP_SCB which is being removed from firmware usage. Print the new SCB_FIFO_USE_COUNT field in the per-SCB section of ahd_dump_card_state(). The SCB_TAG field is now re-used by the sequencer, so it no longer makes sense to reference this field in the kernel driver. aic79xx.h: Re-arrange fields in the hardware SCB from largest size type to smallest. This makes it easier to move fields without changing field alignment. The hardware scb tag field is now down near the "spare" portion of the SCB to facilitate reuse by the sequencer. aic79xx.reg: Remove LONGJMP_ADDR. Rearrange SCB fields to match aic79xx.h. Add SCB_FIFO_USE_COUNT as the first byte of the SCB_TAG field. aic79xx.seq: Add a per-SCB "Fifos in use count" field and use it to determine when it is safe (all data posted) to deliver status back to the host. The old method involved polling one or both FIFOs to verify that the current task did not have pending data. This makes running down the GSFIFO very cheap, so we will empty the GSFIFO in one idle loop pass in all cases. Use this simplification of the completion process to prune down the data FIFO teardown sequencer for packetized transfers. Much more code is now shared between the data residual and transfer complete cases. Correct some issues in the packetized status handler. It used to be possible to CLRCHN our FIFO before status had fully transferred to the host. We also failed to handle NONPACKREQ phases that could occur should a CRC error occur during transmission of the status data packet. Correct a few big endian issues: aic79xx.c: aic79xx_inline.h: aic79xx_pci.c: aic79xx_osm.c: o Always get the SCB's tag via the SCB_GET_TAG acccessor o Add missing use of byte swapping macros when touching hscb fields. o Don't double swap SEEPROM data when it is printed. Correct a big-endian bug. We cannot assign a o When assigning a 32bit LE variable to a 64bit LE variable, we must be explict about how the words of the 64bit LE variable are initialized. Cast to (uint32_t*) to do this. aic79xx.c: In ahd_clear_critical_section(), hit CRLSCSIINT after restoring the interrupt masks to avoid what appears to be a glitch on SCSIINT. Any real SCSIINT status will be persistent and will immidiately reset SCSIINT. This clear should only get rid of spurious SCSIINTs. This glitch was the cause of the "Unexpected PKT busfree" status that occurred under high queue full loads Call ahd_fini_scbdata() after shutdown so that any ahd_chip_init() routine that might access SCB data will not access free'd memory. Reset the bus on an IOERR since the chip doesn't seem to reset to the new voltage level without this. Change offset calculation for scatter gather maps so that the calculation is correct if an integral multiple of sg lists does not fit in the allocation size. Adjust bus dma tag for data buffers based on 39BIT addressing flag in our softc. Use the QFREEZE count to simplify ahd_pause_and_flushworkd(). We can thus rely on the sequencer eventually clearing ENSELO. In ahd_abort_scbs(), fix a bug that could potentially corrupt sequencer state. The saved SCB was being restored in the SCSI mode instead of the saved mode. It turns out that the SCB did not need to be saved at all as the scbptr is already restored by all subroutines called during this function that modify that register. aic79xx.c: aic79xx.h: aic79xx_pci.c: Add support for parsing the seeprom vital product data. The VPD data are currently unused. aic79xx.h: aic79xx.seq: aic79xx_pci.c: Add a firmware workaround to make the LED blink brighter during packetized operations on the H2A. aic79xx_inline.h: The host does not use timer interrupts, so don't gate our decision on whether or not to unpause the sequencer on whether or not a timer interrupt is pending.
2003-05-04 00:20:07 +00:00
struct vpd_config vpd;
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
struct seeprom_config *sc;
u_int adapter_control;
int have_seeprom;
int error;
sc = ahd->seep_config;
have_seeprom = ahd_acquire_seeprom(ahd);
if (have_seeprom) {
u_int start_addr;
Correct spelling errors. Switch to handling bad SCSI status as a sequencer interrupt instead of having the kernel proccess these failures via the completion queue. This is done because: o The old scheme required us to pause the sequencer and clear critical sections for each SCB. It seems that these pause actions, if coincident with a sequencer FIFO interrupt, would result in a FIFO interrupt getting lost or directing to the wrong FIFO. This caused hangs when the driver was stressed under high "queue full" loads. o The completion code assumed that it was always called with the sequencer running. This may not be the case in timeout processing where completions occur manually via ahd_pause_and_flushwork(). o With this scheme, the extra expense of clearing critical sections is avoided since the sequencer will only self pause once all pending selections have cleared and it is not in a critical section. aic79xx.c Add code to handle the new BAD_SCB_STATUS sequencer interrupt code. This just redirects the SCB through the already existing ahd_complete_scb() code path. Remove code in ahd_handle_scsi_status() that paused the sequencer, made sure that no selections where pending, and cleared critical sections. Bad status SCBs are now only processed when all of these conditions are true. aic79xx.reg: Add the BAD_SCB_STATUS sequencer interrupt code. aic79xx.seq: When completing an SCB upload to the host, if we are doing this because the SCB contains non-zero SCSI status, defer completing the SCB until there are no pending selection events. When completing these SCBs, use the new BAD_SCB_STATUS sequencer interrupt. For all other uploaded SCBs (currently only for underruns), the SCB is completed via the normal done queue. Additionally, keep the SCB that is currently being uploaded on the COMPLETE_DMA_SCB list until the dma is completed, not just until the DMA is started. This ensures that the DMA is restarted properly should the host disable the DMA transfer for some reason. In our RevA workaround for Maxtor drives, guard against the host pausing us while trying to pause I/O until the first data-valid REQ by clearing the current snapshot so that we can tell if the transfer has completed prior to us noticing the REQINIT status. In cfg4data_intr, shave off an instruction before getting the data path running by adding an entrypoint to the overrun handler to also increment the FIFO use count. In the overrun handler, be sure to clear our LONGJMP address in both exit paths. Perform a few sequencer optimizations. aic79xx.c: Print the full path from the SCB when a packetized status overrun occurs. Remove references to LONGJMP_SCB which is being removed from firmware usage. Print the new SCB_FIFO_USE_COUNT field in the per-SCB section of ahd_dump_card_state(). The SCB_TAG field is now re-used by the sequencer, so it no longer makes sense to reference this field in the kernel driver. aic79xx.h: Re-arrange fields in the hardware SCB from largest size type to smallest. This makes it easier to move fields without changing field alignment. The hardware scb tag field is now down near the "spare" portion of the SCB to facilitate reuse by the sequencer. aic79xx.reg: Remove LONGJMP_ADDR. Rearrange SCB fields to match aic79xx.h. Add SCB_FIFO_USE_COUNT as the first byte of the SCB_TAG field. aic79xx.seq: Add a per-SCB "Fifos in use count" field and use it to determine when it is safe (all data posted) to deliver status back to the host. The old method involved polling one or both FIFOs to verify that the current task did not have pending data. This makes running down the GSFIFO very cheap, so we will empty the GSFIFO in one idle loop pass in all cases. Use this simplification of the completion process to prune down the data FIFO teardown sequencer for packetized transfers. Much more code is now shared between the data residual and transfer complete cases. Correct some issues in the packetized status handler. It used to be possible to CLRCHN our FIFO before status had fully transferred to the host. We also failed to handle NONPACKREQ phases that could occur should a CRC error occur during transmission of the status data packet. Correct a few big endian issues: aic79xx.c: aic79xx_inline.h: aic79xx_pci.c: aic79xx_osm.c: o Always get the SCB's tag via the SCB_GET_TAG acccessor o Add missing use of byte swapping macros when touching hscb fields. o Don't double swap SEEPROM data when it is printed. Correct a big-endian bug. We cannot assign a o When assigning a 32bit LE variable to a 64bit LE variable, we must be explict about how the words of the 64bit LE variable are initialized. Cast to (uint32_t*) to do this. aic79xx.c: In ahd_clear_critical_section(), hit CRLSCSIINT after restoring the interrupt masks to avoid what appears to be a glitch on SCSIINT. Any real SCSIINT status will be persistent and will immidiately reset SCSIINT. This clear should only get rid of spurious SCSIINTs. This glitch was the cause of the "Unexpected PKT busfree" status that occurred under high queue full loads Call ahd_fini_scbdata() after shutdown so that any ahd_chip_init() routine that might access SCB data will not access free'd memory. Reset the bus on an IOERR since the chip doesn't seem to reset to the new voltage level without this. Change offset calculation for scatter gather maps so that the calculation is correct if an integral multiple of sg lists does not fit in the allocation size. Adjust bus dma tag for data buffers based on 39BIT addressing flag in our softc. Use the QFREEZE count to simplify ahd_pause_and_flushworkd(). We can thus rely on the sequencer eventually clearing ENSELO. In ahd_abort_scbs(), fix a bug that could potentially corrupt sequencer state. The saved SCB was being restored in the SCSI mode instead of the saved mode. It turns out that the SCB did not need to be saved at all as the scbptr is already restored by all subroutines called during this function that modify that register. aic79xx.c: aic79xx.h: aic79xx_pci.c: Add support for parsing the seeprom vital product data. The VPD data are currently unused. aic79xx.h: aic79xx.seq: aic79xx_pci.c: Add a firmware workaround to make the LED blink brighter during packetized operations on the H2A. aic79xx_inline.h: The host does not use timer interrupts, so don't gate our decision on whether or not to unpause the sequencer on whether or not a timer interrupt is pending.
2003-05-04 00:20:07 +00:00
/*
* Fetch VPD for this function and parse it.
*/
if (bootverbose)
printf("%s: Reading VPD from SEEPROM...",
ahd_name(ahd));
/* Address is always in units of 16bit words */
start_addr = ((2 * sizeof(*sc))
+ (sizeof(vpd) * (ahd->channel - 'A'))) / 2;
error = ahd_read_seeprom(ahd, (uint16_t *)&vpd,
start_addr, sizeof(vpd)/2,
/*bytestream*/TRUE);
if (error == 0)
error = ahd_parse_vpddata(ahd, &vpd);
if (bootverbose)
printf("%s: VPD parsing %s\n",
ahd_name(ahd),
error == 0 ? "successful" : "failed");
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
if (bootverbose)
printf("%s: Reading SEEPROM...", ahd_name(ahd));
/* Address is always in units of 16bit words */
start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A');
error = ahd_read_seeprom(ahd, (uint16_t *)sc,
Correct spelling errors. Switch to handling bad SCSI status as a sequencer interrupt instead of having the kernel proccess these failures via the completion queue. This is done because: o The old scheme required us to pause the sequencer and clear critical sections for each SCB. It seems that these pause actions, if coincident with a sequencer FIFO interrupt, would result in a FIFO interrupt getting lost or directing to the wrong FIFO. This caused hangs when the driver was stressed under high "queue full" loads. o The completion code assumed that it was always called with the sequencer running. This may not be the case in timeout processing where completions occur manually via ahd_pause_and_flushwork(). o With this scheme, the extra expense of clearing critical sections is avoided since the sequencer will only self pause once all pending selections have cleared and it is not in a critical section. aic79xx.c Add code to handle the new BAD_SCB_STATUS sequencer interrupt code. This just redirects the SCB through the already existing ahd_complete_scb() code path. Remove code in ahd_handle_scsi_status() that paused the sequencer, made sure that no selections where pending, and cleared critical sections. Bad status SCBs are now only processed when all of these conditions are true. aic79xx.reg: Add the BAD_SCB_STATUS sequencer interrupt code. aic79xx.seq: When completing an SCB upload to the host, if we are doing this because the SCB contains non-zero SCSI status, defer completing the SCB until there are no pending selection events. When completing these SCBs, use the new BAD_SCB_STATUS sequencer interrupt. For all other uploaded SCBs (currently only for underruns), the SCB is completed via the normal done queue. Additionally, keep the SCB that is currently being uploaded on the COMPLETE_DMA_SCB list until the dma is completed, not just until the DMA is started. This ensures that the DMA is restarted properly should the host disable the DMA transfer for some reason. In our RevA workaround for Maxtor drives, guard against the host pausing us while trying to pause I/O until the first data-valid REQ by clearing the current snapshot so that we can tell if the transfer has completed prior to us noticing the REQINIT status. In cfg4data_intr, shave off an instruction before getting the data path running by adding an entrypoint to the overrun handler to also increment the FIFO use count. In the overrun handler, be sure to clear our LONGJMP address in both exit paths. Perform a few sequencer optimizations. aic79xx.c: Print the full path from the SCB when a packetized status overrun occurs. Remove references to LONGJMP_SCB which is being removed from firmware usage. Print the new SCB_FIFO_USE_COUNT field in the per-SCB section of ahd_dump_card_state(). The SCB_TAG field is now re-used by the sequencer, so it no longer makes sense to reference this field in the kernel driver. aic79xx.h: Re-arrange fields in the hardware SCB from largest size type to smallest. This makes it easier to move fields without changing field alignment. The hardware scb tag field is now down near the "spare" portion of the SCB to facilitate reuse by the sequencer. aic79xx.reg: Remove LONGJMP_ADDR. Rearrange SCB fields to match aic79xx.h. Add SCB_FIFO_USE_COUNT as the first byte of the SCB_TAG field. aic79xx.seq: Add a per-SCB "Fifos in use count" field and use it to determine when it is safe (all data posted) to deliver status back to the host. The old method involved polling one or both FIFOs to verify that the current task did not have pending data. This makes running down the GSFIFO very cheap, so we will empty the GSFIFO in one idle loop pass in all cases. Use this simplification of the completion process to prune down the data FIFO teardown sequencer for packetized transfers. Much more code is now shared between the data residual and transfer complete cases. Correct some issues in the packetized status handler. It used to be possible to CLRCHN our FIFO before status had fully transferred to the host. We also failed to handle NONPACKREQ phases that could occur should a CRC error occur during transmission of the status data packet. Correct a few big endian issues: aic79xx.c: aic79xx_inline.h: aic79xx_pci.c: aic79xx_osm.c: o Always get the SCB's tag via the SCB_GET_TAG acccessor o Add missing use of byte swapping macros when touching hscb fields. o Don't double swap SEEPROM data when it is printed. Correct a big-endian bug. We cannot assign a o When assigning a 32bit LE variable to a 64bit LE variable, we must be explict about how the words of the 64bit LE variable are initialized. Cast to (uint32_t*) to do this. aic79xx.c: In ahd_clear_critical_section(), hit CRLSCSIINT after restoring the interrupt masks to avoid what appears to be a glitch on SCSIINT. Any real SCSIINT status will be persistent and will immidiately reset SCSIINT. This clear should only get rid of spurious SCSIINTs. This glitch was the cause of the "Unexpected PKT busfree" status that occurred under high queue full loads Call ahd_fini_scbdata() after shutdown so that any ahd_chip_init() routine that might access SCB data will not access free'd memory. Reset the bus on an IOERR since the chip doesn't seem to reset to the new voltage level without this. Change offset calculation for scatter gather maps so that the calculation is correct if an integral multiple of sg lists does not fit in the allocation size. Adjust bus dma tag for data buffers based on 39BIT addressing flag in our softc. Use the QFREEZE count to simplify ahd_pause_and_flushworkd(). We can thus rely on the sequencer eventually clearing ENSELO. In ahd_abort_scbs(), fix a bug that could potentially corrupt sequencer state. The saved SCB was being restored in the SCSI mode instead of the saved mode. It turns out that the SCB did not need to be saved at all as the scbptr is already restored by all subroutines called during this function that modify that register. aic79xx.c: aic79xx.h: aic79xx_pci.c: Add support for parsing the seeprom vital product data. The VPD data are currently unused. aic79xx.h: aic79xx.seq: aic79xx_pci.c: Add a firmware workaround to make the LED blink brighter during packetized operations on the H2A. aic79xx_inline.h: The host does not use timer interrupts, so don't gate our decision on whether or not to unpause the sequencer on whether or not a timer interrupt is pending.
2003-05-04 00:20:07 +00:00
start_addr, sizeof(*sc)/2,
/*bytestream*/FALSE);
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
if (error != 0) {
printf("Unable to read SEEPROM\n");
have_seeprom = 0;
} else {
have_seeprom = ahd_verify_cksum(sc);
if (bootverbose) {
if (have_seeprom == 0)
printf ("checksum error\n");
else
printf ("done.\n");
}
}
ahd_release_seeprom(ahd);
}
if (!have_seeprom) {
u_int nvram_scb;
/*
* Pull scratch ram settings and treat them as
* if they are the contents of an seeprom if
* the 'ADPT', 'BIOS', or 'ASPI' signature is found
* in SCB 0xFF. We manually compose the data as 16bit
* values to avoid endian issues.
*/
ahd_set_scbptr(ahd, 0xFF);
nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET);
if (nvram_scb != 0xFF
&& ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
&& ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D'
&& ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
&& ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T')
|| (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B'
&& ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I'
&& ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O'
&& ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S')
|| (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
&& ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S'
&& ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
&& ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) {
uint16_t *sc_data;
int i;
ahd_set_scbptr(ahd, nvram_scb);
sc_data = (uint16_t *)sc;
for (i = 0; i < 64; i += 2)
*sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i);
have_seeprom = ahd_verify_cksum(sc);
if (have_seeprom)
ahd->flags |= AHD_SCB_CONFIG_USED;
}
}
#if AHD_DEBUG
if (have_seeprom != 0
&& (ahd_debug & AHD_DUMP_SEEPROM) != 0) {
Correct spelling errors. Switch to handling bad SCSI status as a sequencer interrupt instead of having the kernel proccess these failures via the completion queue. This is done because: o The old scheme required us to pause the sequencer and clear critical sections for each SCB. It seems that these pause actions, if coincident with a sequencer FIFO interrupt, would result in a FIFO interrupt getting lost or directing to the wrong FIFO. This caused hangs when the driver was stressed under high "queue full" loads. o The completion code assumed that it was always called with the sequencer running. This may not be the case in timeout processing where completions occur manually via ahd_pause_and_flushwork(). o With this scheme, the extra expense of clearing critical sections is avoided since the sequencer will only self pause once all pending selections have cleared and it is not in a critical section. aic79xx.c Add code to handle the new BAD_SCB_STATUS sequencer interrupt code. This just redirects the SCB through the already existing ahd_complete_scb() code path. Remove code in ahd_handle_scsi_status() that paused the sequencer, made sure that no selections where pending, and cleared critical sections. Bad status SCBs are now only processed when all of these conditions are true. aic79xx.reg: Add the BAD_SCB_STATUS sequencer interrupt code. aic79xx.seq: When completing an SCB upload to the host, if we are doing this because the SCB contains non-zero SCSI status, defer completing the SCB until there are no pending selection events. When completing these SCBs, use the new BAD_SCB_STATUS sequencer interrupt. For all other uploaded SCBs (currently only for underruns), the SCB is completed via the normal done queue. Additionally, keep the SCB that is currently being uploaded on the COMPLETE_DMA_SCB list until the dma is completed, not just until the DMA is started. This ensures that the DMA is restarted properly should the host disable the DMA transfer for some reason. In our RevA workaround for Maxtor drives, guard against the host pausing us while trying to pause I/O until the first data-valid REQ by clearing the current snapshot so that we can tell if the transfer has completed prior to us noticing the REQINIT status. In cfg4data_intr, shave off an instruction before getting the data path running by adding an entrypoint to the overrun handler to also increment the FIFO use count. In the overrun handler, be sure to clear our LONGJMP address in both exit paths. Perform a few sequencer optimizations. aic79xx.c: Print the full path from the SCB when a packetized status overrun occurs. Remove references to LONGJMP_SCB which is being removed from firmware usage. Print the new SCB_FIFO_USE_COUNT field in the per-SCB section of ahd_dump_card_state(). The SCB_TAG field is now re-used by the sequencer, so it no longer makes sense to reference this field in the kernel driver. aic79xx.h: Re-arrange fields in the hardware SCB from largest size type to smallest. This makes it easier to move fields without changing field alignment. The hardware scb tag field is now down near the "spare" portion of the SCB to facilitate reuse by the sequencer. aic79xx.reg: Remove LONGJMP_ADDR. Rearrange SCB fields to match aic79xx.h. Add SCB_FIFO_USE_COUNT as the first byte of the SCB_TAG field. aic79xx.seq: Add a per-SCB "Fifos in use count" field and use it to determine when it is safe (all data posted) to deliver status back to the host. The old method involved polling one or both FIFOs to verify that the current task did not have pending data. This makes running down the GSFIFO very cheap, so we will empty the GSFIFO in one idle loop pass in all cases. Use this simplification of the completion process to prune down the data FIFO teardown sequencer for packetized transfers. Much more code is now shared between the data residual and transfer complete cases. Correct some issues in the packetized status handler. It used to be possible to CLRCHN our FIFO before status had fully transferred to the host. We also failed to handle NONPACKREQ phases that could occur should a CRC error occur during transmission of the status data packet. Correct a few big endian issues: aic79xx.c: aic79xx_inline.h: aic79xx_pci.c: aic79xx_osm.c: o Always get the SCB's tag via the SCB_GET_TAG acccessor o Add missing use of byte swapping macros when touching hscb fields. o Don't double swap SEEPROM data when it is printed. Correct a big-endian bug. We cannot assign a o When assigning a 32bit LE variable to a 64bit LE variable, we must be explict about how the words of the 64bit LE variable are initialized. Cast to (uint32_t*) to do this. aic79xx.c: In ahd_clear_critical_section(), hit CRLSCSIINT after restoring the interrupt masks to avoid what appears to be a glitch on SCSIINT. Any real SCSIINT status will be persistent and will immidiately reset SCSIINT. This clear should only get rid of spurious SCSIINTs. This glitch was the cause of the "Unexpected PKT busfree" status that occurred under high queue full loads Call ahd_fini_scbdata() after shutdown so that any ahd_chip_init() routine that might access SCB data will not access free'd memory. Reset the bus on an IOERR since the chip doesn't seem to reset to the new voltage level without this. Change offset calculation for scatter gather maps so that the calculation is correct if an integral multiple of sg lists does not fit in the allocation size. Adjust bus dma tag for data buffers based on 39BIT addressing flag in our softc. Use the QFREEZE count to simplify ahd_pause_and_flushworkd(). We can thus rely on the sequencer eventually clearing ENSELO. In ahd_abort_scbs(), fix a bug that could potentially corrupt sequencer state. The saved SCB was being restored in the SCSI mode instead of the saved mode. It turns out that the SCB did not need to be saved at all as the scbptr is already restored by all subroutines called during this function that modify that register. aic79xx.c: aic79xx.h: aic79xx_pci.c: Add support for parsing the seeprom vital product data. The VPD data are currently unused. aic79xx.h: aic79xx.seq: aic79xx_pci.c: Add a firmware workaround to make the LED blink brighter during packetized operations on the H2A. aic79xx_inline.h: The host does not use timer interrupts, so don't gate our decision on whether or not to unpause the sequencer on whether or not a timer interrupt is pending.
2003-05-04 00:20:07 +00:00
uint16_t *sc_data;
int i;
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
printf("%s: Seeprom Contents:", ahd_name(ahd));
Correct spelling errors. Switch to handling bad SCSI status as a sequencer interrupt instead of having the kernel proccess these failures via the completion queue. This is done because: o The old scheme required us to pause the sequencer and clear critical sections for each SCB. It seems that these pause actions, if coincident with a sequencer FIFO interrupt, would result in a FIFO interrupt getting lost or directing to the wrong FIFO. This caused hangs when the driver was stressed under high "queue full" loads. o The completion code assumed that it was always called with the sequencer running. This may not be the case in timeout processing where completions occur manually via ahd_pause_and_flushwork(). o With this scheme, the extra expense of clearing critical sections is avoided since the sequencer will only self pause once all pending selections have cleared and it is not in a critical section. aic79xx.c Add code to handle the new BAD_SCB_STATUS sequencer interrupt code. This just redirects the SCB through the already existing ahd_complete_scb() code path. Remove code in ahd_handle_scsi_status() that paused the sequencer, made sure that no selections where pending, and cleared critical sections. Bad status SCBs are now only processed when all of these conditions are true. aic79xx.reg: Add the BAD_SCB_STATUS sequencer interrupt code. aic79xx.seq: When completing an SCB upload to the host, if we are doing this because the SCB contains non-zero SCSI status, defer completing the SCB until there are no pending selection events. When completing these SCBs, use the new BAD_SCB_STATUS sequencer interrupt. For all other uploaded SCBs (currently only for underruns), the SCB is completed via the normal done queue. Additionally, keep the SCB that is currently being uploaded on the COMPLETE_DMA_SCB list until the dma is completed, not just until the DMA is started. This ensures that the DMA is restarted properly should the host disable the DMA transfer for some reason. In our RevA workaround for Maxtor drives, guard against the host pausing us while trying to pause I/O until the first data-valid REQ by clearing the current snapshot so that we can tell if the transfer has completed prior to us noticing the REQINIT status. In cfg4data_intr, shave off an instruction before getting the data path running by adding an entrypoint to the overrun handler to also increment the FIFO use count. In the overrun handler, be sure to clear our LONGJMP address in both exit paths. Perform a few sequencer optimizations. aic79xx.c: Print the full path from the SCB when a packetized status overrun occurs. Remove references to LONGJMP_SCB which is being removed from firmware usage. Print the new SCB_FIFO_USE_COUNT field in the per-SCB section of ahd_dump_card_state(). The SCB_TAG field is now re-used by the sequencer, so it no longer makes sense to reference this field in the kernel driver. aic79xx.h: Re-arrange fields in the hardware SCB from largest size type to smallest. This makes it easier to move fields without changing field alignment. The hardware scb tag field is now down near the "spare" portion of the SCB to facilitate reuse by the sequencer. aic79xx.reg: Remove LONGJMP_ADDR. Rearrange SCB fields to match aic79xx.h. Add SCB_FIFO_USE_COUNT as the first byte of the SCB_TAG field. aic79xx.seq: Add a per-SCB "Fifos in use count" field and use it to determine when it is safe (all data posted) to deliver status back to the host. The old method involved polling one or both FIFOs to verify that the current task did not have pending data. This makes running down the GSFIFO very cheap, so we will empty the GSFIFO in one idle loop pass in all cases. Use this simplification of the completion process to prune down the data FIFO teardown sequencer for packetized transfers. Much more code is now shared between the data residual and transfer complete cases. Correct some issues in the packetized status handler. It used to be possible to CLRCHN our FIFO before status had fully transferred to the host. We also failed to handle NONPACKREQ phases that could occur should a CRC error occur during transmission of the status data packet. Correct a few big endian issues: aic79xx.c: aic79xx_inline.h: aic79xx_pci.c: aic79xx_osm.c: o Always get the SCB's tag via the SCB_GET_TAG acccessor o Add missing use of byte swapping macros when touching hscb fields. o Don't double swap SEEPROM data when it is printed. Correct a big-endian bug. We cannot assign a o When assigning a 32bit LE variable to a 64bit LE variable, we must be explict about how the words of the 64bit LE variable are initialized. Cast to (uint32_t*) to do this. aic79xx.c: In ahd_clear_critical_section(), hit CRLSCSIINT after restoring the interrupt masks to avoid what appears to be a glitch on SCSIINT. Any real SCSIINT status will be persistent and will immidiately reset SCSIINT. This clear should only get rid of spurious SCSIINTs. This glitch was the cause of the "Unexpected PKT busfree" status that occurred under high queue full loads Call ahd_fini_scbdata() after shutdown so that any ahd_chip_init() routine that might access SCB data will not access free'd memory. Reset the bus on an IOERR since the chip doesn't seem to reset to the new voltage level without this. Change offset calculation for scatter gather maps so that the calculation is correct if an integral multiple of sg lists does not fit in the allocation size. Adjust bus dma tag for data buffers based on 39BIT addressing flag in our softc. Use the QFREEZE count to simplify ahd_pause_and_flushworkd(). We can thus rely on the sequencer eventually clearing ENSELO. In ahd_abort_scbs(), fix a bug that could potentially corrupt sequencer state. The saved SCB was being restored in the SCSI mode instead of the saved mode. It turns out that the SCB did not need to be saved at all as the scbptr is already restored by all subroutines called during this function that modify that register. aic79xx.c: aic79xx.h: aic79xx_pci.c: Add support for parsing the seeprom vital product data. The VPD data are currently unused. aic79xx.h: aic79xx.seq: aic79xx_pci.c: Add a firmware workaround to make the LED blink brighter during packetized operations on the H2A. aic79xx_inline.h: The host does not use timer interrupts, so don't gate our decision on whether or not to unpause the sequencer on whether or not a timer interrupt is pending.
2003-05-04 00:20:07 +00:00
sc_data = (uint16_t *)sc;
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
for (i = 0; i < (sizeof(*sc)); i += 2)
Correct spelling errors. Switch to handling bad SCSI status as a sequencer interrupt instead of having the kernel proccess these failures via the completion queue. This is done because: o The old scheme required us to pause the sequencer and clear critical sections for each SCB. It seems that these pause actions, if coincident with a sequencer FIFO interrupt, would result in a FIFO interrupt getting lost or directing to the wrong FIFO. This caused hangs when the driver was stressed under high "queue full" loads. o The completion code assumed that it was always called with the sequencer running. This may not be the case in timeout processing where completions occur manually via ahd_pause_and_flushwork(). o With this scheme, the extra expense of clearing critical sections is avoided since the sequencer will only self pause once all pending selections have cleared and it is not in a critical section. aic79xx.c Add code to handle the new BAD_SCB_STATUS sequencer interrupt code. This just redirects the SCB through the already existing ahd_complete_scb() code path. Remove code in ahd_handle_scsi_status() that paused the sequencer, made sure that no selections where pending, and cleared critical sections. Bad status SCBs are now only processed when all of these conditions are true. aic79xx.reg: Add the BAD_SCB_STATUS sequencer interrupt code. aic79xx.seq: When completing an SCB upload to the host, if we are doing this because the SCB contains non-zero SCSI status, defer completing the SCB until there are no pending selection events. When completing these SCBs, use the new BAD_SCB_STATUS sequencer interrupt. For all other uploaded SCBs (currently only for underruns), the SCB is completed via the normal done queue. Additionally, keep the SCB that is currently being uploaded on the COMPLETE_DMA_SCB list until the dma is completed, not just until the DMA is started. This ensures that the DMA is restarted properly should the host disable the DMA transfer for some reason. In our RevA workaround for Maxtor drives, guard against the host pausing us while trying to pause I/O until the first data-valid REQ by clearing the current snapshot so that we can tell if the transfer has completed prior to us noticing the REQINIT status. In cfg4data_intr, shave off an instruction before getting the data path running by adding an entrypoint to the overrun handler to also increment the FIFO use count. In the overrun handler, be sure to clear our LONGJMP address in both exit paths. Perform a few sequencer optimizations. aic79xx.c: Print the full path from the SCB when a packetized status overrun occurs. Remove references to LONGJMP_SCB which is being removed from firmware usage. Print the new SCB_FIFO_USE_COUNT field in the per-SCB section of ahd_dump_card_state(). The SCB_TAG field is now re-used by the sequencer, so it no longer makes sense to reference this field in the kernel driver. aic79xx.h: Re-arrange fields in the hardware SCB from largest size type to smallest. This makes it easier to move fields without changing field alignment. The hardware scb tag field is now down near the "spare" portion of the SCB to facilitate reuse by the sequencer. aic79xx.reg: Remove LONGJMP_ADDR. Rearrange SCB fields to match aic79xx.h. Add SCB_FIFO_USE_COUNT as the first byte of the SCB_TAG field. aic79xx.seq: Add a per-SCB "Fifos in use count" field and use it to determine when it is safe (all data posted) to deliver status back to the host. The old method involved polling one or both FIFOs to verify that the current task did not have pending data. This makes running down the GSFIFO very cheap, so we will empty the GSFIFO in one idle loop pass in all cases. Use this simplification of the completion process to prune down the data FIFO teardown sequencer for packetized transfers. Much more code is now shared between the data residual and transfer complete cases. Correct some issues in the packetized status handler. It used to be possible to CLRCHN our FIFO before status had fully transferred to the host. We also failed to handle NONPACKREQ phases that could occur should a CRC error occur during transmission of the status data packet. Correct a few big endian issues: aic79xx.c: aic79xx_inline.h: aic79xx_pci.c: aic79xx_osm.c: o Always get the SCB's tag via the SCB_GET_TAG acccessor o Add missing use of byte swapping macros when touching hscb fields. o Don't double swap SEEPROM data when it is printed. Correct a big-endian bug. We cannot assign a o When assigning a 32bit LE variable to a 64bit LE variable, we must be explict about how the words of the 64bit LE variable are initialized. Cast to (uint32_t*) to do this. aic79xx.c: In ahd_clear_critical_section(), hit CRLSCSIINT after restoring the interrupt masks to avoid what appears to be a glitch on SCSIINT. Any real SCSIINT status will be persistent and will immidiately reset SCSIINT. This clear should only get rid of spurious SCSIINTs. This glitch was the cause of the "Unexpected PKT busfree" status that occurred under high queue full loads Call ahd_fini_scbdata() after shutdown so that any ahd_chip_init() routine that might access SCB data will not access free'd memory. Reset the bus on an IOERR since the chip doesn't seem to reset to the new voltage level without this. Change offset calculation for scatter gather maps so that the calculation is correct if an integral multiple of sg lists does not fit in the allocation size. Adjust bus dma tag for data buffers based on 39BIT addressing flag in our softc. Use the QFREEZE count to simplify ahd_pause_and_flushworkd(). We can thus rely on the sequencer eventually clearing ENSELO. In ahd_abort_scbs(), fix a bug that could potentially corrupt sequencer state. The saved SCB was being restored in the SCSI mode instead of the saved mode. It turns out that the SCB did not need to be saved at all as the scbptr is already restored by all subroutines called during this function that modify that register. aic79xx.c: aic79xx.h: aic79xx_pci.c: Add support for parsing the seeprom vital product data. The VPD data are currently unused. aic79xx.h: aic79xx.seq: aic79xx_pci.c: Add a firmware workaround to make the LED blink brighter during packetized operations on the H2A. aic79xx_inline.h: The host does not use timer interrupts, so don't gate our decision on whether or not to unpause the sequencer on whether or not a timer interrupt is pending.
2003-05-04 00:20:07 +00:00
printf("\n\t0x%.4x", sc_data[i]);
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
printf("\n");
}
#endif
if (!have_seeprom) {
if (bootverbose)
printf("%s: No SEEPROM available.\n", ahd_name(ahd));
ahd->flags |= AHD_USEDEFAULTS;
error = ahd_default_config(ahd);
adapter_control = CFAUTOTERM|CFSEAUTOTERM;
free(ahd->seep_config, M_DEVBUF);
ahd->seep_config = NULL;
} else {
error = ahd_parse_cfgdata(ahd, sc);
adapter_control = sc->adapter_control;
}
if (error != 0)
return (error);
ahd_configure_termination(ahd, adapter_control);
return (0);
}
static void
ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control)
{
int error;
u_int sxfrctl1;
uint8_t termctl;
uint32_t devconfig;
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
devconfig &= ~STPWLEVEL;
Identify new controllers and the aic7901A. Move interrupt enable to the OSM. Remove some debugging messages. Remove chip bug workarounds for non-production asics.
2002-08-31 06:52:27 +00:00
if ((ahd->flags & AHD_STPWLEVEL_A) != 0)
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
devconfig |= STPWLEVEL;
Identify new controllers and the aic7901A. Move interrupt enable to the OSM. Remove some debugging messages. Remove chip bug workarounds for non-production asics.
2002-08-31 06:52:27 +00:00
if (bootverbose)
printf("%s: STPWLEVEL is %s\n",
ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off");
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
aic_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
/* Make sure current sensing is off. */
if ((ahd->flags & AHD_CURRENT_SENSING) != 0) {
(void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
}
/*
* Read to sense. Write to set.
*/
error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl);
if ((adapter_control & CFAUTOTERM) == 0) {
if (bootverbose)
printf("%s: Manual Primary Termination\n",
ahd_name(ahd));
termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH);
if ((adapter_control & CFSTERM) != 0)
termctl |= FLX_TERMCTL_ENPRILOW;
if ((adapter_control & CFWSTERM) != 0)
termctl |= FLX_TERMCTL_ENPRIHIGH;
} else if (error != 0) {
printf("%s: Primary Auto-Term Sensing failed! "
"Using Defaults.\n", ahd_name(ahd));
termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH;
}
if ((adapter_control & CFSEAUTOTERM) == 0) {
if (bootverbose)
printf("%s: Manual Secondary Termination\n",
ahd_name(ahd));
termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH);
if ((adapter_control & CFSELOWTERM) != 0)
termctl |= FLX_TERMCTL_ENSECLOW;
if ((adapter_control & CFSEHIGHTERM) != 0)
termctl |= FLX_TERMCTL_ENSECHIGH;
} else if (error != 0) {
printf("%s: Secondary Auto-Term Sensing failed! "
"Using Defaults.\n", ahd_name(ahd));
termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH;
}
/*
* Now set the termination based on what we found.
*/
sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN;
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
ahd->flags &= ~AHD_TERM_ENB_A;
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) {
ahd->flags |= AHD_TERM_ENB_A;
sxfrctl1 |= STPWEN;
}
/* Must set the latch once in order to be effective. */
ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
ahd_outb(ahd, SXFRCTL1, sxfrctl1);
error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl);
if (error != 0) {
printf("%s: Unable to set termination settings!\n",
ahd_name(ahd));
} else if (bootverbose) {
printf("%s: Primary High byte termination %sabled\n",
ahd_name(ahd),
(termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis");
printf("%s: Primary Low byte termination %sabled\n",
ahd_name(ahd),
(termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis");
printf("%s: Secondary High byte termination %sabled\n",
ahd_name(ahd),
(termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis");
printf("%s: Secondary Low byte termination %sabled\n",
ahd_name(ahd),
(termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis");
}
return;
}
#define DPE 0x80
#define SSE 0x40
#define RMA 0x20
#define RTA 0x10
#define STA 0x08
#define DPR 0x01
static const char *split_status_source[] =
{
"DFF0",
"DFF1",
"OVLY",
"CMC",
};
static const char *pci_status_source[] =
{
"DFF0",
"DFF1",
"SG",
"CMC",
"OVLY",
"NONE",
"MSI",
"TARG"
};
static const char *split_status_strings[] =
{
aic79xx.c: Clear the LQICRC_NLQ status should it pop up after we have already handled the SCSIPERR. During some streaming operations this status can be delayed until the stream ends. Without this change, the driver would complain about a "Missing case in ahd_handle_scsiint". In the LQOBUSFREE handler... Don't return the LQOMGR back to the idle state until after we have cleaned up ENSELO and any status related to this selection. The last thing we need is the LQO manager starting another select-out before we have updated the execution queue. It is not clear whether the LQOMGR would, or would not start a new selection early. Make sure ENSELO is off prior to clearing SELDO by flushing device writes. Move assignment of the next target SCB pointer inside of an if to make the code clearer. The effect is the same. Dump card state in both "Unexpected PKT busfree" paths. In ahd_reset(), set the chip to SCSI mode before reading SXFRCTL1. That register only exists in the SCSI mode. Also set the mode explicitly to the SCSI mode after chip reset due to paranoia. Re-arrange code so that SXFRCTL1 is restored as quickly after the chip reset as possible. S/G structurs must be 8byte aligned. Make this official by saying so in our DMA tag. Disable CIO bus stretch on MDFFSTAT if SHVALID is about to come true. This can cause a CIO bus lockup if a PCI or PCI-X error occurs while the stretch is occurring - the host cannot service the PCI-X error since the CIO bus is locked out and SHVALID will never resolve. The stretch was added in the Rev B to simplify the wait for SHVALID to resolve, but the code to do this in the open source sequencer is so simple it was never removed. Consistently use MAX_OFFSET for the user max syncrate set from non-volatile storage. This ensures that the offset does not conflict with AH?_OFFSET_UNKNOWN. Have ahd_pause_and_flushwork set the mode to ensure that it has access to the registers it checks. Also modify the checking of intstat so that the check against 0xFF can actually succeed if the INT_PEND mask is something other than 0xFF. Although there are no cardbus U320 controllers, this check may be needed to recover from a hot-plug PCI removal that occurs without informing the driver. Fix a typo. sg_prefetch_cnt -> sg_prefetch_align. This fixes an infinite loop at card initialization if the cacheline size is 0. aic79xx.h: Add AHD_EARLY_REQ_BUG bug flag. Fix spelling errors. Include the CDB's length just after the CDB pointer in the DMA'ed CDB case. Change AH?_OFFSET_UNKNOWN to 0xFF. This is a value that the curr->offset can never be, unlike '0' which we previously used. This fixes code that only checks for a non-zero offset to determine if a sync negotiation is required since it will fire in the unknown case even if the goal is async. aic79xx.reg: Add comments for LQISTAT bits indicating their names in the 7902 data book. We use slightly different and more descriptive names in the firmware. Fix spelling errors. Include the CDB's length just after the CDB pointer in the DMA'ed CDB case. aic79xx.seq: Update comments regarding rundown of the GSFIFO to reflect reality. Fix spelling errors. Since we use an 8byte address and 1 byte length, shorten the size of a block move for the legacy DMA'ed CDB case from 11 to 9 bytes. Remove code that, assuming the abort pending feature worked, would set MK_MESSAGE in the SCB's control byte on completion to catch invalid reselections. Since we don't see interrupts for completed selections, this status update could occur prior to us noticing the SELDO. The "select-out" queue logic will get confused by the MK_MESSAGE bit being set as this is used to catch packatized connections where we select-out with ATN. Since the abort pending feature doesn't work on any released controllers yet, this code was never executed. Add support for the AHD_EARLY_REQ_BUG. Don't ignore persistent REQ assertions just because they were asserted within the bus settle delay window. This allows us to tolerate devices like the GEM318 that violate the SCSI spec. Remove unintentional settnig of SG_CACHE_AVAIL. Writing this bit should have no effect, but who knows... On the Rev A, we must wait for HDMAENACK before loading additional segments to avoid clobbering the address of the first segment in the S/G FIFO. This resolves data-corruption issues with certain IBM (now Hitachi) and Fujitsu U320 drives. Rearrange calc_residual to avoid an extra jmp instruction. On RevA Silicon, if the target returns us to data-out after we have already trained for data-out, it is possible for us to transition the free running clock to data-valid before the required 100ns P1 setup time (8 P1 assertions in fast-160 mode). This will only happen if this L-Q is a continuation of a data transfer for which we have already prefetched data into our FIFO (LQ/Data followed by LQ/Data for the same write transaction). This can cause some target implementations to miss the first few data transfers on the bus. We detect this situation by noticing that this is the first data transfer after an LQ (LQIWORKONLQ true), that the data transfer is a continuation of a transfer already setup in our FIFO (SAVEPTRS interrupt), and that the transaction is a write (DIRECTION set in DFCNTRL). The delay is performed by disabling SCSIEN until we see the first REQ from the target. Only compile in snapshot savepointers handler for RevA silicon where it is enabled. Handle the cfg4icmd packetized interrupt. We just need to load the address and count, start the DMA, and CLRCHN once the transfer is complete. Fix an oversight in the overrun handler for packetized status operations. We need to wait for either CTXTDONE or an overrun when checking for an overrun. The previous code did not wait and thus could decide that no overrun had occurred even though an overrun will occur on the next data-valid req. Add some comment to this section for clarity. Use LAST_SEG_DONE instead of LASTSDONE for testing transfer completion in the packetized status case. LASTSDONE may come up more quickly since it only records completion on the SCSI side, but since LAST_SEG_DONE is used everywhere else (and needs to be), this is less confusing. Add a missing invalidation of the longjmp address in the non-pack handler. This code needs additional review. aic79xx_inline.h: Fix spelling error. aic79xx_osm.c: Set the cdb length for CDBs dma'ed from host memory. Add a comment indicating that, should CAM start supporting cdbs larger than 16bytes, the driver could store the CDB in the status buffer. aic79xx_pci.c: Add a table entry for the 39320A. Added a missing comma to an error string table. Fix spelling errors.
2003-02-27 23:23:16 +00:00
"%s: Received split response in %s.\n",
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
"%s: Received split completion error message in %s\n",
"%s: Receive overrun in %s\n",
"%s: Count not complete in %s\n",
"%s: Split completion data bucket in %s\n",
"%s: Split completion address error in %s\n",
"%s: Split completion byte count error in %s\n",
aic79xx.c: Clear the LQICRC_NLQ status should it pop up after we have already handled the SCSIPERR. During some streaming operations this status can be delayed until the stream ends. Without this change, the driver would complain about a "Missing case in ahd_handle_scsiint". In the LQOBUSFREE handler... Don't return the LQOMGR back to the idle state until after we have cleaned up ENSELO and any status related to this selection. The last thing we need is the LQO manager starting another select-out before we have updated the execution queue. It is not clear whether the LQOMGR would, or would not start a new selection early. Make sure ENSELO is off prior to clearing SELDO by flushing device writes. Move assignment of the next target SCB pointer inside of an if to make the code clearer. The effect is the same. Dump card state in both "Unexpected PKT busfree" paths. In ahd_reset(), set the chip to SCSI mode before reading SXFRCTL1. That register only exists in the SCSI mode. Also set the mode explicitly to the SCSI mode after chip reset due to paranoia. Re-arrange code so that SXFRCTL1 is restored as quickly after the chip reset as possible. S/G structurs must be 8byte aligned. Make this official by saying so in our DMA tag. Disable CIO bus stretch on MDFFSTAT if SHVALID is about to come true. This can cause a CIO bus lockup if a PCI or PCI-X error occurs while the stretch is occurring - the host cannot service the PCI-X error since the CIO bus is locked out and SHVALID will never resolve. The stretch was added in the Rev B to simplify the wait for SHVALID to resolve, but the code to do this in the open source sequencer is so simple it was never removed. Consistently use MAX_OFFSET for the user max syncrate set from non-volatile storage. This ensures that the offset does not conflict with AH?_OFFSET_UNKNOWN. Have ahd_pause_and_flushwork set the mode to ensure that it has access to the registers it checks. Also modify the checking of intstat so that the check against 0xFF can actually succeed if the INT_PEND mask is something other than 0xFF. Although there are no cardbus U320 controllers, this check may be needed to recover from a hot-plug PCI removal that occurs without informing the driver. Fix a typo. sg_prefetch_cnt -> sg_prefetch_align. This fixes an infinite loop at card initialization if the cacheline size is 0. aic79xx.h: Add AHD_EARLY_REQ_BUG bug flag. Fix spelling errors. Include the CDB's length just after the CDB pointer in the DMA'ed CDB case. Change AH?_OFFSET_UNKNOWN to 0xFF. This is a value that the curr->offset can never be, unlike '0' which we previously used. This fixes code that only checks for a non-zero offset to determine if a sync negotiation is required since it will fire in the unknown case even if the goal is async. aic79xx.reg: Add comments for LQISTAT bits indicating their names in the 7902 data book. We use slightly different and more descriptive names in the firmware. Fix spelling errors. Include the CDB's length just after the CDB pointer in the DMA'ed CDB case. aic79xx.seq: Update comments regarding rundown of the GSFIFO to reflect reality. Fix spelling errors. Since we use an 8byte address and 1 byte length, shorten the size of a block move for the legacy DMA'ed CDB case from 11 to 9 bytes. Remove code that, assuming the abort pending feature worked, would set MK_MESSAGE in the SCB's control byte on completion to catch invalid reselections. Since we don't see interrupts for completed selections, this status update could occur prior to us noticing the SELDO. The "select-out" queue logic will get confused by the MK_MESSAGE bit being set as this is used to catch packatized connections where we select-out with ATN. Since the abort pending feature doesn't work on any released controllers yet, this code was never executed. Add support for the AHD_EARLY_REQ_BUG. Don't ignore persistent REQ assertions just because they were asserted within the bus settle delay window. This allows us to tolerate devices like the GEM318 that violate the SCSI spec. Remove unintentional settnig of SG_CACHE_AVAIL. Writing this bit should have no effect, but who knows... On the Rev A, we must wait for HDMAENACK before loading additional segments to avoid clobbering the address of the first segment in the S/G FIFO. This resolves data-corruption issues with certain IBM (now Hitachi) and Fujitsu U320 drives. Rearrange calc_residual to avoid an extra jmp instruction. On RevA Silicon, if the target returns us to data-out after we have already trained for data-out, it is possible for us to transition the free running clock to data-valid before the required 100ns P1 setup time (8 P1 assertions in fast-160 mode). This will only happen if this L-Q is a continuation of a data transfer for which we have already prefetched data into our FIFO (LQ/Data followed by LQ/Data for the same write transaction). This can cause some target implementations to miss the first few data transfers on the bus. We detect this situation by noticing that this is the first data transfer after an LQ (LQIWORKONLQ true), that the data transfer is a continuation of a transfer already setup in our FIFO (SAVEPTRS interrupt), and that the transaction is a write (DIRECTION set in DFCNTRL). The delay is performed by disabling SCSIEN until we see the first REQ from the target. Only compile in snapshot savepointers handler for RevA silicon where it is enabled. Handle the cfg4icmd packetized interrupt. We just need to load the address and count, start the DMA, and CLRCHN once the transfer is complete. Fix an oversight in the overrun handler for packetized status operations. We need to wait for either CTXTDONE or an overrun when checking for an overrun. The previous code did not wait and thus could decide that no overrun had occurred even though an overrun will occur on the next data-valid req. Add some comment to this section for clarity. Use LAST_SEG_DONE instead of LASTSDONE for testing transfer completion in the packetized status case. LASTSDONE may come up more quickly since it only records completion on the SCSI side, but since LAST_SEG_DONE is used everywhere else (and needs to be), this is less confusing. Add a missing invalidation of the longjmp address in the non-pack handler. This code needs additional review. aic79xx_inline.h: Fix spelling error. aic79xx_osm.c: Set the cdb length for CDBs dma'ed from host memory. Add a comment indicating that, should CAM start supporting cdbs larger than 16bytes, the driver could store the CDB in the status buffer. aic79xx_pci.c: Add a table entry for the 39320A. Added a missing comma to an error string table. Fix spelling errors.
2003-02-27 23:23:16 +00:00
"%s: Signaled Target-abort to early terminate a split in %s\n"
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
};
static const char *pci_status_strings[] =
{
"%s: Data Parity Error has been reported via PERR# in %s\n",
"%s: Target initial wait state error in %s\n",
"%s: Split completion read data parity error in %s\n",
"%s: Split completion address attribute parity error in %s\n",
"%s: Received a Target Abort in %s\n",
"%s: Received a Master Abort in %s\n",
"%s: Signal System Error Detected in %s\n",
"%s: Address or Write Phase Parity Error Detected in %s.\n"
};
void
ahd_pci_intr(struct ahd_softc *ahd)
{
uint8_t pci_status[8];
ahd_mode_state saved_modes;
u_int pci_status1;
u_int intstat;
u_int i;
u_int reg;
intstat = ahd_inb(ahd, INTSTAT);
if ((intstat & SPLTINT) != 0)
ahd_pci_split_intr(ahd, intstat);
if ((intstat & PCIINT) == 0)
return;
printf("%s: PCI error Interrupt\n", ahd_name(ahd));
saved_modes = ahd_save_modes(ahd);
ahd_dump_card_state(ahd);
ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) {
if (i == 5)
continue;
pci_status[i] = ahd_inb(ahd, reg);
aic79xx.c: Clear the LQICRC_NLQ status should it pop up after we have already handled the SCSIPERR. During some streaming operations this status can be delayed until the stream ends. Without this change, the driver would complain about a "Missing case in ahd_handle_scsiint". In the LQOBUSFREE handler... Don't return the LQOMGR back to the idle state until after we have cleaned up ENSELO and any status related to this selection. The last thing we need is the LQO manager starting another select-out before we have updated the execution queue. It is not clear whether the LQOMGR would, or would not start a new selection early. Make sure ENSELO is off prior to clearing SELDO by flushing device writes. Move assignment of the next target SCB pointer inside of an if to make the code clearer. The effect is the same. Dump card state in both "Unexpected PKT busfree" paths. In ahd_reset(), set the chip to SCSI mode before reading SXFRCTL1. That register only exists in the SCSI mode. Also set the mode explicitly to the SCSI mode after chip reset due to paranoia. Re-arrange code so that SXFRCTL1 is restored as quickly after the chip reset as possible. S/G structurs must be 8byte aligned. Make this official by saying so in our DMA tag. Disable CIO bus stretch on MDFFSTAT if SHVALID is about to come true. This can cause a CIO bus lockup if a PCI or PCI-X error occurs while the stretch is occurring - the host cannot service the PCI-X error since the CIO bus is locked out and SHVALID will never resolve. The stretch was added in the Rev B to simplify the wait for SHVALID to resolve, but the code to do this in the open source sequencer is so simple it was never removed. Consistently use MAX_OFFSET for the user max syncrate set from non-volatile storage. This ensures that the offset does not conflict with AH?_OFFSET_UNKNOWN. Have ahd_pause_and_flushwork set the mode to ensure that it has access to the registers it checks. Also modify the checking of intstat so that the check against 0xFF can actually succeed if the INT_PEND mask is something other than 0xFF. Although there are no cardbus U320 controllers, this check may be needed to recover from a hot-plug PCI removal that occurs without informing the driver. Fix a typo. sg_prefetch_cnt -> sg_prefetch_align. This fixes an infinite loop at card initialization if the cacheline size is 0. aic79xx.h: Add AHD_EARLY_REQ_BUG bug flag. Fix spelling errors. Include the CDB's length just after the CDB pointer in the DMA'ed CDB case. Change AH?_OFFSET_UNKNOWN to 0xFF. This is a value that the curr->offset can never be, unlike '0' which we previously used. This fixes code that only checks for a non-zero offset to determine if a sync negotiation is required since it will fire in the unknown case even if the goal is async. aic79xx.reg: Add comments for LQISTAT bits indicating their names in the 7902 data book. We use slightly different and more descriptive names in the firmware. Fix spelling errors. Include the CDB's length just after the CDB pointer in the DMA'ed CDB case. aic79xx.seq: Update comments regarding rundown of the GSFIFO to reflect reality. Fix spelling errors. Since we use an 8byte address and 1 byte length, shorten the size of a block move for the legacy DMA'ed CDB case from 11 to 9 bytes. Remove code that, assuming the abort pending feature worked, would set MK_MESSAGE in the SCB's control byte on completion to catch invalid reselections. Since we don't see interrupts for completed selections, this status update could occur prior to us noticing the SELDO. The "select-out" queue logic will get confused by the MK_MESSAGE bit being set as this is used to catch packatized connections where we select-out with ATN. Since the abort pending feature doesn't work on any released controllers yet, this code was never executed. Add support for the AHD_EARLY_REQ_BUG. Don't ignore persistent REQ assertions just because they were asserted within the bus settle delay window. This allows us to tolerate devices like the GEM318 that violate the SCSI spec. Remove unintentional settnig of SG_CACHE_AVAIL. Writing this bit should have no effect, but who knows... On the Rev A, we must wait for HDMAENACK before loading additional segments to avoid clobbering the address of the first segment in the S/G FIFO. This resolves data-corruption issues with certain IBM (now Hitachi) and Fujitsu U320 drives. Rearrange calc_residual to avoid an extra jmp instruction. On RevA Silicon, if the target returns us to data-out after we have already trained for data-out, it is possible for us to transition the free running clock to data-valid before the required 100ns P1 setup time (8 P1 assertions in fast-160 mode). This will only happen if this L-Q is a continuation of a data transfer for which we have already prefetched data into our FIFO (LQ/Data followed by LQ/Data for the same write transaction). This can cause some target implementations to miss the first few data transfers on the bus. We detect this situation by noticing that this is the first data transfer after an LQ (LQIWORKONLQ true), that the data transfer is a continuation of a transfer already setup in our FIFO (SAVEPTRS interrupt), and that the transaction is a write (DIRECTION set in DFCNTRL). The delay is performed by disabling SCSIEN until we see the first REQ from the target. Only compile in snapshot savepointers handler for RevA silicon where it is enabled. Handle the cfg4icmd packetized interrupt. We just need to load the address and count, start the DMA, and CLRCHN once the transfer is complete. Fix an oversight in the overrun handler for packetized status operations. We need to wait for either CTXTDONE or an overrun when checking for an overrun. The previous code did not wait and thus could decide that no overrun had occurred even though an overrun will occur on the next data-valid req. Add some comment to this section for clarity. Use LAST_SEG_DONE instead of LASTSDONE for testing transfer completion in the packetized status case. LASTSDONE may come up more quickly since it only records completion on the SCSI side, but since LAST_SEG_DONE is used everywhere else (and needs to be), this is less confusing. Add a missing invalidation of the longjmp address in the non-pack handler. This code needs additional review. aic79xx_inline.h: Fix spelling error. aic79xx_osm.c: Set the cdb length for CDBs dma'ed from host memory. Add a comment indicating that, should CAM start supporting cdbs larger than 16bytes, the driver could store the CDB in the status buffer. aic79xx_pci.c: Add a table entry for the 39320A. Added a missing comma to an error string table. Fix spelling errors.
2003-02-27 23:23:16 +00:00
/* Clear latched errors. So our interrupt deasserts. */
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
ahd_outb(ahd, reg, pci_status[i]);
}
for (i = 0; i < 8; i++) {
u_int bit;
if (i == 5)
continue;
for (bit = 0; bit < 8; bit++) {
if ((pci_status[i] & (0x1 << bit)) != 0) {
static const char *s;
s = pci_status_strings[bit];
if (i == 7/*TARG*/ && bit == 3)
Last minute fixes to ahc and ahd: ahd_pci.c: Retrieve the allow_memio hint from the resource manager to determine whether or not to try PCI MEMIO. aic79xx_osm.h: aic7xxx_osm.h: Don't wrongly abuse the callout_reset() interface when trying to abuse timeouts generated from the CAM layer. This fixes the console freeze and lost timeout problem that many have reported, especially on SMP systems. aic79xx_pci.c aic7xxx_pci.c Rewrite the MEMIO test routine to prevent certain broken chipsets from trying to burst multiple DWORDs to the registers. Also make the routine better detect byte merging by the host bridge and deal with it. aic79xx.reg: Correct an incorrect register definition. Approved by: re (rwatson, jhb)
2002-12-04 22:51:29 +00:00
s = "%s: Signaled Target Abort\n";
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
printf(s, ahd_name(ahd), pci_status_source[i]);
}
}
}
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
pci_status1 = aic_pci_read_config(ahd->dev_softc,
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
PCIR_STATUS + 1, /*bytes*/1);
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
pci_status1, /*bytes*/1);
ahd_restore_modes(ahd, saved_modes);
Last minute fixes to ahc and ahd: ahd_pci.c: Retrieve the allow_memio hint from the resource manager to determine whether or not to try PCI MEMIO. aic79xx_osm.h: aic7xxx_osm.h: Don't wrongly abuse the callout_reset() interface when trying to abuse timeouts generated from the CAM layer. This fixes the console freeze and lost timeout problem that many have reported, especially on SMP systems. aic79xx_pci.c aic7xxx_pci.c Rewrite the MEMIO test routine to prevent certain broken chipsets from trying to burst multiple DWORDs to the registers. Also make the routine better detect byte merging by the host bridge and deal with it. aic79xx.reg: Correct an incorrect register definition. Approved by: re (rwatson, jhb)
2002-12-04 22:51:29 +00:00
ahd_outb(ahd, CLRINT, CLRPCIINT);
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
ahd_unpause(ahd);
}
static void
ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat)
{
uint8_t split_status[4];
uint8_t split_status1[4];
uint8_t sg_split_status[2];
uint8_t sg_split_status1[2];
ahd_mode_state saved_modes;
u_int i;
uint16_t pcix_status;
/*
* Check for splits in all modes. Modes 0 and 1
* additionally have SG engine splits to look at.
*/
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
pcix_status = aic_pci_read_config(ahd->dev_softc, PCIXR_STATUS,
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
/*bytes*/2);
printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n",
ahd_name(ahd), pcix_status);
saved_modes = ahd_save_modes(ahd);
for (i = 0; i < 4; i++) {
ahd_set_modes(ahd, i, i);
split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0);
split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1);
aic79xx.c: Clear the LQICRC_NLQ status should it pop up after we have already handled the SCSIPERR. During some streaming operations this status can be delayed until the stream ends. Without this change, the driver would complain about a "Missing case in ahd_handle_scsiint". In the LQOBUSFREE handler... Don't return the LQOMGR back to the idle state until after we have cleaned up ENSELO and any status related to this selection. The last thing we need is the LQO manager starting another select-out before we have updated the execution queue. It is not clear whether the LQOMGR would, or would not start a new selection early. Make sure ENSELO is off prior to clearing SELDO by flushing device writes. Move assignment of the next target SCB pointer inside of an if to make the code clearer. The effect is the same. Dump card state in both "Unexpected PKT busfree" paths. In ahd_reset(), set the chip to SCSI mode before reading SXFRCTL1. That register only exists in the SCSI mode. Also set the mode explicitly to the SCSI mode after chip reset due to paranoia. Re-arrange code so that SXFRCTL1 is restored as quickly after the chip reset as possible. S/G structurs must be 8byte aligned. Make this official by saying so in our DMA tag. Disable CIO bus stretch on MDFFSTAT if SHVALID is about to come true. This can cause a CIO bus lockup if a PCI or PCI-X error occurs while the stretch is occurring - the host cannot service the PCI-X error since the CIO bus is locked out and SHVALID will never resolve. The stretch was added in the Rev B to simplify the wait for SHVALID to resolve, but the code to do this in the open source sequencer is so simple it was never removed. Consistently use MAX_OFFSET for the user max syncrate set from non-volatile storage. This ensures that the offset does not conflict with AH?_OFFSET_UNKNOWN. Have ahd_pause_and_flushwork set the mode to ensure that it has access to the registers it checks. Also modify the checking of intstat so that the check against 0xFF can actually succeed if the INT_PEND mask is something other than 0xFF. Although there are no cardbus U320 controllers, this check may be needed to recover from a hot-plug PCI removal that occurs without informing the driver. Fix a typo. sg_prefetch_cnt -> sg_prefetch_align. This fixes an infinite loop at card initialization if the cacheline size is 0. aic79xx.h: Add AHD_EARLY_REQ_BUG bug flag. Fix spelling errors. Include the CDB's length just after the CDB pointer in the DMA'ed CDB case. Change AH?_OFFSET_UNKNOWN to 0xFF. This is a value that the curr->offset can never be, unlike '0' which we previously used. This fixes code that only checks for a non-zero offset to determine if a sync negotiation is required since it will fire in the unknown case even if the goal is async. aic79xx.reg: Add comments for LQISTAT bits indicating their names in the 7902 data book. We use slightly different and more descriptive names in the firmware. Fix spelling errors. Include the CDB's length just after the CDB pointer in the DMA'ed CDB case. aic79xx.seq: Update comments regarding rundown of the GSFIFO to reflect reality. Fix spelling errors. Since we use an 8byte address and 1 byte length, shorten the size of a block move for the legacy DMA'ed CDB case from 11 to 9 bytes. Remove code that, assuming the abort pending feature worked, would set MK_MESSAGE in the SCB's control byte on completion to catch invalid reselections. Since we don't see interrupts for completed selections, this status update could occur prior to us noticing the SELDO. The "select-out" queue logic will get confused by the MK_MESSAGE bit being set as this is used to catch packatized connections where we select-out with ATN. Since the abort pending feature doesn't work on any released controllers yet, this code was never executed. Add support for the AHD_EARLY_REQ_BUG. Don't ignore persistent REQ assertions just because they were asserted within the bus settle delay window. This allows us to tolerate devices like the GEM318 that violate the SCSI spec. Remove unintentional settnig of SG_CACHE_AVAIL. Writing this bit should have no effect, but who knows... On the Rev A, we must wait for HDMAENACK before loading additional segments to avoid clobbering the address of the first segment in the S/G FIFO. This resolves data-corruption issues with certain IBM (now Hitachi) and Fujitsu U320 drives. Rearrange calc_residual to avoid an extra jmp instruction. On RevA Silicon, if the target returns us to data-out after we have already trained for data-out, it is possible for us to transition the free running clock to data-valid before the required 100ns P1 setup time (8 P1 assertions in fast-160 mode). This will only happen if this L-Q is a continuation of a data transfer for which we have already prefetched data into our FIFO (LQ/Data followed by LQ/Data for the same write transaction). This can cause some target implementations to miss the first few data transfers on the bus. We detect this situation by noticing that this is the first data transfer after an LQ (LQIWORKONLQ true), that the data transfer is a continuation of a transfer already setup in our FIFO (SAVEPTRS interrupt), and that the transaction is a write (DIRECTION set in DFCNTRL). The delay is performed by disabling SCSIEN until we see the first REQ from the target. Only compile in snapshot savepointers handler for RevA silicon where it is enabled. Handle the cfg4icmd packetized interrupt. We just need to load the address and count, start the DMA, and CLRCHN once the transfer is complete. Fix an oversight in the overrun handler for packetized status operations. We need to wait for either CTXTDONE or an overrun when checking for an overrun. The previous code did not wait and thus could decide that no overrun had occurred even though an overrun will occur on the next data-valid req. Add some comment to this section for clarity. Use LAST_SEG_DONE instead of LASTSDONE for testing transfer completion in the packetized status case. LASTSDONE may come up more quickly since it only records completion on the SCSI side, but since LAST_SEG_DONE is used everywhere else (and needs to be), this is less confusing. Add a missing invalidation of the longjmp address in the non-pack handler. This code needs additional review. aic79xx_inline.h: Fix spelling error. aic79xx_osm.c: Set the cdb length for CDBs dma'ed from host memory. Add a comment indicating that, should CAM start supporting cdbs larger than 16bytes, the driver could store the CDB in the status buffer. aic79xx_pci.c: Add a table entry for the 39320A. Added a missing comma to an error string table. Fix spelling errors.
2003-02-27 23:23:16 +00:00
/* Clear latched errors. So our interrupt deasserts. */
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]);
ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]);
Correct spelling errors. Switch to handling bad SCSI status as a sequencer interrupt instead of having the kernel proccess these failures via the completion queue. This is done because: o The old scheme required us to pause the sequencer and clear critical sections for each SCB. It seems that these pause actions, if coincident with a sequencer FIFO interrupt, would result in a FIFO interrupt getting lost or directing to the wrong FIFO. This caused hangs when the driver was stressed under high "queue full" loads. o The completion code assumed that it was always called with the sequencer running. This may not be the case in timeout processing where completions occur manually via ahd_pause_and_flushwork(). o With this scheme, the extra expense of clearing critical sections is avoided since the sequencer will only self pause once all pending selections have cleared and it is not in a critical section. aic79xx.c Add code to handle the new BAD_SCB_STATUS sequencer interrupt code. This just redirects the SCB through the already existing ahd_complete_scb() code path. Remove code in ahd_handle_scsi_status() that paused the sequencer, made sure that no selections where pending, and cleared critical sections. Bad status SCBs are now only processed when all of these conditions are true. aic79xx.reg: Add the BAD_SCB_STATUS sequencer interrupt code. aic79xx.seq: When completing an SCB upload to the host, if we are doing this because the SCB contains non-zero SCSI status, defer completing the SCB until there are no pending selection events. When completing these SCBs, use the new BAD_SCB_STATUS sequencer interrupt. For all other uploaded SCBs (currently only for underruns), the SCB is completed via the normal done queue. Additionally, keep the SCB that is currently being uploaded on the COMPLETE_DMA_SCB list until the dma is completed, not just until the DMA is started. This ensures that the DMA is restarted properly should the host disable the DMA transfer for some reason. In our RevA workaround for Maxtor drives, guard against the host pausing us while trying to pause I/O until the first data-valid REQ by clearing the current snapshot so that we can tell if the transfer has completed prior to us noticing the REQINIT status. In cfg4data_intr, shave off an instruction before getting the data path running by adding an entrypoint to the overrun handler to also increment the FIFO use count. In the overrun handler, be sure to clear our LONGJMP address in both exit paths. Perform a few sequencer optimizations. aic79xx.c: Print the full path from the SCB when a packetized status overrun occurs. Remove references to LONGJMP_SCB which is being removed from firmware usage. Print the new SCB_FIFO_USE_COUNT field in the per-SCB section of ahd_dump_card_state(). The SCB_TAG field is now re-used by the sequencer, so it no longer makes sense to reference this field in the kernel driver. aic79xx.h: Re-arrange fields in the hardware SCB from largest size type to smallest. This makes it easier to move fields without changing field alignment. The hardware scb tag field is now down near the "spare" portion of the SCB to facilitate reuse by the sequencer. aic79xx.reg: Remove LONGJMP_ADDR. Rearrange SCB fields to match aic79xx.h. Add SCB_FIFO_USE_COUNT as the first byte of the SCB_TAG field. aic79xx.seq: Add a per-SCB "Fifos in use count" field and use it to determine when it is safe (all data posted) to deliver status back to the host. The old method involved polling one or both FIFOs to verify that the current task did not have pending data. This makes running down the GSFIFO very cheap, so we will empty the GSFIFO in one idle loop pass in all cases. Use this simplification of the completion process to prune down the data FIFO teardown sequencer for packetized transfers. Much more code is now shared between the data residual and transfer complete cases. Correct some issues in the packetized status handler. It used to be possible to CLRCHN our FIFO before status had fully transferred to the host. We also failed to handle NONPACKREQ phases that could occur should a CRC error occur during transmission of the status data packet. Correct a few big endian issues: aic79xx.c: aic79xx_inline.h: aic79xx_pci.c: aic79xx_osm.c: o Always get the SCB's tag via the SCB_GET_TAG acccessor o Add missing use of byte swapping macros when touching hscb fields. o Don't double swap SEEPROM data when it is printed. Correct a big-endian bug. We cannot assign a o When assigning a 32bit LE variable to a 64bit LE variable, we must be explict about how the words of the 64bit LE variable are initialized. Cast to (uint32_t*) to do this. aic79xx.c: In ahd_clear_critical_section(), hit CRLSCSIINT after restoring the interrupt masks to avoid what appears to be a glitch on SCSIINT. Any real SCSIINT status will be persistent and will immidiately reset SCSIINT. This clear should only get rid of spurious SCSIINTs. This glitch was the cause of the "Unexpected PKT busfree" status that occurred under high queue full loads Call ahd_fini_scbdata() after shutdown so that any ahd_chip_init() routine that might access SCB data will not access free'd memory. Reset the bus on an IOERR since the chip doesn't seem to reset to the new voltage level without this. Change offset calculation for scatter gather maps so that the calculation is correct if an integral multiple of sg lists does not fit in the allocation size. Adjust bus dma tag for data buffers based on 39BIT addressing flag in our softc. Use the QFREEZE count to simplify ahd_pause_and_flushworkd(). We can thus rely on the sequencer eventually clearing ENSELO. In ahd_abort_scbs(), fix a bug that could potentially corrupt sequencer state. The saved SCB was being restored in the SCSI mode instead of the saved mode. It turns out that the SCB did not need to be saved at all as the scbptr is already restored by all subroutines called during this function that modify that register. aic79xx.c: aic79xx.h: aic79xx_pci.c: Add support for parsing the seeprom vital product data. The VPD data are currently unused. aic79xx.h: aic79xx.seq: aic79xx_pci.c: Add a firmware workaround to make the LED blink brighter during packetized operations on the H2A. aic79xx_inline.h: The host does not use timer interrupts, so don't gate our decision on whether or not to unpause the sequencer on whether or not a timer interrupt is pending.
2003-05-04 00:20:07 +00:00
if (i > 1)
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
continue;
sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0);
sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1);
aic79xx.c: Clear the LQICRC_NLQ status should it pop up after we have already handled the SCSIPERR. During some streaming operations this status can be delayed until the stream ends. Without this change, the driver would complain about a "Missing case in ahd_handle_scsiint". In the LQOBUSFREE handler... Don't return the LQOMGR back to the idle state until after we have cleaned up ENSELO and any status related to this selection. The last thing we need is the LQO manager starting another select-out before we have updated the execution queue. It is not clear whether the LQOMGR would, or would not start a new selection early. Make sure ENSELO is off prior to clearing SELDO by flushing device writes. Move assignment of the next target SCB pointer inside of an if to make the code clearer. The effect is the same. Dump card state in both "Unexpected PKT busfree" paths. In ahd_reset(), set the chip to SCSI mode before reading SXFRCTL1. That register only exists in the SCSI mode. Also set the mode explicitly to the SCSI mode after chip reset due to paranoia. Re-arrange code so that SXFRCTL1 is restored as quickly after the chip reset as possible. S/G structurs must be 8byte aligned. Make this official by saying so in our DMA tag. Disable CIO bus stretch on MDFFSTAT if SHVALID is about to come true. This can cause a CIO bus lockup if a PCI or PCI-X error occurs while the stretch is occurring - the host cannot service the PCI-X error since the CIO bus is locked out and SHVALID will never resolve. The stretch was added in the Rev B to simplify the wait for SHVALID to resolve, but the code to do this in the open source sequencer is so simple it was never removed. Consistently use MAX_OFFSET for the user max syncrate set from non-volatile storage. This ensures that the offset does not conflict with AH?_OFFSET_UNKNOWN. Have ahd_pause_and_flushwork set the mode to ensure that it has access to the registers it checks. Also modify the checking of intstat so that the check against 0xFF can actually succeed if the INT_PEND mask is something other than 0xFF. Although there are no cardbus U320 controllers, this check may be needed to recover from a hot-plug PCI removal that occurs without informing the driver. Fix a typo. sg_prefetch_cnt -> sg_prefetch_align. This fixes an infinite loop at card initialization if the cacheline size is 0. aic79xx.h: Add AHD_EARLY_REQ_BUG bug flag. Fix spelling errors. Include the CDB's length just after the CDB pointer in the DMA'ed CDB case. Change AH?_OFFSET_UNKNOWN to 0xFF. This is a value that the curr->offset can never be, unlike '0' which we previously used. This fixes code that only checks for a non-zero offset to determine if a sync negotiation is required since it will fire in the unknown case even if the goal is async. aic79xx.reg: Add comments for LQISTAT bits indicating their names in the 7902 data book. We use slightly different and more descriptive names in the firmware. Fix spelling errors. Include the CDB's length just after the CDB pointer in the DMA'ed CDB case. aic79xx.seq: Update comments regarding rundown of the GSFIFO to reflect reality. Fix spelling errors. Since we use an 8byte address and 1 byte length, shorten the size of a block move for the legacy DMA'ed CDB case from 11 to 9 bytes. Remove code that, assuming the abort pending feature worked, would set MK_MESSAGE in the SCB's control byte on completion to catch invalid reselections. Since we don't see interrupts for completed selections, this status update could occur prior to us noticing the SELDO. The "select-out" queue logic will get confused by the MK_MESSAGE bit being set as this is used to catch packatized connections where we select-out with ATN. Since the abort pending feature doesn't work on any released controllers yet, this code was never executed. Add support for the AHD_EARLY_REQ_BUG. Don't ignore persistent REQ assertions just because they were asserted within the bus settle delay window. This allows us to tolerate devices like the GEM318 that violate the SCSI spec. Remove unintentional settnig of SG_CACHE_AVAIL. Writing this bit should have no effect, but who knows... On the Rev A, we must wait for HDMAENACK before loading additional segments to avoid clobbering the address of the first segment in the S/G FIFO. This resolves data-corruption issues with certain IBM (now Hitachi) and Fujitsu U320 drives. Rearrange calc_residual to avoid an extra jmp instruction. On RevA Silicon, if the target returns us to data-out after we have already trained for data-out, it is possible for us to transition the free running clock to data-valid before the required 100ns P1 setup time (8 P1 assertions in fast-160 mode). This will only happen if this L-Q is a continuation of a data transfer for which we have already prefetched data into our FIFO (LQ/Data followed by LQ/Data for the same write transaction). This can cause some target implementations to miss the first few data transfers on the bus. We detect this situation by noticing that this is the first data transfer after an LQ (LQIWORKONLQ true), that the data transfer is a continuation of a transfer already setup in our FIFO (SAVEPTRS interrupt), and that the transaction is a write (DIRECTION set in DFCNTRL). The delay is performed by disabling SCSIEN until we see the first REQ from the target. Only compile in snapshot savepointers handler for RevA silicon where it is enabled. Handle the cfg4icmd packetized interrupt. We just need to load the address and count, start the DMA, and CLRCHN once the transfer is complete. Fix an oversight in the overrun handler for packetized status operations. We need to wait for either CTXTDONE or an overrun when checking for an overrun. The previous code did not wait and thus could decide that no overrun had occurred even though an overrun will occur on the next data-valid req. Add some comment to this section for clarity. Use LAST_SEG_DONE instead of LASTSDONE for testing transfer completion in the packetized status case. LASTSDONE may come up more quickly since it only records completion on the SCSI side, but since LAST_SEG_DONE is used everywhere else (and needs to be), this is less confusing. Add a missing invalidation of the longjmp address in the non-pack handler. This code needs additional review. aic79xx_inline.h: Fix spelling error. aic79xx_osm.c: Set the cdb length for CDBs dma'ed from host memory. Add a comment indicating that, should CAM start supporting cdbs larger than 16bytes, the driver could store the CDB in the status buffer. aic79xx_pci.c: Add a table entry for the 39320A. Added a missing comma to an error string table. Fix spelling errors.
2003-02-27 23:23:16 +00:00
/* Clear latched errors. So our interrupt deasserts. */
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]);
ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]);
}
for (i = 0; i < 4; i++) {
u_int bit;
for (bit = 0; bit < 8; bit++) {
if ((split_status[i] & (0x1 << bit)) != 0) {
static const char *s;
s = split_status_strings[bit];
printf(s, ahd_name(ahd),
split_status_source[i]);
}
Correct spelling errors. Switch to handling bad SCSI status as a sequencer interrupt instead of having the kernel proccess these failures via the completion queue. This is done because: o The old scheme required us to pause the sequencer and clear critical sections for each SCB. It seems that these pause actions, if coincident with a sequencer FIFO interrupt, would result in a FIFO interrupt getting lost or directing to the wrong FIFO. This caused hangs when the driver was stressed under high "queue full" loads. o The completion code assumed that it was always called with the sequencer running. This may not be the case in timeout processing where completions occur manually via ahd_pause_and_flushwork(). o With this scheme, the extra expense of clearing critical sections is avoided since the sequencer will only self pause once all pending selections have cleared and it is not in a critical section. aic79xx.c Add code to handle the new BAD_SCB_STATUS sequencer interrupt code. This just redirects the SCB through the already existing ahd_complete_scb() code path. Remove code in ahd_handle_scsi_status() that paused the sequencer, made sure that no selections where pending, and cleared critical sections. Bad status SCBs are now only processed when all of these conditions are true. aic79xx.reg: Add the BAD_SCB_STATUS sequencer interrupt code. aic79xx.seq: When completing an SCB upload to the host, if we are doing this because the SCB contains non-zero SCSI status, defer completing the SCB until there are no pending selection events. When completing these SCBs, use the new BAD_SCB_STATUS sequencer interrupt. For all other uploaded SCBs (currently only for underruns), the SCB is completed via the normal done queue. Additionally, keep the SCB that is currently being uploaded on the COMPLETE_DMA_SCB list until the dma is completed, not just until the DMA is started. This ensures that the DMA is restarted properly should the host disable the DMA transfer for some reason. In our RevA workaround for Maxtor drives, guard against the host pausing us while trying to pause I/O until the first data-valid REQ by clearing the current snapshot so that we can tell if the transfer has completed prior to us noticing the REQINIT status. In cfg4data_intr, shave off an instruction before getting the data path running by adding an entrypoint to the overrun handler to also increment the FIFO use count. In the overrun handler, be sure to clear our LONGJMP address in both exit paths. Perform a few sequencer optimizations. aic79xx.c: Print the full path from the SCB when a packetized status overrun occurs. Remove references to LONGJMP_SCB which is being removed from firmware usage. Print the new SCB_FIFO_USE_COUNT field in the per-SCB section of ahd_dump_card_state(). The SCB_TAG field is now re-used by the sequencer, so it no longer makes sense to reference this field in the kernel driver. aic79xx.h: Re-arrange fields in the hardware SCB from largest size type to smallest. This makes it easier to move fields without changing field alignment. The hardware scb tag field is now down near the "spare" portion of the SCB to facilitate reuse by the sequencer. aic79xx.reg: Remove LONGJMP_ADDR. Rearrange SCB fields to match aic79xx.h. Add SCB_FIFO_USE_COUNT as the first byte of the SCB_TAG field. aic79xx.seq: Add a per-SCB "Fifos in use count" field and use it to determine when it is safe (all data posted) to deliver status back to the host. The old method involved polling one or both FIFOs to verify that the current task did not have pending data. This makes running down the GSFIFO very cheap, so we will empty the GSFIFO in one idle loop pass in all cases. Use this simplification of the completion process to prune down the data FIFO teardown sequencer for packetized transfers. Much more code is now shared between the data residual and transfer complete cases. Correct some issues in the packetized status handler. It used to be possible to CLRCHN our FIFO before status had fully transferred to the host. We also failed to handle NONPACKREQ phases that could occur should a CRC error occur during transmission of the status data packet. Correct a few big endian issues: aic79xx.c: aic79xx_inline.h: aic79xx_pci.c: aic79xx_osm.c: o Always get the SCB's tag via the SCB_GET_TAG acccessor o Add missing use of byte swapping macros when touching hscb fields. o Don't double swap SEEPROM data when it is printed. Correct a big-endian bug. We cannot assign a o When assigning a 32bit LE variable to a 64bit LE variable, we must be explict about how the words of the 64bit LE variable are initialized. Cast to (uint32_t*) to do this. aic79xx.c: In ahd_clear_critical_section(), hit CRLSCSIINT after restoring the interrupt masks to avoid what appears to be a glitch on SCSIINT. Any real SCSIINT status will be persistent and will immidiately reset SCSIINT. This clear should only get rid of spurious SCSIINTs. This glitch was the cause of the "Unexpected PKT busfree" status that occurred under high queue full loads Call ahd_fini_scbdata() after shutdown so that any ahd_chip_init() routine that might access SCB data will not access free'd memory. Reset the bus on an IOERR since the chip doesn't seem to reset to the new voltage level without this. Change offset calculation for scatter gather maps so that the calculation is correct if an integral multiple of sg lists does not fit in the allocation size. Adjust bus dma tag for data buffers based on 39BIT addressing flag in our softc. Use the QFREEZE count to simplify ahd_pause_and_flushworkd(). We can thus rely on the sequencer eventually clearing ENSELO. In ahd_abort_scbs(), fix a bug that could potentially corrupt sequencer state. The saved SCB was being restored in the SCSI mode instead of the saved mode. It turns out that the SCB did not need to be saved at all as the scbptr is already restored by all subroutines called during this function that modify that register. aic79xx.c: aic79xx.h: aic79xx_pci.c: Add support for parsing the seeprom vital product data. The VPD data are currently unused. aic79xx.h: aic79xx.seq: aic79xx_pci.c: Add a firmware workaround to make the LED blink brighter during packetized operations on the H2A. aic79xx_inline.h: The host does not use timer interrupts, so don't gate our decision on whether or not to unpause the sequencer on whether or not a timer interrupt is pending.
2003-05-04 00:20:07 +00:00
if (i > 1)
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
continue;
if ((sg_split_status[i] & (0x1 << bit)) != 0) {
static const char *s;
s = split_status_strings[bit];
printf(s, ahd_name(ahd), "SG");
}
}
}
/*
* Clear PCI-X status bits.
*/
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
aic_pci_write_config(ahd->dev_softc, PCIXR_STATUS,
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
pcix_status, /*bytes*/2);
Last minute fixes to ahc and ahd: ahd_pci.c: Retrieve the allow_memio hint from the resource manager to determine whether or not to try PCI MEMIO. aic79xx_osm.h: aic7xxx_osm.h: Don't wrongly abuse the callout_reset() interface when trying to abuse timeouts generated from the CAM layer. This fixes the console freeze and lost timeout problem that many have reported, especially on SMP systems. aic79xx_pci.c aic7xxx_pci.c Rewrite the MEMIO test routine to prevent certain broken chipsets from trying to burst multiple DWORDs to the registers. Also make the routine better detect byte merging by the host bridge and deal with it. aic79xx.reg: Correct an incorrect register definition. Approved by: re (rwatson, jhb)
2002-12-04 22:51:29 +00:00
ahd_outb(ahd, CLRINT, CLRSPLTINT);
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
ahd_restore_modes(ahd, saved_modes);
}
Add 7901B support. Sort IDs based on chip type. Remove IROC IDs. We'll switch to using the IROC masks if/when we want to start attaching to IROC controllers. Approved by: RE
2003-05-26 21:15:52 +00:00
static int
ahd_aic7901_setup(struct ahd_softc *ahd)
{
ahd->chip = AHD_AIC7901;
aic79xx.h: Add a 7901A specific feature definition. aic79xx_pci.c: Split out the general aic790X setup into it's own setup handler that works on single and dual controllers. Adjust all other PCI setup handlers to initialize the chips basic features and type before calling the generic handler. Turn off a few Rev B workarounds that are not required on the 7901B.
2003-06-28 04:39:49 +00:00
ahd->features = AHD_AIC7901_FE;
return (ahd_aic790X_setup(ahd));
Add 7901B support. Sort IDs based on chip type. Remove IROC IDs. We'll switch to using the IROC masks if/when we want to start attaching to IROC controllers. Approved by: RE
2003-05-26 21:15:52 +00:00
}
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
static int
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
ahd_aic7901A_setup(struct ahd_softc *ahd)
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
{
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
ahd->chip = AHD_AIC7901A;
aic79xx.h: Add a 7901A specific feature definition. aic79xx_pci.c: Split out the general aic790X setup into it's own setup handler that works on single and dual controllers. Adjust all other PCI setup handlers to initialize the chips basic features and type before calling the generic handler. Turn off a few Rev B workarounds that are not required on the 7901B.
2003-06-28 04:39:49 +00:00
ahd->features = AHD_AIC7901A_FE;
return (ahd_aic790X_setup(ahd));
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
static int
ahd_aic7902_setup(struct ahd_softc *ahd)
aic79xx.h: Add a 7901A specific feature definition. aic79xx_pci.c: Split out the general aic790X setup into it's own setup handler that works on single and dual controllers. Adjust all other PCI setup handlers to initialize the chips basic features and type before calling the generic handler. Turn off a few Rev B workarounds that are not required on the 7901B.
2003-06-28 04:39:49 +00:00
{
ahd->chip = AHD_AIC7902;
ahd->features = AHD_AIC7902_FE;
return (ahd_aic790X_setup(ahd));
}
static int
ahd_aic790X_setup(struct ahd_softc *ahd)
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
{
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
aic_dev_softc_t pci;
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
u_int rev;
pci = ahd->dev_softc;
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
Identify new controllers and the aic7901A. Move interrupt enable to the OSM. Remove some debugging messages. Remove chip bug workarounds for non-production asics.
2002-08-31 06:52:27 +00:00
if (rev < ID_AIC7902_PCI_REV_A4) {
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
printf("%s: Unable to attach to unsupported chip revision %d\n",
ahd_name(ahd), rev);
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
aic_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2);
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
return (ENXIO);
}
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
ahd->channel = aic_get_pci_function(pci) + 'A';
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
if (rev < ID_AIC7902_PCI_REV_B0) {
/*
* Enable A series workarounds.
*/
ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG
| AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG
| AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG
| AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG
| AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG
aic79xx.c: Include read streaming in the PPR flags we display in diagnostics. In ahd_reset(), set the known mode after our initial pause prior to setting the mode. We can't just set the mode directly because the current mode, after the pause, is most likely unknown and setting the mode when the saved mode is unknown will trigger an assertion in the mode debug code. Complete an audit for SCB RAM reads. These reads must be performed via the special ahd_in?_scbram() methods so we can perform a Rev A. PCI-X workaround. Remove a superfluous mode save operation that was performed just prior to a call to ahd_clear_critical_section(). The saved mode was never restored and wouldn't have been valid anyway since the mode could change while single stepping out of a critical section. aic79xx.h: Add new BUG definition AHD_PCIX_SCBRAM_RD_BUG. aic79xx_inline.h: Update ahd_inb_scbram routine to check for AHD_PCIX_SCBRAM_RD_BUG and only apply the workaround if this bug is active. The old code applied the workaround in all cases. aic79xx_pci.c: Set AHD_PCIX_SCBRAM_RD_BUG for the A4. Remove an attempted saved_modes call in ahd_pci_test_register_access(). Saving the modes can only occur when we are paused, but the call was happening before the chip was known to be paused. Restoring the modes doesn't make sense either since the code makes no assumptions about the state of the sequencer until the first time the mode is set by the driver. This happens after the registers are successfully mapped.
2003-03-06 23:58:34 +00:00
| AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG
| AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG
| AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG
| AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG
Correct spelling errors. Switch to handling bad SCSI status as a sequencer interrupt instead of having the kernel proccess these failures via the completion queue. This is done because: o The old scheme required us to pause the sequencer and clear critical sections for each SCB. It seems that these pause actions, if coincident with a sequencer FIFO interrupt, would result in a FIFO interrupt getting lost or directing to the wrong FIFO. This caused hangs when the driver was stressed under high "queue full" loads. o The completion code assumed that it was always called with the sequencer running. This may not be the case in timeout processing where completions occur manually via ahd_pause_and_flushwork(). o With this scheme, the extra expense of clearing critical sections is avoided since the sequencer will only self pause once all pending selections have cleared and it is not in a critical section. aic79xx.c Add code to handle the new BAD_SCB_STATUS sequencer interrupt code. This just redirects the SCB through the already existing ahd_complete_scb() code path. Remove code in ahd_handle_scsi_status() that paused the sequencer, made sure that no selections where pending, and cleared critical sections. Bad status SCBs are now only processed when all of these conditions are true. aic79xx.reg: Add the BAD_SCB_STATUS sequencer interrupt code. aic79xx.seq: When completing an SCB upload to the host, if we are doing this because the SCB contains non-zero SCSI status, defer completing the SCB until there are no pending selection events. When completing these SCBs, use the new BAD_SCB_STATUS sequencer interrupt. For all other uploaded SCBs (currently only for underruns), the SCB is completed via the normal done queue. Additionally, keep the SCB that is currently being uploaded on the COMPLETE_DMA_SCB list until the dma is completed, not just until the DMA is started. This ensures that the DMA is restarted properly should the host disable the DMA transfer for some reason. In our RevA workaround for Maxtor drives, guard against the host pausing us while trying to pause I/O until the first data-valid REQ by clearing the current snapshot so that we can tell if the transfer has completed prior to us noticing the REQINIT status. In cfg4data_intr, shave off an instruction before getting the data path running by adding an entrypoint to the overrun handler to also increment the FIFO use count. In the overrun handler, be sure to clear our LONGJMP address in both exit paths. Perform a few sequencer optimizations. aic79xx.c: Print the full path from the SCB when a packetized status overrun occurs. Remove references to LONGJMP_SCB which is being removed from firmware usage. Print the new SCB_FIFO_USE_COUNT field in the per-SCB section of ahd_dump_card_state(). The SCB_TAG field is now re-used by the sequencer, so it no longer makes sense to reference this field in the kernel driver. aic79xx.h: Re-arrange fields in the hardware SCB from largest size type to smallest. This makes it easier to move fields without changing field alignment. The hardware scb tag field is now down near the "spare" portion of the SCB to facilitate reuse by the sequencer. aic79xx.reg: Remove LONGJMP_ADDR. Rearrange SCB fields to match aic79xx.h. Add SCB_FIFO_USE_COUNT as the first byte of the SCB_TAG field. aic79xx.seq: Add a per-SCB "Fifos in use count" field and use it to determine when it is safe (all data posted) to deliver status back to the host. The old method involved polling one or both FIFOs to verify that the current task did not have pending data. This makes running down the GSFIFO very cheap, so we will empty the GSFIFO in one idle loop pass in all cases. Use this simplification of the completion process to prune down the data FIFO teardown sequencer for packetized transfers. Much more code is now shared between the data residual and transfer complete cases. Correct some issues in the packetized status handler. It used to be possible to CLRCHN our FIFO before status had fully transferred to the host. We also failed to handle NONPACKREQ phases that could occur should a CRC error occur during transmission of the status data packet. Correct a few big endian issues: aic79xx.c: aic79xx_inline.h: aic79xx_pci.c: aic79xx_osm.c: o Always get the SCB's tag via the SCB_GET_TAG acccessor o Add missing use of byte swapping macros when touching hscb fields. o Don't double swap SEEPROM data when it is printed. Correct a big-endian bug. We cannot assign a o When assigning a 32bit LE variable to a 64bit LE variable, we must be explict about how the words of the 64bit LE variable are initialized. Cast to (uint32_t*) to do this. aic79xx.c: In ahd_clear_critical_section(), hit CRLSCSIINT after restoring the interrupt masks to avoid what appears to be a glitch on SCSIINT. Any real SCSIINT status will be persistent and will immidiately reset SCSIINT. This clear should only get rid of spurious SCSIINTs. This glitch was the cause of the "Unexpected PKT busfree" status that occurred under high queue full loads Call ahd_fini_scbdata() after shutdown so that any ahd_chip_init() routine that might access SCB data will not access free'd memory. Reset the bus on an IOERR since the chip doesn't seem to reset to the new voltage level without this. Change offset calculation for scatter gather maps so that the calculation is correct if an integral multiple of sg lists does not fit in the allocation size. Adjust bus dma tag for data buffers based on 39BIT addressing flag in our softc. Use the QFREEZE count to simplify ahd_pause_and_flushworkd(). We can thus rely on the sequencer eventually clearing ENSELO. In ahd_abort_scbs(), fix a bug that could potentially corrupt sequencer state. The saved SCB was being restored in the SCSI mode instead of the saved mode. It turns out that the SCB did not need to be saved at all as the scbptr is already restored by all subroutines called during this function that modify that register. aic79xx.c: aic79xx.h: aic79xx_pci.c: Add support for parsing the seeprom vital product data. The VPD data are currently unused. aic79xx.h: aic79xx.seq: aic79xx_pci.c: Add a firmware workaround to make the LED blink brighter during packetized operations on the H2A. aic79xx_inline.h: The host does not use timer interrupts, so don't gate our decision on whether or not to unpause the sequencer on whether or not a timer interrupt is pending.
2003-05-04 00:20:07 +00:00
| AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG
| AHD_FAINT_LED_BUG;
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
/*
* IO Cell paramter setup.
*/
AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
Identify new controllers and the aic7901A. Move interrupt enable to the OSM. Remove some debugging messages. Remove chip bug workarounds for non-production asics.
2002-08-31 06:52:27 +00:00
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
if ((ahd->flags & AHD_HP_BOARD) == 0)
AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA);
} else {
u_int devconfig1;
ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
| AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY;
aic79xx.h: Add a 7901A specific feature definition. aic79xx_pci.c: Split out the general aic790X setup into it's own setup handler that works on single and dual controllers. Adjust all other PCI setup handlers to initialize the chips basic features and type before calling the generic handler. Turn off a few Rev B workarounds that are not required on the 7901B.
2003-06-28 04:39:49 +00:00
ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG;
/*
* Some issues have been resolved in the 7901B.
*/
if ((ahd->features & AHD_MULTI_FUNC) != 0)
ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG;
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
/*
* IO Cell paramter setup.
*/
AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB);
AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF);
/*
* Set the PREQDIS bit for H2B which disables some workaround
* that doesn't work on regular PCI busses.
* XXX - Find out exactly what this does from the hardware
* folks!
*/
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
aic_pci_write_config(pci, DEVCONFIG1,
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
devconfig1|PREQDIS, /*bytes*/1);
ahc_eisa.c: ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
2003-12-17 00:02:10 +00:00
devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
Implement workaround for broken busfree-rev in the A4. HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
2002-12-01 07:59:01 +00:00
}
Identify new controllers and the aic7901A. Move interrupt enable to the OSM. Remove some debugging messages. Remove chip bug workarounds for non-production asics.
2002-08-31 06:52:27 +00:00
return (0);
}
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