487 lines
12 KiB
C
487 lines
12 KiB
C
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/*-
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* Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_wlan.h"
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#include <sys/param.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/mbuf.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/queue.h>
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#include <sys/taskqueue.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/linker.h>
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#include <net/if.h>
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#include <net/ethernet.h>
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#include <net/if_media.h>
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#include <net80211/ieee80211_var.h>
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#include <net80211/ieee80211_radiotap.h>
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#include <dev/rtwn/if_rtwnreg.h>
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#include <dev/rtwn/if_rtwnvar.h>
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#include <dev/rtwn/if_rtwn_debug.h>
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#include <dev/rtwn/rtl8192c/r92c.h>
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#include <dev/rtwn/rtl8812a/r12a.h>
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#include <dev/rtwn/rtl8812a/r12a_priv.h>
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#include <dev/rtwn/rtl8812a/r12a_reg.h>
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#include <dev/rtwn/rtl8812a/r12a_var.h>
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int
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r12a_check_condition(struct rtwn_softc *sc, const uint8_t cond[])
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{
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struct r12a_softc *rs = sc->sc_priv;
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uint8_t mask[4];
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int i, j, nmasks;
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RTWN_DPRINTF(sc, RTWN_DEBUG_RESET,
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"%s: condition byte 0: %02X; ext PA/LNA: %d/%d (2 GHz), "
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"%d/%d (5 GHz)\n", __func__, cond[0], rs->ext_pa_2g,
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rs->ext_lna_2g, rs->ext_pa_5g, rs->ext_lna_5g);
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if (cond[0] == 0)
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return (1);
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if (!rs->ext_pa_2g && !rs->ext_lna_2g &&
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!rs->ext_pa_5g && !rs->ext_lna_5g)
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return (0);
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nmasks = 0;
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if (rs->ext_pa_2g) {
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mask[nmasks] = R12A_COND_GPA;
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mask[nmasks] |= R12A_COND_TYPE(rs->type_pa_2g);
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nmasks++;
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}
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if (rs->ext_pa_5g) {
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mask[nmasks] = R12A_COND_APA;
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mask[nmasks] |= R12A_COND_TYPE(rs->type_pa_5g);
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nmasks++;
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}
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if (rs->ext_lna_2g) {
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mask[nmasks] = R12A_COND_GLNA;
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mask[nmasks] |= R12A_COND_TYPE(rs->type_lna_2g);
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nmasks++;
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}
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if (rs->ext_lna_5g) {
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mask[nmasks] = R12A_COND_ALNA;
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mask[nmasks] |= R12A_COND_TYPE(rs->type_lna_5g);
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nmasks++;
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}
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for (i = 0; i < RTWN_MAX_CONDITIONS && cond[i] != 0; i++)
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for (j = 0; j < nmasks; j++)
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if ((cond[i] & mask[j]) == mask[j])
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return (1);
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return (0);
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}
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int
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r12a_set_page_size(struct rtwn_softc *sc)
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{
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return (rtwn_setbits_1(sc, R92C_PBP, R92C_PBP_PSTX_M,
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R92C_PBP_512 << R92C_PBP_PSTX_S) == 0);
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}
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void
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r12a_init_edca(struct rtwn_softc *sc)
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{
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r92c_init_edca(sc);
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/* 80 MHz clock */
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rtwn_write_1(sc, R92C_USTIME_TSF, 0x50);
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rtwn_write_1(sc, R92C_USTIME_EDCA, 0x50);
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}
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void
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r12a_init_bb(struct rtwn_softc *sc)
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{
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int i, j;
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rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, 0, R92C_SYS_FUNC_EN_USBA);
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/* Enable BB and RF. */
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rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, 0,
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R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST);
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/* PathA RF Power On. */
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rtwn_write_1(sc, R92C_RF_CTRL,
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R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
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/* PathB RF Power On. */
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rtwn_write_1(sc, R12A_RF_B_CTRL,
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R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
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/* Write BB initialization values. */
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for (i = 0; i < sc->bb_size; i++) {
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const struct rtwn_bb_prog *bb_prog = &sc->bb_prog[i];
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while (!rtwn_check_condition(sc, bb_prog->cond)) {
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KASSERT(bb_prog->next != NULL,
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("%s: wrong condition value (i %d)\n",
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__func__, i));
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bb_prog = bb_prog->next;
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}
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for (j = 0; j < bb_prog->count; j++) {
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RTWN_DPRINTF(sc, RTWN_DEBUG_RESET,
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"BB: reg 0x%03x, val 0x%08x\n",
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bb_prog->reg[j], bb_prog->val[j]);
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rtwn_bb_write(sc, bb_prog->reg[j], bb_prog->val[j]);
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rtwn_delay(sc, 1);
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}
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}
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/* XXX meshpoint mode? */
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/* Write AGC values. */
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for (i = 0; i < sc->agc_size; i++) {
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const struct rtwn_agc_prog *agc_prog = &sc->agc_prog[i];
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while (!rtwn_check_condition(sc, agc_prog->cond)) {
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KASSERT(agc_prog->next != NULL,
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("%s: wrong condition value (2) (i %d)\n",
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__func__, i));
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agc_prog = agc_prog->next;
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}
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for (j = 0; j < agc_prog->count; j++) {
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RTWN_DPRINTF(sc, RTWN_DEBUG_RESET,
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"AGC: val 0x%08x\n", agc_prog->val[j]);
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rtwn_bb_write(sc, 0x81c, agc_prog->val[j]);
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rtwn_delay(sc, 1);
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}
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}
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for (i = 0; i < sc->nrxchains; i++) {
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rtwn_bb_write(sc, R12A_INITIAL_GAIN(i), 0x22);
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rtwn_delay(sc, 1);
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rtwn_bb_write(sc, R12A_INITIAL_GAIN(i), 0x20);
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rtwn_delay(sc, 1);
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}
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rtwn_r12a_crystalcap_write(sc);
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if (rtwn_bb_read(sc, R12A_CCK_RPT_FORMAT) & R12A_CCK_RPT_FORMAT_HIPWR)
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sc->sc_flags |= RTWN_FLAG_CCK_HIPWR;
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}
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void
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r12a_init_rf(struct rtwn_softc *sc)
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{
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int chain, i;
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for (chain = 0, i = 0; chain < sc->nrxchains; chain++, i++) {
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/* Write RF initialization values for this chain. */
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i += r92c_init_rf_chain(sc, &sc->rf_prog[i], chain);
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}
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}
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void
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r12a_crystalcap_write(struct rtwn_softc *sc)
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{
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struct r12a_softc *rs = sc->sc_priv;
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uint32_t reg;
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uint8_t val;
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val = rs->crystalcap & 0x3f;
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reg = rtwn_bb_read(sc, R92C_MAC_PHY_CTRL);
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reg = RW(reg, R12A_MAC_PHY_CRYSTALCAP, val | (val << 6));
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rtwn_bb_write(sc, R92C_MAC_PHY_CTRL, reg);
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}
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static void
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r12a_rf_init_workaround(struct rtwn_softc *sc)
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{
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rtwn_write_1(sc, R92C_RF_CTRL,
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R92C_RF_CTRL_EN | R92C_RF_CTRL_SDMRSTB);
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rtwn_write_1(sc, R92C_RF_CTRL,
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R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB |
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R92C_RF_CTRL_SDMRSTB);
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rtwn_write_1(sc, R12A_RF_B_CTRL,
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R92C_RF_CTRL_EN | R92C_RF_CTRL_SDMRSTB);
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rtwn_write_1(sc, R12A_RF_B_CTRL,
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R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB |
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R92C_RF_CTRL_SDMRSTB);
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}
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int
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r12a_power_on(struct rtwn_softc *sc)
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{
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#define RTWN_CHK(res) do { \
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if (res != 0) \
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return (EIO); \
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} while(0)
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int ntries;
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r12a_rf_init_workaround(sc);
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/* Force PWM mode. */
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RTWN_CHK(rtwn_setbits_1(sc, R92C_SPS0_CTRL + 1, 0, 0x01));
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/* Turn off ZCD. */
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RTWN_CHK(rtwn_setbits_2(sc, 0x014, 0x0180, 0));
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/* Enable LDO normal mode. */
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RTWN_CHK(rtwn_setbits_1(sc, R92C_LPLDO_CTRL, R92C_LPLDO_CTRL_SLEEP,
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0));
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/* GPIO 0...7 input mode. */
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RTWN_CHK(rtwn_write_1(sc, R92C_GPIO_IOSEL, 0));
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/* GPIO 11...8 input mode. */
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RTWN_CHK(rtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0));
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/* Enable WL suspend. */
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RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
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R92C_APS_FSMCO_AFSM_HSUS, 0, 1));
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/* Enable 8051. */
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RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN,
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0, R92C_SYS_FUNC_EN_CPUEN, 1));
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/* Disable SW LPS. */
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RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
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R92C_APS_FSMCO_APFM_RSM, 0, 1));
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/* Wait for power ready bit. */
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for (ntries = 0; ntries < 5000; ntries++) {
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if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
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break;
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rtwn_delay(sc, 10);
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}
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if (ntries == 5000) {
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device_printf(sc->sc_dev,
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"timeout waiting for chip power up\n");
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return (ETIMEDOUT);
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}
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/* Disable WL suspend. */
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RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
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R92C_APS_FSMCO_AFSM_HSUS, 0, 1));
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RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
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R92C_APS_FSMCO_APFM_ONMAC, 1));
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for (ntries = 0; ntries < 5000; ntries++) {
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if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
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R92C_APS_FSMCO_APFM_ONMAC))
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break;
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rtwn_delay(sc, 10);
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}
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if (ntries == 5000)
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return (ETIMEDOUT);
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/* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
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RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0x0000));
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RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
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R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN |
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R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN |
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R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN |
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((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
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R92C_CR_CALTMR_EN));
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return (0);
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}
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void
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r12a_power_off(struct rtwn_softc *sc)
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{
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struct r12a_softc *rs = sc->sc_priv;
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int error, ntries;
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/* Stop Rx. */
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error = rtwn_write_1(sc, R92C_CR, 0);
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if (error == ENXIO) /* hardware gone */
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return;
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/* Move card to Low Power state. */
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/* Block all Tx queues. */
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rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
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for (ntries = 0; ntries < 10; ntries++) {
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/* Should be zero if no packet is transmitting. */
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if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0)
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break;
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rtwn_delay(sc, 5000);
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}
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if (ntries == 10) {
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device_printf(sc->sc_dev, "%s: failed to block Tx queues\n",
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__func__);
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return;
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}
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/* Turn off 3-wire. */
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rtwn_write_1(sc, R12A_HSSI_PARAM1(0), 0x04);
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rtwn_write_1(sc, R12A_HSSI_PARAM1(1), 0x04);
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/* CCK and OFDM are disabled, and clock are gated. */
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rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0);
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rtwn_delay(sc, 1);
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/* Reset whole BB. */
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rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
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/* Reset MAC TRX. */
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rtwn_write_1(sc, R92C_CR,
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R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN);
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/* check if removed later. (?) */
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rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
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/* Respond TxOK to scheduler */
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rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, R92C_DUAL_TSF_RST_TXOK);
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/* If firmware in ram code, do reset. */
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#ifndef RTWN_WITHOUT_UCODE
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if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL)
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r12a_fw_reset(sc, RTWN_FW_RESET_SHUTDOWN);
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#endif
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/* Reset MCU. */
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rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_CPUEN,
|
||
|
0, 1);
|
||
|
rtwn_write_1(sc, R92C_MCUFWDL, 0);
|
||
|
|
||
|
/* Move card to Disabled state. */
|
||
|
/* Turn off 3-wire. */
|
||
|
rtwn_write_1(sc, R12A_HSSI_PARAM1(0), 0x04);
|
||
|
rtwn_write_1(sc, R12A_HSSI_PARAM1(1), 0x04);
|
||
|
|
||
|
/* Reset BB, close RF. */
|
||
|
rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
|
||
|
|
||
|
rtwn_delay(sc, 1);
|
||
|
|
||
|
/* SPS PWM mode. */
|
||
|
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0xff,
|
||
|
R92C_APS_FSMCO_SOP_RCK | R92C_APS_FSMCO_SOP_ABG, 3);
|
||
|
|
||
|
/* ANA clock = 500k. */
|
||
|
rtwn_setbits_1(sc, R92C_SYS_CLKR, R92C_SYS_CLKR_ANA8M, 0);
|
||
|
|
||
|
/* Turn off MAC by HW state machine */
|
||
|
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_APFM_OFF,
|
||
|
1);
|
||
|
for (ntries = 0; ntries < 10; ntries++) {
|
||
|
/* Wait until it will be disabled. */
|
||
|
if ((rtwn_read_2(sc, R92C_APS_FSMCO) &
|
||
|
R92C_APS_FSMCO_APFM_OFF) == 0)
|
||
|
break;
|
||
|
|
||
|
rtwn_delay(sc, 5000);
|
||
|
}
|
||
|
if (ntries == 10) {
|
||
|
device_printf(sc->sc_dev, "%s: could not turn off MAC\n",
|
||
|
__func__);
|
||
|
return;
|
||
|
}
|
||
|
|
||
|
/* Reset 8051. */
|
||
|
rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_CPUEN,
|
||
|
0, 1);
|
||
|
|
||
|
/* Fill the default value of host_CPU handshake field. */
|
||
|
rtwn_write_1(sc, R92C_MCUFWDL,
|
||
|
R92C_MCUFWDL_EN | R92C_MCUFWDL_CHKSUM_RPT);
|
||
|
|
||
|
rtwn_setbits_1(sc, R92C_GPIO_IO_SEL, 0xf0, 0xc0);
|
||
|
|
||
|
/* GPIO 11 input mode, 10...8 output mode. */
|
||
|
rtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0x07);
|
||
|
|
||
|
/* GPIO 7...0, output = input */
|
||
|
rtwn_write_1(sc, R92C_GPIO_OUT, 0);
|
||
|
|
||
|
/* GPIO 7...0 output mode. */
|
||
|
rtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff);
|
||
|
|
||
|
rtwn_write_1(sc, R92C_GPIO_MOD, 0);
|
||
|
|
||
|
/* Turn on ZCD. */
|
||
|
rtwn_setbits_2(sc, 0x014, 0, 0x0180);
|
||
|
|
||
|
/* Force PFM mode. */
|
||
|
rtwn_setbits_1(sc, R92C_SPS0_CTRL + 1, 0x01, 0);
|
||
|
|
||
|
/* LDO sleep mode. */
|
||
|
rtwn_setbits_1(sc, R92C_LPLDO_CTRL, 0, R92C_LPLDO_CTRL_SLEEP);
|
||
|
|
||
|
/* ANA clock = 500k. */
|
||
|
rtwn_setbits_1(sc, R92C_SYS_CLKR, R92C_SYS_CLKR_ANA8M, 0);
|
||
|
|
||
|
/* SOP option to disable BG/MB. */
|
||
|
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0xff,
|
||
|
R92C_APS_FSMCO_SOP_RCK, 3);
|
||
|
|
||
|
/* Disable RFC_0. */
|
||
|
rtwn_setbits_1(sc, R92C_RF_CTRL, R92C_RF_CTRL_RSTB, 0);
|
||
|
|
||
|
/* Disable RFC_1. */
|
||
|
rtwn_setbits_1(sc, R12A_RF_B_CTRL, R92C_RF_CTRL_RSTB, 0);
|
||
|
|
||
|
/* Enable WL suspend. */
|
||
|
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_AFSM_HSUS,
|
||
|
1);
|
||
|
|
||
|
rs->rs_flags &= ~R12A_IQK_RUNNING;
|
||
|
}
|
||
|
|
||
|
void
|
||
|
r12a_init_intr(struct rtwn_softc *sc)
|
||
|
{
|
||
|
rtwn_write_4(sc, R88E_HIMR, 0);
|
||
|
rtwn_write_4(sc, R88E_HIMRE, 0);
|
||
|
}
|
||
|
|
||
|
void
|
||
|
r12a_init_antsel(struct rtwn_softc *sc)
|
||
|
{
|
||
|
uint32_t reg;
|
||
|
|
||
|
rtwn_write_1(sc, R92C_LEDCFG2, 0x82);
|
||
|
rtwn_bb_setbits(sc, R92C_FPGA0_RFPARAM(0), 0, 0x2000);
|
||
|
reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0));
|
||
|
sc->sc_ant = MS(reg, R92C_FPGA0_RFIFACEOE0_ANT);
|
||
|
}
|