2002-04-27 20:47:57 +00:00
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/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
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*
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* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
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* Copyright 2000 VA Linux Systems, Inc., Fremont, California.
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* All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Kevin E. Martin <martin@valinux.com>
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* Gareth Hughes <gareth@valinux.com>
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*
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* $FreeBSD$
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*/
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#ifndef __RADEON_DRV_H__
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#define __RADEON_DRV_H__
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typedef struct drm_radeon_freelist {
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unsigned int age;
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drm_buf_t *buf;
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struct drm_radeon_freelist *next;
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struct drm_radeon_freelist *prev;
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} drm_radeon_freelist_t;
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typedef struct drm_radeon_ring_buffer {
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u32 *start;
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u32 *end;
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int size;
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int size_l2qw;
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volatile u32 *head;
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u32 tail;
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u32 tail_mask;
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int space;
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int high_mark;
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} drm_radeon_ring_buffer_t;
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typedef struct drm_radeon_depth_clear_t {
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u32 rb3d_cntl;
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u32 rb3d_zstencilcntl;
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u32 se_cntl;
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} drm_radeon_depth_clear_t;
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typedef struct drm_radeon_private {
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drm_radeon_ring_buffer_t ring;
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drm_radeon_sarea_t *sarea_priv;
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int agp_size;
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u32 agp_vm_start;
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unsigned long agp_buffers_offset;
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int cp_mode;
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int cp_running;
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drm_radeon_freelist_t *head;
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drm_radeon_freelist_t *tail;
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/* FIXME: ROTATE_BUFS is a hask to cycle through bufs until freelist
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code is used. Note this hides a problem with the scratch register
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(used to keep track of last buffer completed) being written to before
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the last buffer has actually completed rendering. */
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#define ROTATE_BUFS 1
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#if ROTATE_BUFS
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int last_buf;
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#endif
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volatile u32 *scratch;
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int usec_timeout;
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int is_pci;
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unsigned long phys_pci_gart;
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#if __REALLY_HAVE_SG
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dma_addr_t bus_pci_gart;
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#endif
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atomic_t idle_count;
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int page_flipping;
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int current_page;
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u32 crtc_offset;
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u32 crtc_offset_cntl;
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u32 color_fmt;
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unsigned int front_offset;
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unsigned int front_pitch;
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unsigned int back_offset;
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unsigned int back_pitch;
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u32 depth_fmt;
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unsigned int depth_offset;
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unsigned int depth_pitch;
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u32 front_pitch_offset;
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u32 back_pitch_offset;
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u32 depth_pitch_offset;
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drm_radeon_depth_clear_t depth_clear;
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drm_map_t *sarea;
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drm_map_t *fb;
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drm_map_t *mmio;
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drm_map_t *cp_ring;
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drm_map_t *ring_rptr;
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drm_map_t *buffers;
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drm_map_t *agp_textures;
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} drm_radeon_private_t;
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typedef struct drm_radeon_buf_priv {
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u32 age;
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int prim;
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int discard;
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int dispatched;
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drm_radeon_freelist_t *list_entry;
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} drm_radeon_buf_priv_t;
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/* radeon_cp.c */
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extern int radeon_cp_init( DRM_OS_IOCTL );
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extern int radeon_cp_start( DRM_OS_IOCTL );
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extern int radeon_cp_stop( DRM_OS_IOCTL );
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extern int radeon_cp_reset( DRM_OS_IOCTL );
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extern int radeon_cp_idle( DRM_OS_IOCTL );
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extern int radeon_engine_reset( DRM_OS_IOCTL );
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extern int radeon_fullscreen( DRM_OS_IOCTL );
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extern int radeon_cp_buffers( DRM_OS_IOCTL );
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extern void radeon_freelist_reset( drm_device_t *dev );
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extern drm_buf_t *radeon_freelist_get( drm_device_t *dev );
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extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n );
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static __inline__ void
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radeon_update_ring_snapshot( drm_radeon_ring_buffer_t *ring )
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{
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ring->space = (*(volatile int *)ring->head - ring->tail) * sizeof(u32);
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if ( ring->space <= 0 )
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ring->space += ring->size;
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}
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extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv );
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extern int radeon_do_cleanup_cp( drm_device_t *dev );
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extern int radeon_do_cleanup_pageflip( drm_device_t *dev );
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/* radeon_state.c */
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extern int radeon_cp_clear( DRM_OS_IOCTL );
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extern int radeon_cp_swap( DRM_OS_IOCTL );
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extern int radeon_cp_vertex( DRM_OS_IOCTL );
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extern int radeon_cp_indices( DRM_OS_IOCTL );
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extern int radeon_cp_texture( DRM_OS_IOCTL );
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extern int radeon_cp_stipple( DRM_OS_IOCTL );
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extern int radeon_cp_indirect( DRM_OS_IOCTL );
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/* Register definitions, register access macros and drmAddMap constants
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* for Radeon kernel driver.
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*/
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#define RADEON_AGP_COMMAND 0x0f60
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#define RADEON_AUX_SCISSOR_CNTL 0x26f0
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# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
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# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
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# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
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# define RADEON_SCISSOR_0_ENABLE (1 << 28)
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# define RADEON_SCISSOR_1_ENABLE (1 << 29)
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# define RADEON_SCISSOR_2_ENABLE (1 << 30)
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#define RADEON_BUS_CNTL 0x0030
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# define RADEON_BUS_MASTER_DIS (1 << 6)
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#define RADEON_CLOCK_CNTL_DATA 0x000c
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# define RADEON_PLL_WR_EN (1 << 7)
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#define RADEON_CLOCK_CNTL_INDEX 0x0008
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#define RADEON_CONFIG_APER_SIZE 0x0108
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#define RADEON_CRTC_OFFSET 0x0224
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#define RADEON_CRTC_OFFSET_CNTL 0x0228
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# define RADEON_CRTC_TILE_EN (1 << 15)
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# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
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#define RADEON_RB3D_COLORPITCH 0x1c48
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#define RADEON_RB3D_DEPTHCLEARVALUE 0x1c30
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#define RADEON_RB3D_DEPTHXY_OFFSET 0x1c60
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#define RADEON_DP_GUI_MASTER_CNTL 0x146c
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# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
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# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
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# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
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# define RADEON_GMC_BRUSH_NONE (15 << 4)
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# define RADEON_GMC_DST_16BPP (4 << 8)
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# define RADEON_GMC_DST_24BPP (5 << 8)
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# define RADEON_GMC_DST_32BPP (6 << 8)
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# define RADEON_GMC_DST_DATATYPE_SHIFT 8
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# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
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# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
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# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
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# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
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# define RADEON_GMC_WR_MSK_DIS (1 << 30)
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# define RADEON_ROP3_S 0x00cc0000
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# define RADEON_ROP3_P 0x00f00000
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#define RADEON_DP_WRITE_MASK 0x16cc
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#define RADEON_DST_PITCH_OFFSET 0x142c
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#define RADEON_DST_PITCH_OFFSET_C 0x1c80
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# define RADEON_DST_TILE_LINEAR (0 << 30)
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# define RADEON_DST_TILE_MACRO (1 << 30)
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# define RADEON_DST_TILE_MICRO (2 << 30)
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# define RADEON_DST_TILE_BOTH (3 << 30)
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#define RADEON_SCRATCH_REG0 0x15e0
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#define RADEON_SCRATCH_REG1 0x15e4
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#define RADEON_SCRATCH_REG2 0x15e8
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#define RADEON_SCRATCH_REG3 0x15ec
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#define RADEON_SCRATCH_REG4 0x15f0
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#define RADEON_SCRATCH_REG5 0x15f4
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#define RADEON_SCRATCH_UMSK 0x0770
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#define RADEON_SCRATCH_ADDR 0x0774
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#define RADEON_HOST_PATH_CNTL 0x0130
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# define RADEON_HDP_SOFT_RESET (1 << 26)
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# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
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# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
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#define RADEON_ISYNC_CNTL 0x1724
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# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
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# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
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# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
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# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
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# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
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# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
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#define RADEON_MC_AGP_LOCATION 0x014c
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#define RADEON_MC_FB_LOCATION 0x0148
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#define RADEON_MCLK_CNTL 0x0012
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# define RADEON_FORCEON_MCLKA (1 << 16)
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# define RADEON_FORCEON_MCLKB (1 << 17)
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# define RADEON_FORCEON_YCLKA (1 << 18)
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# define RADEON_FORCEON_YCLKB (1 << 19)
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# define RADEON_FORCEON_MC (1 << 20)
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# define RADEON_FORCEON_AIC (1 << 21)
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#define RADEON_PP_BORDER_COLOR_0 0x1d40
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#define RADEON_PP_BORDER_COLOR_1 0x1d44
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#define RADEON_PP_BORDER_COLOR_2 0x1d48
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#define RADEON_PP_CNTL 0x1c38
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# define RADEON_SCISSOR_ENABLE (1 << 1)
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#define RADEON_PP_LUM_MATRIX 0x1d00
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#define RADEON_PP_MISC 0x1c14
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#define RADEON_PP_ROT_MATRIX_0 0x1d58
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#define RADEON_PP_TXFILTER_0 0x1c54
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#define RADEON_PP_TXFILTER_1 0x1c6c
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#define RADEON_PP_TXFILTER_2 0x1c84
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#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
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# define RADEON_RB2D_DC_FLUSH (3 << 0)
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# define RADEON_RB2D_DC_FREE (3 << 2)
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# define RADEON_RB2D_DC_FLUSH_ALL 0xf
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# define RADEON_RB2D_DC_BUSY (1 << 31)
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#define RADEON_RB3D_CNTL 0x1c3c
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# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
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# define RADEON_PLANE_MASK_ENABLE (1 << 1)
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# define RADEON_DITHER_ENABLE (1 << 2)
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# define RADEON_ROUND_ENABLE (1 << 3)
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# define RADEON_SCALE_DITHER_ENABLE (1 << 4)
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# define RADEON_DITHER_INIT (1 << 5)
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# define RADEON_ROP_ENABLE (1 << 6)
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# define RADEON_STENCIL_ENABLE (1 << 7)
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# define RADEON_Z_ENABLE (1 << 8)
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# define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9)
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# define RADEON_ZBLOCK8 (0 << 15)
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# define RADEON_ZBLOCK16 (1 << 15)
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#define RADEON_RB3D_DEPTHOFFSET 0x1c24
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#define RADEON_RB3D_PLANEMASK 0x1d84
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#define RADEON_RB3D_STENCILREFMASK 0x1d7c
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#define RADEON_RB3D_ZCACHE_MODE 0x3250
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#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
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# define RADEON_RB3D_ZC_FLUSH (1 << 0)
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# define RADEON_RB3D_ZC_FREE (1 << 2)
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# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
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# define RADEON_RB3D_ZC_BUSY (1 << 31)
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#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
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# define RADEON_Z_TEST_MASK (7 << 4)
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# define RADEON_Z_TEST_ALWAYS (7 << 4)
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# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
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# define RADEON_STENCIL_S_FAIL_KEEP (0 << 16)
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# define RADEON_STENCIL_ZPASS_KEEP (0 << 20)
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# define RADEON_STENCIL_ZFAIL_KEEP (0 << 20)
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# define RADEON_Z_WRITE_ENABLE (1 << 30)
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#define RADEON_RBBM_SOFT_RESET 0x00f0
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# define RADEON_SOFT_RESET_CP (1 << 0)
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# define RADEON_SOFT_RESET_HI (1 << 1)
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# define RADEON_SOFT_RESET_SE (1 << 2)
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# define RADEON_SOFT_RESET_RE (1 << 3)
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# define RADEON_SOFT_RESET_PP (1 << 4)
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# define RADEON_SOFT_RESET_E2 (1 << 5)
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# define RADEON_SOFT_RESET_RB (1 << 6)
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# define RADEON_SOFT_RESET_HDP (1 << 7)
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#define RADEON_RBBM_STATUS 0x0e40
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# define RADEON_RBBM_FIFOCNT_MASK 0x007f
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# define RADEON_RBBM_ACTIVE (1 << 31)
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#define RADEON_RE_LINE_PATTERN 0x1cd0
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#define RADEON_RE_MISC 0x26c4
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#define RADEON_RE_TOP_LEFT 0x26c0
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#define RADEON_RE_WIDTH_HEIGHT 0x1c44
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#define RADEON_RE_STIPPLE_ADDR 0x1cc8
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#define RADEON_RE_STIPPLE_DATA 0x1ccc
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#define RADEON_SCISSOR_TL_0 0x1cd8
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#define RADEON_SCISSOR_BR_0 0x1cdc
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#define RADEON_SCISSOR_TL_1 0x1ce0
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#define RADEON_SCISSOR_BR_1 0x1ce4
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#define RADEON_SCISSOR_TL_2 0x1ce8
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#define RADEON_SCISSOR_BR_2 0x1cec
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#define RADEON_SE_COORD_FMT 0x1c50
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#define RADEON_SE_CNTL 0x1c4c
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# define RADEON_FFACE_CULL_CW (0 << 0)
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# define RADEON_BFACE_SOLID (3 << 1)
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# define RADEON_FFACE_SOLID (3 << 3)
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# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
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# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
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# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
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# define RADEON_ALPHA_SHADE_FLAT (1 << 10)
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# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
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# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
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# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
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# define RADEON_FOG_SHADE_FLAT (1 << 14)
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# define RADEON_FOG_SHADE_GOURAUD (2 << 14)
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# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
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# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
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# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
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# define RADEON_ROUND_MODE_TRUNC (0 << 28)
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# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
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#define RADEON_SE_CNTL_STATUS 0x2140
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#define RADEON_SE_LINE_WIDTH 0x1db8
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#define RADEON_SE_VPORT_XSCALE 0x1d98
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#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
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#define RADEON_SURFACE_ACCESS_CLR 0x0bfc
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#define RADEON_SURFACE_CNTL 0x0b00
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|
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# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
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# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
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# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
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# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
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# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
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# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
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|
# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
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|
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# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
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|
# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
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|
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#define RADEON_SURFACE0_INFO 0x0b0c
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|
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# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
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|
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# define RADEON_SURF_TILE_MODE_MASK (3 << 16)
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|
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# define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
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# define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
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|
|
# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
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|
|
# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
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|
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#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
|
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|
|
#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
|
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|
|
#define RADEON_SURFACE1_INFO 0x0b1c
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|
|
#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
|
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|
|
#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
|
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|
|
#define RADEON_SURFACE2_INFO 0x0b2c
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|
|
#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
|
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|
|
#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
|
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|
|
#define RADEON_SURFACE3_INFO 0x0b3c
|
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|
|
#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
|
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|
|
#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
|
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|
|
#define RADEON_SURFACE4_INFO 0x0b4c
|
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|
|
#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
|
|
|
|
|
#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
|
|
|
|
|
#define RADEON_SURFACE5_INFO 0x0b5c
|
|
|
|
|
#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
|
|
|
|
|
#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
|
|
|
|
|
#define RADEON_SURFACE6_INFO 0x0b6c
|
|
|
|
|
#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
|
|
|
|
|
#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
|
|
|
|
|
#define RADEON_SURFACE7_INFO 0x0b7c
|
|
|
|
|
#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
|
|
|
|
|
#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
|
|
|
|
|
#define RADEON_SW_SEMAPHORE 0x013c
|
|
|
|
|
|
|
|
|
|
#define RADEON_WAIT_UNTIL 0x1720
|
|
|
|
|
# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
|
|
|
|
|
# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
|
|
|
|
|
# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
|
|
|
|
|
# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
|
|
|
|
|
|
|
|
|
|
#define RADEON_RB3D_ZMASKOFFSET 0x1c34
|
|
|
|
|
#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
|
|
|
|
|
# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
|
|
|
|
|
# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* CP registers */
|
|
|
|
|
#define RADEON_CP_ME_RAM_ADDR 0x07d4
|
|
|
|
|
#define RADEON_CP_ME_RAM_RADDR 0x07d8
|
|
|
|
|
#define RADEON_CP_ME_RAM_DATAH 0x07dc
|
|
|
|
|
#define RADEON_CP_ME_RAM_DATAL 0x07e0
|
|
|
|
|
|
|
|
|
|
#define RADEON_CP_RB_BASE 0x0700
|
|
|
|
|
#define RADEON_CP_RB_CNTL 0x0704
|
|
|
|
|
#define RADEON_CP_RB_RPTR_ADDR 0x070c
|
|
|
|
|
#define RADEON_CP_RB_RPTR 0x0710
|
|
|
|
|
#define RADEON_CP_RB_WPTR 0x0714
|
|
|
|
|
|
|
|
|
|
#define RADEON_CP_RB_WPTR_DELAY 0x0718
|
|
|
|
|
# define RADEON_PRE_WRITE_TIMER_SHIFT 0
|
|
|
|
|
# define RADEON_PRE_WRITE_LIMIT_SHIFT 23
|
|
|
|
|
|
|
|
|
|
#define RADEON_CP_IB_BASE 0x0738
|
|
|
|
|
|
|
|
|
|
#define RADEON_CP_CSQ_CNTL 0x0740
|
|
|
|
|
# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
|
|
|
|
|
# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
|
|
|
|
|
# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
|
|
|
|
|
# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
|
|
|
|
|
# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
|
|
|
|
|
# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
|
|
|
|
|
# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
|
|
|
|
|
|
|
|
|
|
#define RADEON_AIC_CNTL 0x01d0
|
|
|
|
|
# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
|
|
|
|
|
#define RADEON_AIC_STAT 0x01d4
|
|
|
|
|
#define RADEON_AIC_PT_BASE 0x01d8
|
|
|
|
|
#define RADEON_AIC_LO_ADDR 0x01dc
|
|
|
|
|
#define RADEON_AIC_HI_ADDR 0x01e0
|
|
|
|
|
#define RADEON_AIC_TLB_ADDR 0x01e4
|
|
|
|
|
#define RADEON_AIC_TLB_DATA 0x01e8
|
|
|
|
|
|
|
|
|
|
/* CP command packets */
|
|
|
|
|
#define RADEON_CP_PACKET0 0x00000000
|
|
|
|
|
# define RADEON_ONE_REG_WR (1 << 15)
|
|
|
|
|
#define RADEON_CP_PACKET1 0x40000000
|
|
|
|
|
#define RADEON_CP_PACKET2 0x80000000
|
|
|
|
|
#define RADEON_CP_PACKET3 0xC0000000
|
|
|
|
|
# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
|
|
|
|
|
# define RADEON_WAIT_FOR_IDLE 0x00002600
|
|
|
|
|
# define RADEON_3D_DRAW_IMMD 0x00002900
|
|
|
|
|
# define RADEON_3D_CLEAR_ZMASK 0x00003200
|
|
|
|
|
# define RADEON_CNTL_HOSTDATA_BLT 0x00009400
|
|
|
|
|
# define RADEON_CNTL_PAINT_MULTI 0x00009A00
|
|
|
|
|
# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
|
|
|
|
|
|
|
|
|
|
#define RADEON_CP_PACKET_MASK 0xC0000000
|
|
|
|
|
#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
|
|
|
|
|
#define RADEON_CP_PACKET0_REG_MASK 0x000007ff
|
|
|
|
|
#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
|
|
|
|
|
#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
|
|
|
|
|
|
|
|
|
|
#define RADEON_VTX_Z_PRESENT (1 << 31)
|
|
|
|
|
|
|
|
|
|
#define RADEON_PRIM_TYPE_NONE (0 << 0)
|
|
|
|
|
#define RADEON_PRIM_TYPE_POINT (1 << 0)
|
|
|
|
|
#define RADEON_PRIM_TYPE_LINE (2 << 0)
|
|
|
|
|
#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
|
|
|
|
|
#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
|
|
|
|
|
#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
|
|
|
|
|
#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
|
|
|
|
|
#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
|
|
|
|
|
#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
|
|
|
|
|
#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
|
|
|
|
|
#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
|
|
|
|
|
#define RADEON_PRIM_WALK_IND (1 << 4)
|
|
|
|
|
#define RADEON_PRIM_WALK_LIST (2 << 4)
|
|
|
|
|
#define RADEON_PRIM_WALK_RING (3 << 4)
|
|
|
|
|
#define RADEON_COLOR_ORDER_BGRA (0 << 6)
|
|
|
|
|
#define RADEON_COLOR_ORDER_RGBA (1 << 6)
|
|
|
|
|
#define RADEON_MAOS_ENABLE (1 << 7)
|
|
|
|
|
#define RADEON_VTX_FMT_R128_MODE (0 << 8)
|
|
|
|
|
#define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
|
|
|
|
|
#define RADEON_NUM_VERTICES_SHIFT 16
|
|
|
|
|
|
|
|
|
|
#define RADEON_COLOR_FORMAT_CI8 2
|
|
|
|
|
#define RADEON_COLOR_FORMAT_ARGB1555 3
|
|
|
|
|
#define RADEON_COLOR_FORMAT_RGB565 4
|
|
|
|
|
#define RADEON_COLOR_FORMAT_ARGB8888 6
|
|
|
|
|
#define RADEON_COLOR_FORMAT_RGB332 7
|
|
|
|
|
#define RADEON_COLOR_FORMAT_RGB8 9
|
|
|
|
|
#define RADEON_COLOR_FORMAT_ARGB4444 15
|
|
|
|
|
|
|
|
|
|
#define RADEON_TXFORMAT_I8 0
|
|
|
|
|
#define RADEON_TXFORMAT_AI88 1
|
|
|
|
|
#define RADEON_TXFORMAT_RGB332 2
|
|
|
|
|
#define RADEON_TXFORMAT_ARGB1555 3
|
|
|
|
|
#define RADEON_TXFORMAT_RGB565 4
|
|
|
|
|
#define RADEON_TXFORMAT_ARGB4444 5
|
|
|
|
|
#define RADEON_TXFORMAT_ARGB8888 6
|
|
|
|
|
#define RADEON_TXFORMAT_RGBA8888 7
|
|
|
|
|
|
|
|
|
|
/* Constants */
|
|
|
|
|
#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
|
|
|
|
|
|
|
|
|
|
#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
|
|
|
|
|
#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
|
|
|
|
|
#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
|
|
|
|
|
#define RADEON_LAST_DISPATCH 1
|
|
|
|
|
|
|
|
|
|
#define RADEON_MAX_VB_AGE 0x7fffffff
|
|
|
|
|
#define RADEON_MAX_VB_VERTS (0xffff)
|
|
|
|
|
|
|
|
|
|
#define RADEON_RING_HIGH_MARK 128
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#define RADEON_BASE(reg) ((unsigned long)(dev_priv->mmio->handle))
|
|
|
|
|
#define RADEON_ADDR(reg) (RADEON_BASE( reg ) + reg)
|
|
|
|
|
|
|
|
|
|
#define RADEON_DEREF(reg) *(volatile u32 *)RADEON_ADDR( reg )
|
|
|
|
|
#ifdef __alpha__
|
|
|
|
|
#define RADEON_READ(reg) (_RADEON_READ((u32 *)RADEON_ADDR( reg )))
|
|
|
|
|
static inline u32 _RADEON_READ(u32 *addr)
|
|
|
|
|
{
|
|
|
|
|
DRM_OS_READMEMORYBARRIER;
|
|
|
|
|
return *(volatile u32 *)addr;
|
|
|
|
|
}
|
|
|
|
|
#define RADEON_WRITE(reg,val) \
|
|
|
|
|
do { \
|
|
|
|
|
DRM_OS_WRITEMEMORYBARRIER; \
|
|
|
|
|
RADEON_DEREF(reg) = val; \
|
|
|
|
|
} while (0)
|
|
|
|
|
#else
|
|
|
|
|
#define RADEON_READ(reg) RADEON_DEREF( reg )
|
|
|
|
|
#define RADEON_WRITE(reg, val) do { RADEON_DEREF( reg ) = val; } while (0)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
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#define RADEON_DEREF8(reg) *(volatile u8 *)RADEON_ADDR( reg )
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#ifdef __alpha__
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#define RADEON_READ8(reg) _RADEON_READ8((u8 *)RADEON_ADDR( reg ))
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static inline u8 _RADEON_READ8(u8 *addr)
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{
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DRM_OS_READMEMORYBARRIER;
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return *(volatile u8 *)addr;
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}
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#define RADEON_WRITE8(reg,val) \
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do { \
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DRM_OS_WRITEMEMORYBARRIER; \
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RADEON_DEREF8( reg ) = val; \
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} while (0)
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#else
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#define RADEON_READ8(reg) RADEON_DEREF8( reg )
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#define RADEON_WRITE8(reg, val) do { RADEON_DEREF8( reg ) = val; } while (0)
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#endif
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#define RADEON_WRITE_PLL( addr, val ) \
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do { \
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RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
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((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
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RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
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} while (0)
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extern int RADEON_READ_PLL( drm_device_t *dev, int addr );
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#define CP_PACKET0( reg, n ) \
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(RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
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#define CP_PACKET0_TABLE( reg, n ) \
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(RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
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#define CP_PACKET1( reg0, reg1 ) \
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(RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
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#define CP_PACKET2() \
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(RADEON_CP_PACKET2)
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#define CP_PACKET3( pkt, n ) \
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(RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
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/* ================================================================
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* Engine control helper macros
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*/
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#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
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OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
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OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
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RADEON_WAIT_HOST_IDLECLEAN) ); \
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} while (0)
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#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
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OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
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OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
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RADEON_WAIT_HOST_IDLECLEAN) ); \
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} while (0)
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#define RADEON_WAIT_UNTIL_IDLE() do { \
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OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
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OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
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RADEON_WAIT_3D_IDLECLEAN | \
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RADEON_WAIT_HOST_IDLECLEAN) ); \
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} while (0)
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#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
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OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
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OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
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} while (0)
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#define RADEON_FLUSH_CACHE() do { \
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OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
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OUT_RING( RADEON_RB2D_DC_FLUSH ); \
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} while (0)
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#define RADEON_PURGE_CACHE() do { \
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OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
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OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \
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} while (0)
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#define RADEON_FLUSH_ZCACHE() do { \
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OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
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OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
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} while (0)
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#define RADEON_PURGE_ZCACHE() do { \
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OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
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OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
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} while (0)
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/* ================================================================
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* Misc helper macros
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*/
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#define LOCK_TEST_WITH_RETURN( dev ) \
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do { \
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if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || \
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2002-05-31 23:19:50 +00:00
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dev->lock.pid != DRM_OS_CURRENTPID ) { \
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DRM_ERROR( "%s called without lock held\n", __func__ ); \
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return DRM_OS_ERR(EINVAL); \
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2002-04-27 20:47:57 +00:00
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} \
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} while (0)
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#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
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do { \
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drm_radeon_ring_buffer_t *ring = &dev_priv->ring; int i; \
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if ( ring->space < ring->high_mark ) { \
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for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { \
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radeon_update_ring_snapshot( ring ); \
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if ( ring->space >= ring->high_mark ) \
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goto __ring_space_done; \
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2002-05-31 23:19:50 +00:00
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DRM_OS_DELAY( 1 ); \
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2002-04-27 20:47:57 +00:00
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} \
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DRM_ERROR( "ring space check failed!\n" ); \
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2002-05-31 23:19:50 +00:00
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return DRM_OS_ERR(EBUSY); \
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2002-04-27 20:47:57 +00:00
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} \
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__ring_space_done: \
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2002-05-31 23:19:50 +00:00
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; \
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2002-04-27 20:47:57 +00:00
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} while (0)
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#ifdef __linux__
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#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
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do { \
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drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
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if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
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int __ret = radeon_do_cp_idle( dev_priv ); \
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if ( __ret < 0 ) return __ret; \
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sarea_priv->last_dispatch = 0; \
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radeon_freelist_reset( dev ); \
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} \
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} while (0)
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#endif /* __linux__ */
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#ifdef __FreeBSD__
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#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
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do { \
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drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
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if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
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int __ret = radeon_do_cp_idle( dev_priv ); \
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if ( __ret ) return __ret; \
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sarea_priv->last_dispatch = 0; \
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radeon_freelist_reset( dev ); \
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} \
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} while (0)
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#endif /* __FreeBSD__ */
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#define RADEON_DISPATCH_AGE( age ) do { \
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OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
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OUT_RING( age ); \
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} while (0)
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#define RADEON_FRAME_AGE( age ) do { \
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OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
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OUT_RING( age ); \
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} while (0)
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#define RADEON_CLEAR_AGE( age ) do { \
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OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
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OUT_RING( age ); \
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} while (0)
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/* ================================================================
|
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|
|
* Ring control
|
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|
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*/
|
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#define radeon_flush_write_combine() DRM_OS_READMEMORYBARRIER
|
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|
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#define RADEON_VERBOSE 0
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#define RING_LOCALS int write; unsigned int mask; volatile u32 *ring;
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#define BEGIN_RING( n ) do { \
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if ( RADEON_VERBOSE ) { \
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DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
|
2002-05-31 23:19:50 +00:00
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n, __func__ ); \
|
2002-04-27 20:47:57 +00:00
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} \
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if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
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radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
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} \
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dev_priv->ring.space -= (n) * sizeof(u32); \
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ring = dev_priv->ring.start; \
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write = dev_priv->ring.tail; \
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mask = dev_priv->ring.tail_mask; \
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} while (0)
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#define ADVANCE_RING() do { \
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if ( RADEON_VERBOSE ) { \
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DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
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write, dev_priv->ring.tail ); \
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} \
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|
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radeon_flush_write_combine(); \
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dev_priv->ring.tail = write; \
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RADEON_WRITE( RADEON_CP_RB_WPTR, write ); \
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} while (0)
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#define OUT_RING( x ) do { \
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if ( RADEON_VERBOSE ) { \
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DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
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|
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(unsigned int)(x), write ); \
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} \
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ring[write++] = (x); \
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write &= mask; \
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} while (0)
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#define RADEON_PERFORMANCE_BOXES 0
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#endif /* __RADEON_DRV_H__ */
|
