Add altera_avgen(4), a generic device driver to be used by hard and soft
CPU cores on Altera FPGAs. The device driver allows memory-mapped devices
on Altera's Avalon SoC bus to be exported to userspace via device nodes.
device.hints directories dictate device name, permissible access methods,
physical address and length, and I/O alignment. Devices can be accessed
using read(2)/write(2), but also memory mapped in userspace using mmap(2).
Devices attach directly to the Nexus, as is common for embedded device
drivers; in the future something more mature might be desirable. There is
currently no facility to support directing device-originated interrupts to
userspace.
In the future, this device driver may be renamed to socgen(4), as it can
in principle also be used with other system-on-chip (SoC) busses, such as
Axi on ASICs and FPGAs. However, we have only tested it on Avalon busses
with memory-mapped ROMs, frame buffers, etc.
Sponsored by: DARPA, AFRL
2012-08-25 11:07:43 +00:00
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.\"-
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.\" Copyright (c) 2012 Robert N. M. Watson
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.\" All rights reserved.
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.\"
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.\" This software was developed by SRI International and the University of
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.\" Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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.\" ("CTSRD"), as part of the DARPA CRASH research programme.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd August 18, 2012
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.Dt ALTERA_AVGEN 4
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.Os
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.Sh NAME
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.Nm altera_avgen
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.Nd driver for generic Altera Avalon-bus-attached, memory-mapped devices
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.Sh SYNOPSIS
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.Cd "device altera_avgen"
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.Pp
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In
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.Pa /boot/device.hints :
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.Cd hint.altera_avgen.0.at="nexus0"
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.Cd hint.altera_avgen.0.maddr=0x7f00a000
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.Cd hint.altera_avgen.0.msize=20
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.Cd hint.altera_avgen.0.width=4
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.Cd hint.altera_avgen.0.fileio="rw"
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.Cd hint.altera_avgen.0.devname="berirom"
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.Sh DESCRIPTION
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The
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.Nm
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device driver provides generic support for memory-mapped devices on the
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Altera Avalon bus.
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.Pa device.hints
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entries configure the address, size, I/O disposition, and
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.Pa /dev
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device node name that will be used.
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The
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2013-10-07 16:49:53 +00:00
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.Xr open 2 ,
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.Xr read 2 ,
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|
.Xr write 2 ,
|
Add altera_avgen(4), a generic device driver to be used by hard and soft
CPU cores on Altera FPGAs. The device driver allows memory-mapped devices
on Altera's Avalon SoC bus to be exported to userspace via device nodes.
device.hints directories dictate device name, permissible access methods,
physical address and length, and I/O alignment. Devices can be accessed
using read(2)/write(2), but also memory mapped in userspace using mmap(2).
Devices attach directly to the Nexus, as is common for embedded device
drivers; in the future something more mature might be desirable. There is
currently no facility to support directing device-originated interrupts to
userspace.
In the future, this device driver may be renamed to socgen(4), as it can
in principle also be used with other system-on-chip (SoC) busses, such as
Axi on ASICs and FPGAs. However, we have only tested it on Avalon busses
with memory-mapped ROMs, frame buffers, etc.
Sponsored by: DARPA, AFRL
2012-08-25 11:07:43 +00:00
|
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|
and
|
2013-10-07 16:49:53 +00:00
|
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|
.Xr mmap 2
|
Add altera_avgen(4), a generic device driver to be used by hard and soft
CPU cores on Altera FPGAs. The device driver allows memory-mapped devices
on Altera's Avalon SoC bus to be exported to userspace via device nodes.
device.hints directories dictate device name, permissible access methods,
physical address and length, and I/O alignment. Devices can be accessed
using read(2)/write(2), but also memory mapped in userspace using mmap(2).
Devices attach directly to the Nexus, as is common for embedded device
drivers; in the future something more mature might be desirable. There is
currently no facility to support directing device-originated interrupts to
userspace.
In the future, this device driver may be renamed to socgen(4), as it can
in principle also be used with other system-on-chip (SoC) busses, such as
Axi on ASICs and FPGAs. However, we have only tested it on Avalon busses
with memory-mapped ROMs, frame buffers, etc.
Sponsored by: DARPA, AFRL
2012-08-25 11:07:43 +00:00
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|
system calls (and variations) may be used on
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.Nm
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device nodes, subject to constraints imposed using
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.Pa device.hints
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entries.
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Although reading and writing mapped memory is supported,
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.Nm
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does not currently support directing device interrupts to userspace.
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.Pp
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A number of
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.Pa device.hints
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sub-fields are available to configure
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.Nm
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device instances:
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.Bl -tag -width devunit
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.It maddr
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base physical address of the memory region to export; must be aligned to
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.Li width
|
2012-08-25 11:34:55 +00:00
|
|
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.It msize
|
Add altera_avgen(4), a generic device driver to be used by hard and soft
CPU cores on Altera FPGAs. The device driver allows memory-mapped devices
on Altera's Avalon SoC bus to be exported to userspace via device nodes.
device.hints directories dictate device name, permissible access methods,
physical address and length, and I/O alignment. Devices can be accessed
using read(2)/write(2), but also memory mapped in userspace using mmap(2).
Devices attach directly to the Nexus, as is common for embedded device
drivers; in the future something more mature might be desirable. There is
currently no facility to support directing device-originated interrupts to
userspace.
In the future, this device driver may be renamed to socgen(4), as it can
in principle also be used with other system-on-chip (SoC) busses, such as
Axi on ASICs and FPGAs. However, we have only tested it on Avalon busses
with memory-mapped ROMs, frame buffers, etc.
Sponsored by: DARPA, AFRL
2012-08-25 11:07:43 +00:00
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|
length of the memory region export; must be aligned to
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.Li width
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.It width
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Granularity at which
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.Xr read 2
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and
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.Xr write 2
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operations will be performed.
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Larger requests will be broken down into
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.Li width -sized
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operations; smaller requests will be rejected.
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I/O operations must be aligned to
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.Li width .
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.It fileio
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allowed file descriptor operations;
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.Li r
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authorizes
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.Xr read 2 ;
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.Li w
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authorizes
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.Xr write 2 .
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.It mmapio
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allowed
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.Xr mmap 2
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permissions;
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.Li w
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authorizes
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.Dv PROT_WRITE ;
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.Li r
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authorizes
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.Dv PROT_READ ;
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.Li x
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authorizes
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.Dv PROT_EXEC .
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.It devname
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specifies a device name relative to
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.Pa /dev .
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.It devunit
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specifies a device unit number; no unit number is used if this is unspecified.
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.El
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.Sh SEE ALSO
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.Xr mmap 2 ,
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.Xr open 2 ,
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.Xr read 2 ,
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.Xr write 2
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|
.Sh HISTORY
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|
The
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.Nm
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|
|
device driver first appeared in
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.Fx 10.0 .
|
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.Sh AUTHORS
|
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|
The
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.Nm
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|
|
|
|
device driver and this manual page were
|
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|
|
developed by SRI International and the University of Cambridge Computer
|
|
|
|
|
Laboratory under DARPA/AFRL contract
|
|
|
|
|
.Pq FA8750-10-C-0237
|
|
|
|
|
.Pq Do CTSRD Dc ,
|
|
|
|
|
as part of the DARPA CRASH research programme.
|
|
|
|
|
This device driver was written by
|
|
|
|
|
.An Robert N. M. Watson .
|
|
|
|
|
.Sh BUGS
|
|
|
|
|
.Nm
|
|
|
|
|
is intended to support the writing of userspace device drivers; however, it
|
|
|
|
|
does not permit directing interrupts to userspace, only memory-mapped I/O.
|
|
|
|
|
.Pp
|
|
|
|
|
.Nm
|
|
|
|
|
supports only a
|
|
|
|
|
.Li nexus
|
|
|
|
|
bus attachment, which is appropriate for system-on-chip busses such as
|
|
|
|
|
Altera's Avalon bus.
|
|
|
|
|
If the target device is off of another bus type, then additional bus
|
|
|
|
|
attachments will be required.
|
