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freebsd-nq/sys/amd64/isa/icu_ipl.S

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Split vector.s into UP and SMP specific files: - vector.s <- stub called by i386/exception.s - icu_vector.s <- UP - apic_vector.s <- SMP Split icu.s into UP and SMP specific files: - ipl.s <- stub called by i386/exception.s (formerly icu.s) - icu_ipl.s <- UP - apic_ipl.s <- SMP This was done in preparation for massive changes to the SMP INTerrupt mechanisms. More fine tuning, such as merging ipl.s into exception.s, may be appropriate.
1997-05-26 17:58:27 +00:00
/*-
* Copyright (c) 1989, 1990 William F. Jolitz.
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* William Jolitz.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
$Id$ -> $FreeBSD$
1999-08-28 01:08:13 +00:00
* $FreeBSD$
Split vector.s into UP and SMP specific files: - vector.s <- stub called by i386/exception.s - icu_vector.s <- UP - apic_vector.s <- SMP Split icu.s into UP and SMP specific files: - ipl.s <- stub called by i386/exception.s (formerly icu.s) - icu_ipl.s <- UP - apic_ipl.s <- SMP This was done in preparation for massive changes to the SMP INTerrupt mechanisms. More fine tuning, such as merging ipl.s into exception.s, may be appropriate.
1997-05-26 17:58:27 +00:00
*/
.data
ALIGN_DATA
The last of the encapsolation of cpl/spl/ipending things into a critical region protected by the simplelock 'cpl_lock'. Notes: - this code is currently controlled on a section by section basis with defines in machine/param.h. All sections are currently enabled. - this code is not as clean as I would like, but that can wait till later. - the "giant lock" still surrounds most instances of this "cpl region". I still have to do the code that arbitrates setting cpl between the top and bottom halves of the kernel. - the possibility of deadlock exists, I am committing the code at this point so as to exercise it and detect any such cases B4 the "giant lock" is removed.
1997-08-24 00:05:37 +00:00
/* interrupt mask enable (all h/w off) */
Remove the leading underscore from all symbols defined in x86 asm and used in C or vice versa. The elf compiler uses the same names for both. Remove asnames.h with great prejudice; it has served its purpose. Note that this does not affect the ability to generate an aout kernel due to gcc's -mno-underscores option. moral support from: peter, jhb
2001-02-25 06:29:04 +00:00
.globl imen
imen: .long HWI_MASK
The last of the encapsolation of cpl/spl/ipending things into a critical region protected by the simplelock 'cpl_lock'. Notes: - this code is currently controlled on a section by section basis with defines in machine/param.h. All sections are currently enabled. - this code is not as clean as I would like, but that can wait till later. - the "giant lock" still surrounds most instances of this "cpl region". I still have to do the code that arbitrates setting cpl between the top and bottom halves of the kernel. - the possibility of deadlock exists, I am committing the code at this point so as to exercise it and detect any such cases B4 the "giant lock" is removed.
1997-08-24 00:05:37 +00:00
Split vector.s into UP and SMP specific files: - vector.s <- stub called by i386/exception.s - icu_vector.s <- UP - apic_vector.s <- SMP Split icu.s into UP and SMP specific files: - ipl.s <- stub called by i386/exception.s (formerly icu.s) - icu_ipl.s <- UP - apic_ipl.s <- SMP This was done in preparation for massive changes to the SMP INTerrupt mechanisms. More fine tuning, such as merging ipl.s into exception.s, may be appropriate.
1997-05-26 17:58:27 +00:00
.text
SUPERALIGN_TEXT
Cleanup some leftover lint from the old interrupt system. Also, while here, run up to 32 interrupt sources on APIC systems. Normalize INTREN/INTRDIS so they are the same on both UP and SMP systems rather than sometimes a macro, and sometimes a function. Reviewed by: jhb, jakeb
2000-12-04 21:15:14 +00:00
#ifdef PC98
#define MASK_OFFSET 2
#else
#define MASK_OFFSET 1
#endif
Split vector.s into UP and SMP specific files: - vector.s <- stub called by i386/exception.s - icu_vector.s <- UP - apic_vector.s <- SMP Split icu.s into UP and SMP specific files: - ipl.s <- stub called by i386/exception.s (formerly icu.s) - icu_ipl.s <- UP - apic_ipl.s <- SMP This was done in preparation for massive changes to the SMP INTerrupt mechanisms. More fine tuning, such as merging ipl.s into exception.s, may be appropriate.
1997-05-26 17:58:27 +00:00
Cleanup some leftover lint from the old interrupt system. Also, while here, run up to 32 interrupt sources on APIC systems. Normalize INTREN/INTRDIS so they are the same on both UP and SMP systems rather than sometimes a macro, and sometimes a function. Reviewed by: jhb, jakeb
2000-12-04 21:15:14 +00:00
ENTRY(INTREN)
movl 4(%esp), %eax
Implement an optimization for INTREN/INTRDIS that bde pointed out last time I tinkered around here. Since INTREN is called from the interrupt critical path now, it should not be too expensive. In this case, we look at the bits being changed to decide which 8 bit IO port to write to rather than unconditionally writing to both. I could probably have gone further and only done the write if the bits actually changed, but that seemed overkill for the usual case in interrupt threads. [an outb is rather expensive when it has to cross the ISA bus]
2001-01-15 04:18:58 +00:00
movl %eax, %ecx
Cleanup some leftover lint from the old interrupt system. Also, while here, run up to 32 interrupt sources on APIC systems. Normalize INTREN/INTRDIS so they are the same on both UP and SMP systems rather than sometimes a macro, and sometimes a function. Reviewed by: jhb, jakeb
2000-12-04 21:15:14 +00:00
notl %eax
andl %eax, imen
movl imen, %eax
Implement an optimization for INTREN/INTRDIS that bde pointed out last time I tinkered around here. Since INTREN is called from the interrupt critical path now, it should not be too expensive. In this case, we look at the bits being changed to decide which 8 bit IO port to write to rather than unconditionally writing to both. I could probably have gone further and only done the write if the bits actually changed, but that seemed overkill for the usual case in interrupt threads. [an outb is rather expensive when it has to cross the ISA bus]
2001-01-15 04:18:58 +00:00
testb %cl, %cl
je 1f
Cleanup some leftover lint from the old interrupt system. Also, while here, run up to 32 interrupt sources on APIC systems. Normalize INTREN/INTRDIS so they are the same on both UP and SMP systems rather than sometimes a macro, and sometimes a function. Reviewed by: jhb, jakeb
2000-12-04 21:15:14 +00:00
outb %al, $(IO_ICU1 + MASK_OFFSET)
Implement an optimization for INTREN/INTRDIS that bde pointed out last time I tinkered around here. Since INTREN is called from the interrupt critical path now, it should not be too expensive. In this case, we look at the bits being changed to decide which 8 bit IO port to write to rather than unconditionally writing to both. I could probably have gone further and only done the write if the bits actually changed, but that seemed overkill for the usual case in interrupt threads. [an outb is rather expensive when it has to cross the ISA bus]
2001-01-15 04:18:58 +00:00
1:
testb %ch, %ch
je 2f
Cleanup some leftover lint from the old interrupt system. Also, while here, run up to 32 interrupt sources on APIC systems. Normalize INTREN/INTRDIS so they are the same on both UP and SMP systems rather than sometimes a macro, and sometimes a function. Reviewed by: jhb, jakeb
2000-12-04 21:15:14 +00:00
shrl $8, %eax
outb %al, $(IO_ICU2 + MASK_OFFSET)
Implement an optimization for INTREN/INTRDIS that bde pointed out last time I tinkered around here. Since INTREN is called from the interrupt critical path now, it should not be too expensive. In this case, we look at the bits being changed to decide which 8 bit IO port to write to rather than unconditionally writing to both. I could probably have gone further and only done the write if the bits actually changed, but that seemed overkill for the usual case in interrupt threads. [an outb is rather expensive when it has to cross the ISA bus]
2001-01-15 04:18:58 +00:00
2:
Split vector.s into UP and SMP specific files: - vector.s <- stub called by i386/exception.s - icu_vector.s <- UP - apic_vector.s <- SMP Split icu.s into UP and SMP specific files: - ipl.s <- stub called by i386/exception.s (formerly icu.s) - icu_ipl.s <- UP - apic_ipl.s <- SMP This was done in preparation for massive changes to the SMP INTerrupt mechanisms. More fine tuning, such as merging ipl.s into exception.s, may be appropriate.
1997-05-26 17:58:27 +00:00
ret
Cleanup some leftover lint from the old interrupt system. Also, while here, run up to 32 interrupt sources on APIC systems. Normalize INTREN/INTRDIS so they are the same on both UP and SMP systems rather than sometimes a macro, and sometimes a function. Reviewed by: jhb, jakeb
2000-12-04 21:15:14 +00:00
ENTRY(INTRDIS)
movl 4(%esp), %eax
Implement an optimization for INTREN/INTRDIS that bde pointed out last time I tinkered around here. Since INTREN is called from the interrupt critical path now, it should not be too expensive. In this case, we look at the bits being changed to decide which 8 bit IO port to write to rather than unconditionally writing to both. I could probably have gone further and only done the write if the bits actually changed, but that seemed overkill for the usual case in interrupt threads. [an outb is rather expensive when it has to cross the ISA bus]
2001-01-15 04:18:58 +00:00
movl %eax, %ecx
Cleanup some leftover lint from the old interrupt system. Also, while here, run up to 32 interrupt sources on APIC systems. Normalize INTREN/INTRDIS so they are the same on both UP and SMP systems rather than sometimes a macro, and sometimes a function. Reviewed by: jhb, jakeb
2000-12-04 21:15:14 +00:00
orl %eax, imen
movl imen, %eax
Implement an optimization for INTREN/INTRDIS that bde pointed out last time I tinkered around here. Since INTREN is called from the interrupt critical path now, it should not be too expensive. In this case, we look at the bits being changed to decide which 8 bit IO port to write to rather than unconditionally writing to both. I could probably have gone further and only done the write if the bits actually changed, but that seemed overkill for the usual case in interrupt threads. [an outb is rather expensive when it has to cross the ISA bus]
2001-01-15 04:18:58 +00:00
testb %cl, %cl
je 1f
Cleanup some leftover lint from the old interrupt system. Also, while here, run up to 32 interrupt sources on APIC systems. Normalize INTREN/INTRDIS so they are the same on both UP and SMP systems rather than sometimes a macro, and sometimes a function. Reviewed by: jhb, jakeb
2000-12-04 21:15:14 +00:00
outb %al, $(IO_ICU1 + MASK_OFFSET)
Implement an optimization for INTREN/INTRDIS that bde pointed out last time I tinkered around here. Since INTREN is called from the interrupt critical path now, it should not be too expensive. In this case, we look at the bits being changed to decide which 8 bit IO port to write to rather than unconditionally writing to both. I could probably have gone further and only done the write if the bits actually changed, but that seemed overkill for the usual case in interrupt threads. [an outb is rather expensive when it has to cross the ISA bus]
2001-01-15 04:18:58 +00:00
1:
testb %ch, %ch
je 2f
Cleanup some leftover lint from the old interrupt system. Also, while here, run up to 32 interrupt sources on APIC systems. Normalize INTREN/INTRDIS so they are the same on both UP and SMP systems rather than sometimes a macro, and sometimes a function. Reviewed by: jhb, jakeb
2000-12-04 21:15:14 +00:00
shrl $8, %eax
outb %al, $(IO_ICU2 + MASK_OFFSET)
Implement an optimization for INTREN/INTRDIS that bde pointed out last time I tinkered around here. Since INTREN is called from the interrupt critical path now, it should not be too expensive. In this case, we look at the bits being changed to decide which 8 bit IO port to write to rather than unconditionally writing to both. I could probably have gone further and only done the write if the bits actually changed, but that seemed overkill for the usual case in interrupt threads. [an outb is rather expensive when it has to cross the ISA bus]
2001-01-15 04:18:58 +00:00
2:
Cleanup some leftover lint from the old interrupt system. Also, while here, run up to 32 interrupt sources on APIC systems. Normalize INTREN/INTRDIS so they are the same on both UP and SMP systems rather than sometimes a macro, and sometimes a function. Reviewed by: jhb, jakeb
2000-12-04 21:15:14 +00:00
ret
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